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| SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 D D D D EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Unbuffered Output Supports 5-V VCC Operation Package Options Include Plastic Small-Outline Transistor (DBV, DCK) Packages DBV OR DCK PACKAGE (TOP VIEW) NC A GND 1 2 3 5 4 VCC Y NC - No internal connection description This single inverter gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1GU04 contains one inverter with an unbuffered output, and performs the Boolean function Y = A. The SN74LVC1GU04 is characterized for operation from -40C to 85C. FUNCTION TABLE INPUT A H L OUTPUT Y L H logic symbol A 2 4 Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) A 2 4 Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN VCC VIH VIL VI VO Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V IOH High-level output current VCC = 3 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V IOL Low-level output current VCC = 3 V VCC = 4.5 V TA Operating free-air temperature -40 IO = -100 mA IO = 100 mA 1.65 0.75 x VCC 0.25 x VCC 0 0 5.5 VCC -4 -8 -16 -24 -32 4 8 16 24 32 85 C mA mA MAX 5.5 UNIT V V V V V 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 mA IOH = -4 mA VOH VIL = 0 V IOH = -8 mA IOH = -16 mA IOH = -24 mA IOH = -32 mA IOL = 100 mA IOL = 4 mA VOL VIH= VCC IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA II ICC Ci VI = 5.5 V or GND VI = 5.5 V or GND, IO = 0 VCC 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 1.65 V 2.3 V 3V 4.5 V 0 to 5.5 V 1.65 V to 5.5 V 3.3 V 7 MIN VCC-0.1 1.2 1.9 2.4 2.3 3.8 0.1 0.45 0.3 0.4 0.55 0.55 5 10 V V TYP MAX UNIT mA mA pF VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) PARAMETER tpd FROM (INPUT) A TO (OUTPUT) Y VCC = 1.8 V 0.15 V MIN 1.3 MAX 5 VCC = 2.5 V 0.2 V MIN 1 MAX 4 VCC = 3.3 V 0.3 V MIN 1.1 MAX 3.7 VCC = 5 V 0.5 V MIN 1 MAX 3 ns UNIT operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 9 VCC = 2.5 V TYP 11 VCC = 3.3 V TYP 13 VCC = 5 V TYP 27 UNIT pF POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k 1 k S1 Open GND TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V 500 S1 6V Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT tw VCC Timing Input tsu Data Input 1.5 V VCC 1.5 V 0V th VCC 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VCC Output Control tPZL VCC Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 1.5 V 0V tPLZ VCC 1.5 V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL Input tPLH 1.5 V 1.5 V 0V tPHL Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74LVC1GU04 SINGLE INVERTER GATE SCES215D - APRIL 1999 - REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION VCC = 5 V 0.5 V 500 S1 11 V Open GND 500 From Output Under Test CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 11 V GND LOAD CIRCUIT Timing Input VCC VCC/2 0V tsu th VCC VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 0V tw VCC Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input VCC Input tPLH Output tPHL VCC/2 VCC/2 VCC/2 VCC/2 0V tPHL VOH VCC/2 VOL tPLH VOH Output VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control tPZL VCC VCC/2 VCC/2 0V tPLZ 5.5 V VCC/2 tPZH VOL + 0.3 V tPHZ VCC/2 VOH - 0.3 V VOH 0 V VOL Output Waveform 1 S1 at 11 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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