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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
D D D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages
DGG, DGV, OR DL PACKAGE (TOP VIEW)
description
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16646 can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74ALVCH16646.
Output-enable (OE) and direction-control (DIR) 28 29 inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16646 is characterized for operation from -40C to 85C.
1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1999, Texas Instruments Incorporated
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
FUNCTION TABLE INPUTS OE X X H H L L L L DIR X X X X L L H H CLKAB X H or L X X X H or L CLKBA X H or L X H or L X X SAB X X X X X X L H SBA X X X X L H X X Input Unspecified Input Input disabled Output Output Input Input DATA I/Os A1-A8 B1-B8 Unspecified Input Input Input disabled Input Input Output Output OPERATION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
Stored A data to B bus The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X H or L CLKBA H or L X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
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BUS A DIR L H
BUS A
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
logic symbol
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 56 1 55 54 2 3 29 28 30 31 27 26 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 1 1 6D 6 8 9 10 12 13 14 15 1 8 13D 14 16 17 19 20 21 23 24 1 14 12 11D 12 1 1 9 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1 7 7 5 51 1 2 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4D 52 1B1
1A1
5
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
logic diagram (positive logic)
56 1OE
1DIR 1CLKBA 1SBA 1CLKAB 1SAB
1 55 54 2 3
One of Eight Channels 1D C1 5 52 1D C1 1B1
1A1
2OE
29
To Seven Other Channels
28 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 30 31 27 26
One of Eight Channels
1D C1
2A1
15 42 1D C1 2B1
To Seven Other Channels
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 1.65 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -4 -12 -12 -24 4 12 12 24 10 ns/V mA mA V V V V MAX 3.6 UNIT V
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -40 85 C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = 0.58 V VI = 1.07 V II(hold) ( ) VI = 0.7 V VI = 1.7 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V IOZ ICC ICC Ci Control inputs VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 1.65 V 1.65 V 2.3 V 2.3 V 3V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 V 3.5 25 -25 45 -45 75 -75 500 10 40 750 A A A pF A MIN TYP MAX UNIT VCC-0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5 A V V
VOL
II
Cio A or B ports 3.3 V 8.5 pF All typical values are at VCC = 3.3 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4)
VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time CLKAB or CLKBA high or low A before CLKAB or B before CLKBA A after CLKAB or B after CLKBA MAX VCC = 2.5 V 0.2 V MIN 3.3 1.6 0.6 MAX 150 3.3 1.7 0.4 VCC = 2.7 V MIN MAX 150 3.3 1.4 0.7 VCC = 3.3 V 0.3 V MIN MAX 150 MHz ns ns ns UNIT
This information was not available at the time of publication.
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4)
PARAMETER fmax A or B tpd ten tdis ten CLKAB or CLKBA SAB or SBA OE OE DIR B or A A or B A or B A or B A or B FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN TYP VCC = 2.5 V 0.2 V MIN 150 1 1 1 1 1.6 1 1.5 4.8 5.6 6.8 6.5 5.7 7.8 6.5 MAX VCC = 2.7 V MIN 150 4.5 5.2 6.4 6.2 5 6.2 6 MAX VCC = 3.3 V 0.3 V MIN 150 1 1 1 1 1.4 1 1.1 3.9 4.5 5.3 5.1 4.7 5.1 5.3 ns ns ns ns ns MAX MHz UNIT
tdis A or B DIR This information was not available at the time of publication.
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP 39 10 VCC = 3.3 V TYP 43 12 UNIT pF
This information was not available at the time of publication.
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 0V th VCC VCC/2 0V Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 0V th VCC VCC/2 0V Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCES032E- JULY 1995 - REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input
2.7 V 1.5 V 0V tsu th 2.7 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Data Input
Output Control (low-level enabling) tPZL
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
2.7 V Input 1.5 V 1.5 V 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH 1.5 V VOL
Output Waveform 1 S1 at 6 V (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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Copyright (c) 1999, Texas Instruments Incorporated

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