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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-833C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Shrink Small-Outline (DB), Plastic Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
description
This octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation; it can interface to a 5-V system environment. The SN74LVCH244 is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVCH244 is characterized for operation from - 40C to 85C.
FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
logic symbol
1OE 1 EN 18 16 14 12
logic diagram (positive logic)
1OE 1
1A1 1A2 1A3 1A4
2 4 6 8
1Y1 1Y2 1Y3 1Y4
1A1
2
18
1Y1
1A2
4
16
1Y2
1A3 2OE 19 EN 1A4 2A1 2A2 2A3 2A4 11 13 15 17 9 7 5 3 2Y1 2Y2 2Y3 2Y4 2A1 2OE
6
14
1Y3
8
12
1Y4
19
11
9
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2Y1
2A2
13
7
2Y2
2A3
15
5
2Y3
2A4
17
3
2Y4
2
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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage data inputs Output voltage High-level High level output current Low level output current Low-level Input transition rise or fall rate High or low state 3 state VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 Operating Data retention only VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2 1.5 2 0.8 0 0 0 5.5 VCC 5.5 - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II II(hold) ( ) IOL = 12 mA IOL = 24 mA VI = 5.5 V or GND VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = VCC or GND VO = 3.6 V or 5.5 V VI = VCC or GND, One input at VCC - 0.6 V, VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3V 3V 3.6 V MIN to MAX 3.6 V 2.7 V to 3.6 V 3.3 V 3.3 V 3.1 5 75 - 75 500 10 50 10 500 A A A pF pF A MIN TYP MAX UNIT VCC - 0.2 2.2 2.4 2.2 0.2 0.4 0.55 5 A V
V
IOZ ICC Ci Co
nICC
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are measured at VCC = 3.3 V, TA = 25C.
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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis tsk(o) FROM (INPUT) A or B OE OE TO (OUTPUT) Y Y Y VCC = 3.3 V 0.3 V MIN 1.5 1.5 1.5 MAX 6.5 8 7 1 VCC = 2.7 V MIN MAX 7.5 9 8 ns ns ns UNIT
ns Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
operating characteristics, VCC = 3.3 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 33 2 UNIT pF
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SN74LVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES009 - JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS
2.7 V Timing Input 1.5 V 0V
tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V
2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPZL and tPZH are the same as ten. F. tPLZ and tPHZ are the same as tdis. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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