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1CY74FCT163646
Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered.
CY74FCT163646
SCCS058 - March 1997 - Revised March 2000
16-Bit Registered Transceiver
Functional Description
The CY74FCT163646 16-bit transceiver is a three-state, D-type register, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a HIGH logic level. Output Enable (OE) and direction pins (DIR) are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register, or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the Output Enable (OE) is Active LOW. In the isolation mode (Output Enable (OE) HIGH), A data may be stored in the B register and/or B data may be stored in the A register. The CY74FCT163646 has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The inputs and outputs were designed to be capable of being driven by 5.0V buses, allowing them to be used in mixed voltage systems as translators. The outputs are also designed with a power-off disable feature enabling them to be used in applications requiring live insertion.
Features
* Low power, pin-compatible replacement for LCX and LPT families * 5V tolerant inputs and outputs * 24 mA balanced drive outputs * Power-off disable outputs permits live insertion * Edge-rate control circuitry for reduced noise * FCT-C speed at 5.4 ns * Latch-up performance exceeds JEDEC standard no. 17 * ESD > 2000V per MIL-STD-883D, Method 3015 * Typical output skew < 250 ps * Industrial temperature range of -40C to +85C * TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) * Typical Volp (ground bounce) performance exceeds Mil Std 883D * VCC = 2.7V to 3.6V
Logic Block Diagrams
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB B REG D C 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB B REG D C
1A1
A REG D C
1B1
2A1
A REG D C
2B1
TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS
Copyright
(c) 2000, Texas Instruments Incorporated
CY74FCT163646
Pin Configuration
1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
SSOP/TSSOP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE
Pin Description
Pin Names A B CLKAB, CLKBA SAB, SBA DIR OE Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Direction Output Enable (Active LOW)
Function Table[1]
Inputs OE H H L L L L
Notes: 1. 2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care, = LOW-to-HIGH Transition The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Data I/O[2] SAB X X X X L H SBA X X L H X X A Input Output Input B Input Input
DIR X X L L H H
CLKAB H or L X X X H or L
CLKBA H or L X H or L X X
Function Isolation Store A and B Data Real Time B Data to A Bus Stored B Data to A Bus
Output Real Time A Data to Bus Stored A Data to B Bus
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CY74FCT163646
BUS A
BUS B
BUS A
BUS B
DIR L
OE L
CLKAB X
CLKBA X
SAB X
SBA L
DIR H
OE L
CLKAB X
CLKBA X
SAB L
SBA X
Real-Time Transfer Bus B to BusA
Real-Time Transfer BusA to Bus B
BUS A
BUS B
BUS A
BUS A
DIR H L X
OE L L H
CLKAB X
CLKBA X
SAB X X X
SBA X X X
DIR [3] L H
OE L L
CLKAB X H or L
CLKBA H or L X
SAB X H
SBA H X
Storage from A and/or B
Transfer Stored Data to A and/or B
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................... -55C to +125C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage Range ..................................... 0.5V to +4.6V DC Input Voltage .................................................-0.5V to +7.0V DC Output Voltage ..............................................-0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...........................-60 to +120 mA Power Dissipation .......................................................... 1.0W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015)
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Notes: 3. Cannot transfer data to A-bus and B-bus simultaneously. 4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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CY74FCT163646
Electrical Characteristics Over the Operating Range VCC=2.7V to 3.6V
Parameter VIH VIL VH VIK IIH IIL IOZH IOZL IODL IODH VOH Description Input HIGH Voltage Input LOW Voltage Input Hysteresis
[6]
Test Conditions All Inputs
Min. 2.0
Typ.[5]
Max. 5.5 0.8
Unit V V mV V A A A A mA mA V
100 VCC=Min., IIN=-18 mA VCC=Max., VI=5.5V VCC=Max., VI=GND VCC=Max., VOUT=5.5V VCC=Max., VOUT=GND VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V VCC=Min., IOH= -0.1 mA VCC=3.0V, IOH= -8 mA VCC=3.0V, IOH= -24 mA 45 -45 VCC-0.2 2.4[8] 2.0 3.0 3.0 0.2 0.3 -60 -135 0.5 -240 100 -0.7 -1.2 1 1 1 1 180 -180
Input Clamp Diode Voltage Input HIGH Current Input LOW Current High Impedance Output Current (Three-State Output pins) High Impedance Output Current (Three-State Output pins) Output LOW Dynamic Current[7] Output HIGH Dynamic Current[7] Output HIGH Voltage
VOL IOS IOFF
Output LOW Voltage Short Circuit Current[7]
VCC=Min., IOL= 0.1mA VCC=Min., IOL= 24 mA VCC=Max., VOUT=GND VCC=0V, VOUT4.5V
V mA A
Power-Off Disable
Capacitance[5] (TA = +25C, f = 1.0 MHz)
Symbol CIN COUT Description[9] Input Capacitance Output Capacitance Conditions VIN = 0V VOUT =0V Typ. 4.5 5.5 Max. 6.0 8.0 Unit pF pF
Notes: 5. Typical values are at VCC=3.3V, TA=+25C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter tests, IOS tests should be performed last. 8. VOH=VCC-0.6 V at rated current. 9. This parameter is measured at characterization but not tested.
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CY74FCT163646
Power Supply Characteristics
Parameter ICC ICC ICCD Description Quiescent Power Supply Current VCC=Max. Test Conditions VIN<0.2V VIN>VCC-0.2V VIN=VCC-0.6V[10] VIN=VCC or VIN=GND Typ.[5] 0.1 2.0 50 Max. 10 30 75 Unit A A A/MHz
Quiescent Power Supply Current VCC=Max. TTL Inputs HIGH Dynamic Power Supply Current[11] VCC=Max., Outputs Open DIR=OE=GND One-Bit Toggling 50% Duty Cycle VCC=Max.,Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND One-Bit Toggling, f1=5 MHz, 50% Duty Cycle VCC=Max., Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND Sixteen-Bits Toggling f1=2.5 MHz 50% Duty Cycle
IC
Total Power Supply Current[12]
VIN=VCC or VIN=GND VIN=VCC-0.6V or VIN=GND VIN=VCC or VIN=GND VIN=VCC-0.6V or VIN=GND
0.5 0.5
0.8 0.8
mA
2.5 2.6
3.8[13] 4.1[13]
Notes: 10. Per TTL driven input); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 12. IC IC = ICC+ICCDHNT+ICCD(f0NC /2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero = Number of clock inputs changing at f1 NC f1 = Input signal frequency = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
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CY74FCT163646
Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[14,15]
CY74FCT163646C Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW tSK(O) Description Propagation Delay Bus to Bus Output Enable Time DIR or OE to Bus Output Disable Time DIR or OE to Bus Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Set-Up Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW Output Skew[17] Min. 1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0 -- Max. 5.4 7.8 6.3 5.7 6.2 -- -- -- 0.5 Unit ns ns ns ns ns ns ns ns ns Fig. No.[16] 1, 2 1, 7, 8 1, 7, 8 1, 5 1,5 4 4 6 --
Ordering Information CY74FCT163646
Speed (ns) 5.4 Ordering Code CY74FCT163646CPACT CY74FCT163646CPVC/PVCT Package Name Z56 O56 Package Type 56-Lead (240-Mil) TSSOP 56-Lead (300-Mil) SSOP Operating Range Industrial
Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 16. See "Parameter Measurement Information" in the General Information section. 17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design.
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CY74FCT163646
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
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Copyright (c) 2000, Texas Instruments Incorporated

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