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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
D D D D D D D D
description
The 'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state. Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.
ODD/EVEN ERR PARITY NC B8 B7 B6
5 6 7 8 9
A8 A7 A6 NC VCC A5 A4
4 3 2 1 28 27 26 25 24 23 22 21 20 10 19 11 12 13 14 15 16 17 18
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down Flow-Through Architecture Optimizes PCB Layout High-Drive Outputs (-32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT657A . . . JT PACKAGE SN74ABT657A . . . DW OR NT PACKAGE (TOP VIEW)
T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY
SN54ABT657A . . . FK PACKAGE (TOP VIEW)
A3 A2 A1 NC T/R OE B1
NC - No internal connection
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high. In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, ERR is low, indicating a parity error.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
B5 GND GND NC B4 B3 B2
Copyright (c) 1997, Texas Instruments Incorporated
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
description (continued)
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT657A is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT657A is characterized for operation from -40C to 85C.
FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH INPUTS OE L L 0, 2, 4, 6, 02468 L L L L L L 1, 3, 5, 1357 L L L L Don't care H T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X I/O PARITY H L H L H L L H H L H L Z OUTPUTS ERR Z Z H L L H Z Z L H H L Z OUTPUT MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z
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POST OFFICE BOX 655303
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
logic symbol
OE T/R ODD/EVEN A1 A2 A3 A4 A5 A6 A7 A8 24 1 11 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 2k 4, 2 5 4, 1 12 ERR G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 1 Z11 1 2 22 21 20 17 16 15 14 B2 B3 B4 B5 B6 B7 B8 23 B1
13
PARITY
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages.
POST OFFICE BOX 655303
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3
SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
logic diagram (positive logic)
T/R 1
24 OE 2 A1 3 A2 4
23 22
B1
B2
A3
21
B3
A4
5
20
B4
A5
6
17
B5
A6
8
16
B6
A7
9
15
B7
A8
10
14
B8
ODD/EVEN
11
13 12
PARITY ERR
Pin numbers shown are for the DW, JT, and NT packages.
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT657A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT657A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT657A MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 0 4.5 2 0.8 VCC -24 48 5 200 -40 85 0 MAX 5.5 SN74ABT657A MIN 4.5 2 0.8 VCC -32 64 5 MAX 5.5 UNIT V V V V mA mA ns/V s/V C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZPU IOZPD IOZH IOZL Ioff ICEX IO ICC Control inputs A or B ports VCC = 0 to 5.5 V, VI = VCC or GND VCC = 2.1 V to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 2 V VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 2 V VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V, , Other inputs at VCC or GND VI or VO 4.5 V Outputs high VO = 2.5 V Outputs high Outputs low Outputs disabled Outputs enabled Outputs disabled -50 -100 VCC = 4 5 V 4.5 II = -18 mA IOH = -3 mA IOH = -3 mA IOH = -24 mA IOH = -32 mA IOL = 48 mA IOL = 64 mA 100 1 20 50 50 10 -10 100 50 -200 250 40 250 1.5 0.25 1.5 4 -50 50 -200 250 40 250 1.5 0.25 1.5 -50 1 20 50 50 10 -10 1 20 50 50 10 -10 100 50 -200 250 40 250 1.5 0.25 1.5 pF pF mA MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25C TYP MAX -1.2 2.5 3 2 2 V mV A A A A A A A mA A mA A SN54ABT657A MIN MAX -1.2 2.5 3 V SN74ABT657A MIN MAX -1.2 UNIT V
VOH
Data inputs ICC# Control inputs Ci Control inputs
VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V
Cio A or B ports 10 * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. This parameter is characterized, but not production tested. The parameters IOZH and IOZL include the input leakage current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 1 1 1.8 2.3 1.1 ODD/EVEN B PARITY PARITY, PARITY ERR ERR ERR A B PARITY A, B, ERR A, B, PARITY, or ,, , ERR 1.3 1.6 2.1 2 2.1 1.4 OE OE OE 1.7 1.8 3.3 2.4 1.8 TYP 3.2 2.8 4.8 4.9 3.3 3.4 4.7 4.9 4.8 4.9 4 4.1 4.1 6.2 4.2 4.2 MAX 4.2 3.8 6.3 6.4 4.2 4.5 6.5 6.9 6.3 6.7 5.4 5.8 5.4 7.6 5.6 6.2 SN54ABT657A MIN 1 1 1.8 2.3 1.1 1.3 1.6 2.1 2 2.1 1.4 1.7 1.8 3.3 2.4 1.8 MAX 5 4.5 8.5 8.1 5.3 5.1 8.4 8 8.1 8 6.8 6.7 6.9 9.7 6.3 8.9 SN74ABT657A MIN 1 1 1.8 2.3 1.1 1.3 1.6 2.1 2 2.1 1.4 1.7 1.8 3.3 2.4 1.8 MAX 4.6 4.3 8.1 7.7 4.9 4.9 7.9 7.8 7.7 7.5 6.5 6.5 6.6 9.2 6.2 7.8 ns ns ns ns ns ns ns ns UNIT
A or B A
B or A PARITY
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCBS192E - JANUARY 1991 - REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
LOAD CIRCUIT Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 3V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 7 V (see Note B) tPZH VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu 1.5 V th 1.5 V
3V 0V
3V 1.5 V 0V
Output Control tPZL
3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
3.5 V VOL + 0.3 V VOL
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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