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SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D - FEBRUARY 1991 - REVISED JANUARY 1999
D D D D D D D
State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25C High-Impedance State During Power Up and Power Down High-Drive Outputs (-32-mA IOH, 64-mA IOL) Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (N) and Ceramic (J) DIPs
SN54ABT126 . . . J PACKAGE SN74ABT126 . . . D, DB, OR N PACKAGE (TOP VIEW)
1OE 1A 1Y 2OE 2A 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4OE 4A 4Y 3OE 3A 3Y
SN54ABT126 . . . FK PACKAGE (TOP VIEW)
description
The 'ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
1Y NC 2OE NC 2A
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1A 1OE NC VCC 4OE 4A NC 4Y NC 3OE
NC - No internal connection A H L X OUTPUT Y H L Z
Copyright (c) 1999, Texas Instruments Incorporated
The SN54ABT126 is characterized for operation over the full military temperature range of -55C to 125C. The SN74ABT126 is characterized for operation from -40C to 85C.
FUNCTION TABLE (each buffer) INPUTS OE H H L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
2Y GND NC 3Y 3A
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SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D - FEBRUARY 1991 - REVISED JANUARY 1999
logic symbol
1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 11 8 6 EN 1 3 1Y
2Y
3Y
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, and N packages.
logic diagram (positive logic)
1OE 1A 1 2 3 3OE 1Y 3A 10 9 8
3Y
2OE 2A
4 5 6
4OE 2Y 4A
13 12 11
4Y
Pin numbers shown are for the D, DB, J, and N packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D - FEBRUARY 1991 - REVISED JANUARY 1999
recommended operating conditions (see Note 3)
SN54ABT126 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature 200 -55 125 0 4.5 2 0.8 VCC -24 48 10 200 -40 85 0 MAX 5.5 SN74ABT126 MIN 4.5 2 0.8 VCC -32 64 10 MAX 5.5 UNIT V V V V mA mA ns/V s/V C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4 5 V 4.5 VOL Vhys II IOZPU IOZPD IOZH IOZL Ioff ICEX IO ICC VCC = 4 5 V 4.5 TEST CONDITIONS II = -18 mA IOH = -3 mA IOH = -3 mA IOH = -24 mA IOH = -32 mA IOL = 48 mA IOL = 64 mA 100 VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE 0.8 V VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE 0.8 V VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5 5 V, IO = 0 5.5 V 0, VI = VCC or GND VCC = 5.5 V, One input at 3 4 V 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VI or VO 4.5 V Outputs high VO = 2.5 V Outputs high Outputs low Outputs disabled Outputs enabled Outputs disabled 3 -50 -100 1 24 0.5 1 50 50 10 -10 100 50 -200 250 30 250 1.5 50 -50 50 -200 250 30 250 1.5 50 -50 1 50 50 10 -10 1 50 50 10 -10 100 50 -200 250 30 250 1.5 50 MIN 2.5 3 2 2* 0.55 0.55* 0.55 0.55 TA = 25C TYP MAX -1.2 2.5 3 2 2 V mV A A A A A A A mA A mA A mA A pF pF SN54ABT126 MIN MAX -1.2 2.5 3 V SN74ABT126 MIN MAX -1.2 UNIT V
VOH
ICC Ci
Co VO = 2.5 V or 0.5 V 7 * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. For VCC between 2.1 V and 4 V, OE should be less than or equal to 0.5 V to ensure a low state. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D - FEBRUARY 1991 - REVISED JANUARY 1999
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 1)
PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25C MIN 1 1 1 1 1 1 TYP 2.9 2.5 4.4 4.4 3 3 MAX 4.9 5.1 5.8 5.9 5.7 5.8 SN54ABT126 MIN 1 1 1 1 1 1 MAX 7.3 5.9 5.3 6.4 6.9 7.2 SN74ABT126 MIN 1 1 1 1 1 1 MAX 6.3 5.7 6.5 6.5 6.8 6.7 ns ns ns UNIT
A
Y Y Y
OE OE
NOTE 4: Limits may vary among suppliers.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SCBS183D - FEBRUARY 1991 - REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
500 S1 7V Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open
From Output Under Test CL = 50 pF (see Note A)
LOAD CIRCUIT tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION
3V Timing Input 1.5 V 0V tsu Data Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control tPZL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZH 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING tPLZ 1.5 V tPHZ 3.5 V VOL + 0.3 V VOL 1.5 V 1.5 V 0V th 3V 1.5 V 0V
3V Input tPLH Output tPHL 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH Output 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
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Copyright (c) 1999, Texas Instruments Incorporated

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