View SCAS318B_999846.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
D D D D D D D
Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
description
This 16-bit bus transceiver and register is designed for low-voltage (3.3-V) VCC operation. The SN74LVC16646 can be used as two 8-bit transceivers or one 16-bit transceiver. The device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC16646.
1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The SN74LVC16646 is characterized for operation from - 40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X H or L CLKBA H or L X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X STORAGE FROM A, B, OR A AND B
SAB X X X
SBA X X X
OE L L
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
BUS A DIR L H
BUS A
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
logic symbol
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 56 1 55 54 2 3 29 28 30 31 27 26 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 1 1 6D 6 8 9 10 12 13 14 15 1 8 13D 14 16 17 19 20 21 23 24 1 14 12 11D 12 1 1 9 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1 7 7 5 51 1 2 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4D 52 1B1
1A1
5
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
logic diagram (positive logic)
1OE 56
1DIR 1CLKBA 1SBA 1CLKAB 1SAB
1 55 54 2 3
One of Eight Channels 1D C1 5 52 1D C1 1B1
1A1
2OE
29
To Seven Other Channels
2DIR 2CLKBA 2SBA 2CLKAB 2SAB
28 30 31 27 26
One of Eight Channels 1D C1 15 42 1D C1 2B1
2A1
To Seven Other Channels
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
FUNCTION TABLE INPUTS OE X X H H L L L L DIR X X X X L L H H CLKAB X H or L X X X H or L CLKBA X H or L X H or L X X SAB X X X X X X L H SBA X X X X L H X X Input Unspecified Input Input disabled Output Output Input Input DATA I/Os A1 THRU A8 B1 THRU B8 Unspecified Input Input Input disabled Input Input Output Output OPERATION OR FUNCTION Store A, B unspecified Store B, A unspecified Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B bus
Stored A data to B bus The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO IOH IOL t /V Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low level output current Low-level Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II II(hold) ( ) IOZ ICC Ci Control inputs A or B ports IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, Control inputs VI = VCC or GND VO = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 3 3 MIN to MAX 2.7 3 3.6 3 3.6 3.6 3.6 3 V to 3.6 V 3.3 3 7 75 -75 500 10 40 500 A A A pF pF A MIN TYP MAX UNIT VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 A V
V
nICC
Cio A or B ports 3.3 For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
VCC = 3.3 V 0.3 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time, A or B before CLKAB or CLKBA Hold time, A or B after CLKAB or CLKBA Data high or low Data high or low 0 4.5 5 0 MAX 100 VCC = 2.7 V MIN 0 4.5 5 0 MAX 80 MHz ns ns ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER fmax A or B tpd CLKAB or CLKBA SAB or SBA OE ten tdis di DIR OE DIR A or B A or B B or A A or B FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN 100 1.5 1.5 1.5 1.5 1.5 1.5 1.5 7 8.5 8.5 8 8 8.5 8.5 MAX VCC = 2.7 V MIN 80 8 9.5 9.5 9 9 9.5 9.5 ns ns ns MAX MHz UNIT
operating characteristics, VCC = 3.3 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 17 4 UNIT pF
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN74LVC16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SCAS318B - NOVEMBER 1993 - REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS Timing Input tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V
2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL VOH Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V
2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
Output Control
1.5 V
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCAS318B

	To Download SCAS318B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .