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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
D D D D D D D
EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
D, DB, OR PW PACKAGE (TOP VIEW)
1A 1B 2A 2B 2C 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 1C 1Y 3C 3B 3A 3Y
description
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC10A performs the Boolean function Y = A * B * C or Y = A + B + C in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN74LVC10A is characterized for operation from -40C to 85C.
FUNCTION TABLE (each gate) INPUTS A H L X X B H X L X C H X X L OUTPUT Y L H H H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1998, Texas Instruments Incorporated
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
logic symbol
1A 1B 1C 2A 2B 2C 3A 3B 3C 1 2 13 3 4 5 9 10 11 8 3Y 6 2Y & 12 1Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each gate (positive logic)
A B C Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 1.65 1.5 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 5.5 VCC -4 -8 -12 -24 4 8 12 24 mA V V V V MAX 3.6 UNIT V
VIH
High-level input voltage
IOH
High level output current High-level
mA
IOL
Low-level Low level output current
TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = -100 A IOH = -4 mA VOH IOH = -8 mA IOH = -12 mA 12 IOH = -24 mA IOL = 100 A VOL IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA II ICC ICC Ci VI = 5.5 V or GND VI = VCC or GND, One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 2.7 V to 3.6 V 3.3 V 5 MIN TYP MAX UNIT VCC-0.2 1.2 1.7 2.2 2.4 2.2 0.2 0.45 0.7 0.4 0.55 5 10 500 A A A pF V V
VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C.
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER tpd tsk(o) Skew between any two outputs of the same package switching in the same direction FROM (INPUT) A TO (OUTPUT) Y VCC = 1.8 V TYP 13.8 VCC = 2.5 V 0.2 V MIN 1 MAX 7.8 VCC = 2.7 V MIN MAX 5.8 VCC = 3.3 V 0.3 V MIN 1 MAX 4.9 1 ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP 9 VCC = 2.5 V TYP 10 VCC = 3.3 V TYP 11 UNIT pF
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC Open
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVC10A TRIPLE 3-INPUT POSITIVE-NAND GATE
SCAS284G - JANUARY 1993 - REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT
tw 2.7 V
Timing Input tsu Data Input 1.5 V
2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
1.5 V
1.5 V 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH
2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL
2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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