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| SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 D D D D D D Member of the Texas Instruments Widebus TM Family EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DGG OR DL PACKAGE (TOP VIEW) description This 20-bit flip-flop is designed specifically for low-voltage (3.3-V) VCC operation; it is tested at 2.5-V, 2.7-V, and 3.3-V VCC. The SN74ALVC16721's 20 flip-flops are edgetriggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored. 30 A buffered output-enable (OE) input places the 28 29 20 outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. OE Q1 Q2 GND Q3 Q4 VCC Q5 Q6 Q7 GND Q8 Q9 Q10 Q11 Q12 Q13 GND Q14 Q15 Q16 VCC Q17 Q18 GND Q19 Q20 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 CLK D1 D2 GND D3 D4 VCC D5 D6 D7 GND D8 D9 D10 D11 D12 D13 GND D14 D15 D16 VCC D17 D18 GND D19 D20 CLKEN Active bus-hold circuitry holds unused or floating data inputs at a valid logic level. The SN74ALVC16721 is available in TI's shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16721 is characterized for operation from - 40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 FUNCTION TABLE (each flip-flop) INPUTS OE L L L L H CLKEN H L L L X CLK X L or H X D X H L X X OUTPUT Q Q0 H L Q0 Z logic diagram (positive logic) OE 1 CLK 56 CLKEN 29 CE C1 2 D1 55 1D Q1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 recommended operating conditions (see Note 4) MIN VCC VIH VIL VI VO IOH Supply voltage High level input voltage High-level Low-level Low level input voltage Input voltage Output voltage High-level output current VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V IOL t /v Low-level output current Input transition rise or fall rate VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 2.3 1.7 2 0.7 0.8 VCC VCC - 12 - 12 - 24 12 12 24 10 85 ns / V C mA mA MAX 3.6 UNIT V V V V V TA Operating free-air temperature NOTE 4: Unused or floating control pins must be held high or low. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = - 100 A IOH = - 6 mA, VOH IOH = - 12 mA, IOH = - 12 mA, IOH = - 12 mA, IOH = - 24 mA, IOL = 100 A IOL = 6 mA, VOL IOL = 12 mA, IOL = 12 mA, IOL = 24 mA, VI = VCC or GND VI = 0.7 V VI = 1.7 V II(hold) ( ) VI = 0.8 V VI = 2 V VI = 0 to 3.6 V VO = VCC or GND VI = VCC or GND, VCC = 3 V to 3.6 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND IO = 0 One input at VCC - 0.6 V, TEST CONDITIONS VCC MIN to MAX VIH = 1.7 V VIH = 1.7 V VIH = 2 V VIH = 2 V VIH = 2 V VIL = 0.7 V VIL = 0.7 V VIL = 0.8 V VIL = 0.8 V 2.3 V 2.3 V 2.7 V 3V 3V MIN to MAX 2.3 V 2.3 V 2.7 V 3V 3.6 V 23V 2.3 3V 3.6 V 3.6 V 3.6 V 45 -45 75 -75 500 10 40 750 3.3 V 3.3 V 3.5 7 A A A pF pF A TA = - 40C to 85C MIN TYP MAX VCC - 0.2 2 1.7 2.2 2.4 2 0.2 0.4 0.7 0.4 0.55 5 A V V UNIT II IOZ ICC nICC Ci Cio For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. For I/O ports, the parameter IOZ includes the input-leakage current. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 and 2) VCC = 3.3 V 0.15 V MIN fclock tw tsu th Clock frequency Pulse duration, CLK high or low Setup time Hold time Data before CLK CLKEN before CLK Data after CLK CLKEN after CLK High or low High or low High or low High or low 0 3.3 4 3.4 0 0 MAX 150 VCC = 3.3 V 0.3 V MIN 0 3.3 3.6 3.1 0 0 MAX 150 VCC = 2.7 V MIN 0 3.3 3.1 2.7 0 0 MAX 150 MHz ns ns ns UNIT switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2) PARAMETER fmax tpd ten tdis FROM (INPUT) TO (OUTPUT) VCC = 2.5 V 0.2 V MIN 150 CLK OE OE Q Q Q 1 1 1 7 7.4 6.2 MAX VCC = 2.7 V MIN 150 1 1 1 5.7 6.5 5.1 MAX VCC = 3.3 V 0.3 V MIN 150 1 1 1 4.9 5.4 4.8 MAX MHz ns ns ns UNIT operating characteristics, TA = 25C PARAMETER Outputs enabled Outputs disabled TEST CONDITIONS VCC = 2.5 V 0.2 V TYP Cpd d Power dissipation capacitance CL = 50 pF pF, f = 10 MHz 55 46 VCC = 3.3 V 0.3 V TYP 59 49 pF UNIT POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 0.2 V VCC = 2.5 V 4.6 V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 4.6 V GND " LOAD CIRCUIT tw 2.3 V Timing Input tsu Data Input 1.2 V 2.3 V 1.2 V 0V th 2.3 V 1.2 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.2 V 1.2 V 0V VOLTAGE WAVEFORMS PULSE DURATION Output Control (low-level enabling) tPZL 2.3 V 1.2 V 1.2 V 0V tPLZ 2.3 V 1.2 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL 2.3 V Input tPLH 1.2 V 1.2 V 0V tPHL VOH Output 1.2 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.2 V VOL Output Waveform 1 S1 at 4.6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH 1.2 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 , tr ns, tf ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v10 v2.5 v2.5 Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCAS267A - MARCH 1993 - REVISED MAY 1995 PARAMETER MEASUREMENT INFORMATION 0.3 V VCC = 2.7 V AND 3.3 V 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND " LOAD CIRCUIT tw 2.7 V Timing Input tsu Data Input 1.5 V 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Output Control (low-level enabling) tPZL 2.7 V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL + 0.3 V VOL 2.7 V Input tPLH 1.5 V 1.5 V 0V tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 , tr ns, tf ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v10 v2.5 v2.5 Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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