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 SN74LVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS218C - JANUARY 1993 - REVISED JULY 1994
* * * *
EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
DB, DW, OR PW PACKAGE (TOP VIEW)
description
This octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation.
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
The SN74LVC245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The SN74LVC245 is characterized for operation from - 40C to 85C.
FUNCTION TABLE INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation
logic symbol
OE DIR 19 1 G3 3EN1[BA] 3EN2[AB] 1 2 18 B1
logic diagram (positive logic)
DIR 1 19
OE
A1
2
A1
2
A2 A3 A4 A5 A6 A7 A8
3 4 5 6 7 8 9
17 16 15 14 13 12 11
B2 B3 B4 B5 B6 B7 B8 To Seven Other Channels
18
B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN74LVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS218C - JANUARY 1993 - REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI: except I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 4.6 V maximum. 2. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature# SCBD002B.
recommended operating conditions (see Note 3)
MIN VCC VIH VIL VI VO IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V 0 - 40 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V 2.7 2 0.8 0 0 VCC VCC - 12 - 24 12 24 10 85 MAX 3.6 UNIT V V V V V mA mA ns / V C
TA Operating free-air temperature NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS218C - JANUARY 1993 - REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOH = - 100 A VOH IOH = - 12 mA IOH = - 24 mA IOL = 100 A VOL II IOZ ICC IOL = 12 mA IOL = 24 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, IO = 0 VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND Control inputs VI = VCC or GND VO = VCC or GND TEST CONDITIONS VCC MIN to MAX 2.7 V 3V 3V MIN to MAX 2.7 V 3V 3.6 V 3.6 V 3.6 V TA = - 40C to 85C MIN TYP MAX VCC - 0.2 2.2 2.4 2 0.2 0.4 0.55 5 10 20 500 3.3 V 5.5 6.7 A A A A pF pF V UNIT
V
nICC
Ci
Cio A or B ports 3.3 V For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 3.3 V 0.3 V MIN TYP MAX 1.5 1.5 1.5 4 4.5 5.5 7 9 8 VCC = 2.7 V MIN MAX 8 10 9 UNIT ns ns ns
All typical values are VCC = 3.3 V, TA = 25C.
operating characteristics, VCC = 3.3 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per transceiver Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 10 MHz TYP 25 2 UNIT pF
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN74LVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS218C - JANUARY 1993 - REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS 2.7 V Timing Input tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note C) Output Waveform 2 S1 at GND (see Note C) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V 1.5 V 0V
Input (see Note B) tPLH Output
2.7 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL
Output Control
Output
1.5 V
[0V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated


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