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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
D D D D D D
Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional 1024 Words by 9 Bits Each Programmable Almost-Full/Almost-Empty Flag Empty, Full, and Half-Full Flags
FN PACKAGE (TOP VIEW)
D D D D D D
Access Times of 25 ns With a 50-pF Load Data Rates From 0 to 50 MHz Fall-Through Times of 23 ns Max High Output Drive for Direct Bus Interface 3-State Outputs Available in 44-Pin PLCC (FN) Package
A2 A1 A0 GND DIR SBA SAB OE GND B0 B1 A3 A4 VCC A5 A6 A7 A8 GND AF/AEA HFA LDCKA
654 7 8 9 10 11 12 13 14 15 16 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 17 29 18 19 20 21 22 23 24 25 26 27 28
B2 B3 B4 VCC B5 B6 B7 B8 GND AF/AEB HFB
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT2236 is arranged as two 1024 by 9-bit FIFOs for high speed and fast access times. It processes data at rates from 0 to 50 MHz with access times of 25 ns in a bit-parallel format. The SN74ACT2236 consists of bus-transceiver circuits, two 1024 x 9 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable OE and DIR inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 shows the five fundamental bus-management functions that can be performed with the SN74ACT2236. The SN74ACT2236 is characterized for operation from 0C to 70C.
FULLA UNCKB EMPTYB DAF RSTA RSTB DBF EMPTYA UNCKA FULLB LDCKB
For more information on this device family, see the application report 1K 9 2 Asynchronous FIFOs SN74ACT2235 and SN74ACT2236 in the 1996 High-Performance FIFO Memories Designer's Handbook, literature number SCAA012A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
logic symbol
FIFO 1024 x 9 x 2 SN74ACT2236 SAB SBA OE DIR RSTA DAF LDCKA UNCKA FILLA EMPTYA AF/AEA HFA 44 1 43 2 22 21 17 26 18 25 15 16 LDCKA UNCKA FULLA EMPTYA 1 MODE 0 3EN1 [BA] 3EN2 [AB] G3 RESET A DEF A FLAG RESET B DEF B FLAG LDCKB UNCKB FULL B EMPTYB 23 24 28 19 27 20 30 29 RSTB DBF LDCKB UNCKB FULLB EMPTYB AF/AEB HFB
ALMOST-FULL/ ALMOST-FULL/ ALMOST-EMPTY A ALMOST-EMPTY B HALF-FULL A HALF-FULL B
A0 A1 A2 A3 A4 A5 A6 A7 A8
4 5 6 7 8 10 11 12 13
0
1
2
0
41 40 39 38
B0 B1 B2 B3 B4 B5 B6 B7 B8
A Data
B Data
37 35 34 33
8
8
32
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
logic diagram (positive logic)
SAB
SBA
HFB AF/AEB EMPTYB UNCKB Q
FIFO B 1024 x 9
RSTB DBF FULLB LDCKB D B0
One of Nine Channels To Other Channels
DIR OE
RSTA DAF FULLA LDCKA A0 D
FIFO A 1024 x 9
HFA AF/AEA EMPTYA UNCKA Q
One of Nine Channels To Other Channels
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
Terminal Functions
TERMINAL NAME AF/AEA, AF/AEB A0 - A8 B0 - B8 NO. I/O DESCRIPTION Almost full/almost empty flags. The almost-full/almost-empty A flag (AF/AEA) is defined by the almost-full/almost-empty offset value for FIFO A (X). AF/AEA is high when FIFO A contains X or less words or 1024 - X words. AF/AEA is low when FIFO A contains between X + 1 or 1023 - X words. The operation of the almost-full/almost-empty B flag (AF/AEB) is the same as AF/AEA for FIFO B. A data inputs and outputs B data inputs and outputs Define-flag inputs. The high-to-low transition of DAF stores the binary value on A0 - A8 as the almost-full/almost-empty offset value for FIFO A (X). The high-to-low transition of DBF stores the binary value of B0-B8 as the almost-full/almost-empty offset value for FIFO B (Y). Empty flags. EMPTYA and EMPTYB are low when their corresponding memories are empty and high when they are not empty. Full flags. FULLA and FULLB are low when their corresponding memories are full and high when they are not full. Half-full flags. HFA and HFB are high when their corresponding memories contain 512 or more words, and low when they contain 511 or less words. Load clocks. Data on A0-A8 is written into FIFO A on a low-to-high transition of LDCKA. Data on B0 - B8 is written into FIFO B on a low-to-high transition of LDCKB. When the FIFOs are full, LDCKA and LDCKB have no effect on the data residing in memory. Enable inputs. DIR and OE control the transceiver functions. When OE is high, both A0 - A8 and B0 - B8 are in the high-impedance state and can be used as inputs. With OE low and DIR high, the A bus is in the high-impedance state and B bus is active. When both OE and DIR are low, the A bus is active and the B bus is in the high-impedance state. Reset. A reset is accomplished in each direction by taking RSTA and RSTB low. This sets EMPTYA, EMPTYB, FULLA, FULLB, and AF/AEB high. Both FIFOs must be reset upon power up. Select-control inputs. SAB and SBA select whether real-time or stored data is transferred. A low level selects real-time data, and a high level selects stored data. Eight fundamental bus-management functions can be performed as shown in Figure 1. Unload clocks. Data in FIFO A is read to B0 - B8 on a low-to-high transition of UNCKB. Data in FIFO B is read to A0 - A8 on a low-to-high transition of UNCKB. When the FIFOs are empty, UNCKA and UNCKB have no effect on data residing in memory.
15, 30
O
4 - 8, 10 - 13 32 - 35, 37 - 41 21, 24
I/O I/O
DAF, DBF EMPTYA, EMPTYB FULLA, FULLB HFA, HFB LDCKA, LDCKB
I
20, 25 18, 27 16, 29
O O O
17, 28
I
DIR, OE
2, 43
I
RSTA, RSTB
22, 23
I
SAB, SBA
1, 44
I
UNCKA, UNCKB
19, 26
I
programming procedure for AF/AEA The almost-full/almost-empty flags (AF/AEA, AF/AEB) are programmed during each reset cycle. The almost-full/almost-empty offset value FIFO A (X) and for FIFO B (Y) are either a user-defined value or the default values of X = 256 and Y = 256. Below are instructions to program AF/AEA using both methods. AF/AEB is programmed in the same manner for FIFO B.
user-defined X
Take DAF from high to low. This stores A0 thru A8 as X. If RSTA is not already low, take RSTA high. With DAF held low, take RSTA high. This defines the AF/AEA flag using X. To retain the current offset for the next reset, keep DAF low.
default X
To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.
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timing diagram for FIFO A
RSTA
II II II II II II II II II II II II II II II II II II II II II II II II II II II II II
Don't Care
Word 1 Word 2 Word 257 Word 512 Word 768 Word 1024
DAF LDCKA
III EEE III III III III III III III III III III III III III III III III III III III III III III III III III III III III III
II II II
SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
X Invalid
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
A0 - A8
Don't Care
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UNCKA
Q0 - Q8
Invalid
Word 1
Word Word 2 257
Word Word 258 513
Word 514
Word 768
Word 769
Word 1024
Word 1024
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5
EMPTYA
FULLA
HFA
AF/AEA Set Flag to Empty + X/Full - X Set Flag to Empty + 256/ Full - 256 (default) Empty + 256 Half Full Full - 256 Full Full - 256 Half Full Empty + 256 Empty Load X into Flag Register (0 X 511)
Operation of FIFO B is identical to that of FIFO A. Last valid data stays on outputs when FIFO goes empty due to a read.
SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
In Bus A
FIFO A Out Bus B Bus A
In
FIFO A Out
Bus B FIFO B Out In
FIFO B Out In
SAB SBA L X
DIR H
OE L
SAB SBA X X
DIR X
OE H
In Bus A
FIFO A Out Bus B Bus A
In
FIFO A Out Bus B
FIFO B Out In
FIFO B Out In
SAB SBA X L
DIR L
OE L
SAB SBA H X
DIR H
OE L
In
FIFO A Out
Bus A FIFO B Out In
Bus B
SAB SBA X H
DIR L
OE L
Figure 1. Bus-Management Functions
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
SELECT-MODE CONTROL TABLE CONTROL SAB L L H H SBA L H L H A BUS Real-time B to A bus FIFO B to A bus Real-time B to A bus FIFO B to A bus OPERATION B BUS Real-time A to B bus Real-time A to B bus FIFO A to B bus FIFO A to B bus
OUTPUT-ENABLE CONTROL TABLE CONTROL DIR X L H OE H L L A BUS Input Output Input OPERATION B BUS Input Input Output
Figure 1. Bus-Management Functions (Continued)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
recommended operating conditions
ACT2236-20 MIN VCC VIH VIL IOH IOL fclock lk Supply voltage High-level input voltage Low-level input voltage High-level output curg rent Low level output current Low-level Clock frequency A or B ports Status flags A or B ports Status flags LDCKA or LDCKB UNCKA or UNCKB RSTA or RSTB low LDCKA or LDCKB low tw Pulse duration LDCKA or LDCKB high UNCKA or UNCKB low UNCKA or UNCKB high DAF or DBF high Data before LDCKA or LDCKB Define AF/AE: D0 - D8 before DAF or DBF Define AF/AE: DAF or DBF before RSTA or RSTB Define AF/AE (default): DAF or DBF high before RSTA or RSTB RSTA or RSTB inactive (high) before LDCKA or LDCKB Data after LDCKA or LDCKB Define AF/AE: D0 - D8 after DAF or DBF th Hold time Define AF/AE: DAF or DBF low after RSTA or RSTB Define AF/AE (default): DAF or DBF high after RSTA or RSTB TA Operating free-air temperature 20 8 8 8 8 10 4 5 4.5 2 0.8 -8 -8 16 8 50 50 20 10 10 10 10 10 4 5 MAX 5.5 ACT2236-30 MIN 4.5 2 0.8 -8 -8 16 8 33 33 25 14 14 14 14 10 5 5 MAX 5.5 ACT2236-40 MIN 4.5 2 0.8 -8 -8 16 8 25 25 25 20 20 20 20 10 5 5 ns MAX 5.5 ACT2236-60 MIN 4.5 2 0.8 -8 -8 16 8 16.7 16.7 MAX 5.5 UNIT V V V mA mA MHz
7
7
7
7 ns
tsu
Setup time
5
5
5
5
5
5
5
5
1 0
1 0
2 0
2 0 ns
0
0
0
0
0 0 70
0 0 70
0 0 70
0 0 70 C
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH VOL II IOZ ICC ICC Ci DIR, OE Other inputs Flags I/O ports VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, TEST CONDITIONS IOH = - 8 mA IOL = 8 mA IOL = 16 mA VI = VCC or 0 10 Other inputs at VCC or GND 4 8 MIN 2.4 0.5 0.5 5 5 400 2 1 TYP MAX UNIT V V A A A mA pF pF
VCC = 5.5 V, VO = VCC or 0 VI = VCC - 0.2 V or 0 VCC = 5 5 V 5.5 V, One input at 3 4 V 3.4 V,
VI = 0, f = 1 MHz Co VO = 0, f = 1 MHz All typical values are at VCC = 5 V, TA = 25C. ICC tested with outputs open. This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figures 4 and 5)
PARAMETER fmax tpd tpd tPLH tPHL tPHL tPHL tPLH tPLH tPLH tPLH tPHL tPHL tpd tpd tpd tpd ten tdis FROM (INPUT) LDCK UNCK LDCK, LDCKB UNCKA, UNCKB LDCK, LDCKB UNCKA, UNCKB RSTA, RSTB LDCK, LDCKB UNCKA, UNCKB RSTA, RSTB RSTA, RSTB LDCK, LDCKB UNCKA, UNCKB RSTA, RSTB SAB or SBA A or B LDCK, LDCKB UNCKA, UNCKB DIR, OE DIR, OE B or A B or A EMPTYA, EMPTYB EMPTYA, EMPTYB EMPTYA, EMPTYB FULLA, FULLB FULLA, FULLB FULLA, FULLB AF/AEA, AF/AEB HFA, HFB HFA, HFB HFA, HFB B or A B or A AF/AEA, AF/AEB AF/AEA, AF/AEB A or B A or B TO (OUTPUT) MIN ACT2236-20 TYP MAX ACT2236-30 MIN 33 33 23 17 25 15 17 18 15 15 15 15 15 19 15 11 11 19 19 12 10 8 10 4 2 2 4 4 2 2 2 4 1 1 1 2 2 2 1 23 25 15 17 18 15 15 15 15 15 19 15 11 11 19 19 12 10 MAX ACT2236-40 MIN 25 25 8 10 4 2 2 4 4 2 2 2 4 1 1 1 2 2 2 1 25 35 17 19 20 17 17 17 17 17 21 17 13 13 21 23 14 12 MAX ACT2236-60 MIN 16.7 16.7 8 10 4 2 2 4 4 2 2 2 4 1 1 1 2 2 2 1 27 45 19 21 22 19 19 19 19 19 23 19 15 15 23 23 16 14 MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
50 50 8 10 4 2 2 4 4 2 2 2 4 1 1 1 2 2 2 1
All typical values are at VCC = 5 V, TA = 25C. These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance per 1K bits Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF f = 5 MHz pF, TYP 71 57 UNIT pF
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME vs LOAD CAPACITANCE
typ + 8 Cpd - Power Dissipation Capacitance - pF VCC = 5 V TA = 25C RL = 500 typ + 2 VCC = 5 V fi = 5 MHz TA = 25C typ + 1
POWER DISSIPATION CAPACITANCE vs SUPPLY VOLTAGE
t pd - Propagation Delay Time - ns
typ + 6
typ + 4
typ
typ + 2
typ - 1
typ
typ - 2
typ - 2 0 50 100 150 200 250 300 CL - Load Capacitance - pF
typ - 3 4.5
4.6
4.7 4.8 4.9
5
5.1 5.2
5.3
5.4 5.5
VCC - Supply Voltage - V
Figure 2
Figure 3
calculating power dissipation
The maximum power dissipation (PT) can be calculated by: PT = VCC x [ICC + (N x ICC x dc)] + (Cpd x VCC2 x fi) + (CL x VCC2 x fo) where: ICC N ICC dc Cpd CL fi fo = = = = = = = = power-down ICC maximum number of inputs driven by a TTL device increase in supply current duty cycle of inputs at a TTL high level of 3.4 V power dissipation capacitance output capacitive load data input frequency data output frequency
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SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS149A - APRIL 1990 - REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
3V From Output Under Test RL = 500 CL = 50 pF Output Input tpd 1.5 V GND tpd 3V 1.5 V 0V LOAD CIRCUIT TOTEM-POLE OUTPUTS
Figure 4. Standard CMOS Outputs (All Flags)
3V Input VCC S1 From Output Under Test RL 1.5 V 1.5 V 0V tPZL Output 1.5 V tPHZ CL tPZH S2 Output 1.5 V 0.3 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOH tPLZ 0.3 V VOL
VCC
PARAMETER ten tdi dis tPZH tPZL tPHZ tPLZ
RL 500 500
CL 50 pF 50 pF
S1 Open Closed Open Closed
S2 Closed Open Closed Open Open
tpd or tt - 50 pF Open Includes probe and test-fixture capacitance
Figure 5. 3-State Outputs (A0 - A8, B0 - B8)
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