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PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
R8C/26, R8C/27 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0168-0010 Rev.0.10 Nov 14, 2005
1.
Overview
This MCU is built using the high-performance silicon gate CMOS process using the R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. Furthermore, the data flash (1KB x 2 blocks) is embedded in the R8C/27 group. The difference between R8C/26 and R8C/27 groups is only the existence of the data flash. Their peripheral functions are the same.
1.1
Applications
Electric household appliance, office equipment, audio, consumer products, etc.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 1 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
1.2
Performance Overview
Table 1.1 lists the R8C/26 Group Performance. Table 1.2 lists the R8C/27 Group Performance. Table 1.1 R8C/26 Group Performance Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction Execution 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V) Time 100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V) TBD(f(XIN)=TBD, VCC=2.2 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.3 Product Information of R8C/26 Group Peripheral Port I/O port: 25 pins, Input port: 3 pins LED Drive Port I/O port: 8 pins Function Timer Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Circuits of input capture and output compare) Timer RE: With real-time clock and compare match function Serial Interface 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock Synchronous Serial 1 channel Interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN Module Hardware LIN: 1 channel (Timer RA, UART0) A/D Converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupt Internal: 10 factors, External: 4 factors, Software: 4 factors, Priority level: 7 levels Clock Generation Circuit 3 circuits * XIN clock generation circuit (Equipped with a built-in feedback resistor) * On-chip oscillator (High speed, low speed) Equipped with frequency adjustment function on high speed on-chip oscillator * XCIN clock generation circuit (32 kHz) Oscillation Stop Detection Function XIN clock oscillation stop detection function Voltage Detection Circuit Included Power-On Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) VCC=2.2 to 5.5V (f(XIN)=TBD) Power Consumption TBD Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V Program/Erase Endurance 100 times Operating Ambient Temperature -20 to 85C -40 to 85C (D Version)(2) Package 32-pin plastic mold LQFP
NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version when using it.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 2 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
Table 1.2
R8C/27 Group Performance Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction Execution 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V) Time 100ns (f(XIN)=10MHz, VCC=2.7 to 5.5V) TBD (f(XIN)=TBD, VCC=2.2 to 5.5V) Operating Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.4 Product Information of R8C/27 Group Peripheral Port I/O: 25 pins, Input: 3 pins LED Drive Port I/O port: 8 pins Function Timer Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RC: 16 bits x 1 channel (Circuits of input capture and output compare) Timer RE:With real-time clock and compare match function Serial Interface 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock Synchronous Serial 1 channel Interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN Module Hardware LIN: 1 channel (Timer RA, UART0) A/D Converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupt Internal: 10 factors, External: 4 factors, Software: 4 factors, Priority level: 7 levels Clock Generation Circuit 3 circuits * XIN clock generation circuit (Equipped with a built-in feedback resistor) * On-chip oscillator (High speed, low speed) Equipped with frequency adjustment function on high speed on-chip oscillator * XCIN clock generation circuit (32 kHz) Oscillation Stop Detection Function XIN clock oscillation stop detection function Voltage Detection Circuit Included Power-On Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) VCC=2.2 to 5.5V (f(XIN)=TBD) Power Consumption TBD Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V Program/Erase Endurance 1,0000 times (Data flash) 1,000 times (Program ROM) Operating Ambient Temperature -20 to 85C -40 to 85C (D Version)(2) Package 32-pin plastic mold LQFP
NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version when using it.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 3 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
6
1
3
2
I/O port Peripheral Function
Port P0
Port P1
Port P3
Port P4
Port P5
Timer Timer RA (8 bits) Timer RB (8 bits) Timer RC (16 bits x 1 channel) Timer RE (8 bits)
A/D Converter (10 bits x 12 channels)
System Clock Generator XIN-XOUT High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator XCIN-XCOUT
UART or Clock Synchronous Serial I/O (8 bits x 2 channels)
I2C bus Interface or Clock synchronous serial I/O with chip select (8 bits x 1 channel)
LIN Module (1 channel)
Watchdog Timer (15 bits)
R8C/Tiny Series CPU Core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type.
Figure 1.1
Block Diagram
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 4 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
1.4
Product Information
Table 1.3 lists the Product Information of R8C/26 Group. Table 1.4 lists the Product Information of R8C/27 Group. Table 1.3 Product Information of R8C/26 Group ROM Capacity 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes RAM Capacity 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A As of Nov 2005 Remarks N Version
Type No. R5F21262SNFP (D) R5F21264SNFP (D) R5F21265SNFP (D) R5F21266SNFP (D) R5F21262SDFP (D) R5F21264SDFP (D) R5F21265SDFP (D) R5F21266SDFP (D) (D): Under Development
D Version
Type No.
R 5 F 21 26 6 S N FP
Package Type: FP : PLQP0032GB-A Grouping N : Operating Ambient Temperature -20 C to 85 C D : Operating Ambient Temperature -40 C to 85 C S : Low voltage version ROM Capacity 2 : 8KB 4 : 16KB 5 : 24KB 6 : 32KB R8C/26 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors
Figure 1.2
Type Number, Memory Size and Package of R8C/26 Group
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 5 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
Table 1.4
Product Information of R8C/27 Group ROM Capacity Program ROM Data flash 8 Kbytes 1 Kbytes x 2 16 Kbytes 1 Kbytes x 2 24 Kbytes 1 Kbytes x 2 32 Kbytes 1 Kbytes x 2 8 Kbytes 1 Kbytes x 2 16 Kbytes 1 Kbytes x 2 24 Kbytes 1 Kbytes x 2 32 Kbytes 1 Kbytes x 2 RAM Capacity 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes Package Type
As of Nov 2005 Remarks
Type No. R5F21272SNFP (D) R5F21274SNFP (D) R5F21275SNFP (D) R5F21276SNFP (D) R5F21272SDFP (D) R5F21274SDFP (D) R5F21275SDFP (D) R5F21276SDFP (D)
PLQP0032GB-A N Version PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A D Version PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A
(D): Under Development
Type No. R 5 F 21 27 6 S N FP
Package Type: FP : PLQP0032GB-A Grouping N : Operating Ambient Temperature -20 C to 85 C D : Operating Ambient Temperature -40 C to 85 C S : Low voltage version ROM Capacity 2 : 8KB 4 : 16KB 5 : 24KB 6 : 32KB R8C/27 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors
Figure 1.3
Type Number, Memory Size and Package of R8C/27 Group
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 6 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
1.5
Pin Assignment
Figure 1.4 shows the Pin Assignment (top view).
Pin Assignment (top view)
P1_1/KI1/AN9/TRCIOA/TRCTRG VREF/P4_2 P1_2/KI2/AN10/TRCIOB P3_4/SDA/SCS/(TRCIOC)(2) P3_3/INT3/SSI/TRCCLK
P1_3/KI3/AN11/TRBO
P1_0/KI0/AN8
24 23 22 21 20 19 18 17
P1_4/TXD0
P0_7/AN0 P0_6/AN1 P0_5/AN2/CLK1 P0_4/AN3/TREO P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7/(TXD1)(2)
25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8
16 15 14
R8C/26 Group R8C/27 Group
13 12 11 10 9
P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0/(SSI)(2) P5_3/TRCIOC P5_4/TRCIOD P3_1/TRBO P3_6/(TXD1)/(RXD1)/(INT1)(2) P1_7/TRAIO/INT1 P4_5/INT0/(RXD1)(2)
P3_5/SCL/SSCK/(TRCIOD)(2)
RESET XOUT/XCOUT/P4_7 (1)
VSS/AVSS XIN/XCIN/P4_6
NOTES: 1. P4_7 is a port for the input. 2. This can be assigned to the pin in parentheses by program. Package: PLQP0032GB-A (32P6U-A)
Figure 1.4
Pin Assignment (top view)
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 7 of 22
P3_7/TRAO/SSO/RXD1/(TXD1)
VCC/AVCC
MODE
(2)
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
1.6
Pin Description
Table 1.5 lists the Pin Description. Table 1.5
Function Analog Power Supply Input Reset Input MODE XIN Clock Input XIN Clock Output XCIN Clock Input
Pin Description
Pin name AVCC, AVSS RESET MODE XIN XOUT XCIN I/O type I I I I I O I O I I O I/O O I I I/O O I/O I O I/O I/O I/O I/O I/O I/O I I I/O Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for the XIN clock generation circuit I/ O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for the XCIN clock generation circuit I/ O. Connect a crystal oscillator between the XCIN and XCOUT pins. To use an externally derived clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. Key input interrupt input pins. Timer RA output pin. Timer RA I/O pin. Timer RB output pin. External clock input pin. External trigger input pin. Sharing output-compare output / input-capture input / PWM / PWM2 output pins. Timer RE output pin. Clock I/O pin. Receive data input pins. Transmit data output pins. Clock I/O pin. Data I/O pin. Data I/O pin. Chip-select signal I/O pin. Clock I/O pin. Data I/O pin. Reference voltage input pin to A/D converter. Analog input pins to A/D converter. These are CMOS I/O ports. Each port contains an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull-up resistor or not by program. P1_0 to P1_7 also function as LED drive ports. Ports for input-only.
Power Supply Input VCC, VSS
XCIN Clock Output XCOUT INT Interrupt Input Key Input Interrupt Timer RA Timer RB Timer RC INT0, INT1, INT3 KI0 to KI3 TRAO TRAIO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD Timer RE Serial Interface TREO CLK0, CLK1 RXD0, RXD1 TXD0, TXD1 I2C bus Interface SCL SDA Clock Synchronous SSI Serial I/O with Chip SCS Select SSCK SSO Reference Voltage Input A/D Converter I/O Port VREF AN0 to AN11 P0_0 to P0_7, P1_0 to P1_7, P3_1, P3_3 to P3_7, P4_5, P5_3, P5_4 P4_2, P4_6, P4_7 O: Output
Input Port I: Input
I
I/O: Input and output
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 8 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
1. Overview
Table 1.6
Pin Name Information by Pin Number
I/O Pin of Peripheral Function Clock Synchronous Serial Interface Serial I/O with Chip Select SSCK RXD1/(TXD1)(1) SSO
Pin Number
Control Pin
Port
Interrupt
Timer (TRCIOD)(1) TRAO
I2C bus Interface SCL
A/D Converter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VRFF RESET XOUT VSS/AVSS XIN VCC/AVCC MODE
P3_5 P3_7 P4_7 P4_6
P4_5 P1_7 P3_6 P3_1 P5_4 P5_3 P1_6 P1_5 P1_4 P1_3 P1_2 P4_2 P1_1 P1_0 P3_3 P3_4 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0
INT0 INT1 (INT1)(1) TRBO TRCIOD TRCIOC TRAIO
(RXD1)(1) (TXD1)/(RXD1)(1)
CLK0 (INT1)(1) KI3 KI2 KI1 KI0 INT3 TRCCLK (TRCIOC)(1) (TRAIO)(1) TRBO TRCIOB TRCIOA/ TRCTRG RXD0 TXD0
(SSI)(1)
AN11 AN10 AN9 AN8 SSI SCS SDA AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CLK1 TREO
(TXD1)(1)
NOTES: 1. This can be assigned to the pin in parentheses by program.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
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Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data Registers (1)
R2 R3 A0 A1 FB
b19 b15 b0
Address Registers (1) Frame Bass Register (1)
INTBH
INTBL
Interrupt Table Register
The 4-high order bits of INTB are INTBH and the 16-low order bits of INTB are INTBL.
b19 b0
PC
Program Counter
b15
b0
USP ISP SB
b15 b0
User Stack Pointer Interrupt Stack Pointer Static Base Register
FLG
b15 b8 b7 b0
Flag Register
IPL
U I OBSZDC
Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Bit Processor Interrupt Priority Level Reserved Bit
NOTES: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Register
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 10 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debug only. Set to "0".
2.8.3
Zero Flag (Z)
The Z flag is set to "1" when an arithmetic operation resulted in 0; otherwise, "0".
2.8.4
Sign Flag (S)
The S flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, "0".
2.8.5
Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is "0". The register bank 1 is selected when this flag is set to "1".
2.8.6
Overflow Flag (O)
The O flag is set to "1" when the operation resulted in an overflow; otherwise, "0".
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 11 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0", and are enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0", USP is selected when the U flag is set to "1". The U flag is set to "0" when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
When write to this bit, set to "0". When read, its content is indeterminate.
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Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
3. Memory
3.
3.1
Memory
R8C/26Group
Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group provides the 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Register (SFR))
002FFh
00400h
Internal RAM
0XXXh 0FFDCh
Undefined Instruction Overflow BRK Instruction Address Match Single Step
Watchdog Timer*Oscillation Stop Detection*Voltage Monitor
0YYYYh
Internal ROM (Program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expansion Area
FFFFFh
NOTES: 1. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21262SNFP, R5F21262SDFP R5F21264SNFP, R5F21264SDFP R5F21265SNFP, R5F21265SDFP R5F21266SNFP, R5F21266SDFP Size 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0E000h 0C000h 0A000h 08000h Size 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes Internal RAM Address 0XXXXh 005FFh 007FFh 009FFh 009FFh
Figure 3.1
Memory Map of R8C/26 Group
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 13 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
3. Memory
3.2
R8C/27 Group
Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group provides the 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users.
00000h
SFR
(See 4. Special Function Register (SFR))
002FFh
00400h
Internal RAM
0XXXXh 02400h
Internal ROM (Data flash)(1)
02BFFh
0FFDCh
Undefined Instruction Overflow BRK Instruction Address Match Single Step
Watchdog Timer*Oscillation Stop Detection*Voltage Monitor
0YYYYh
Internal ROM (Program ROM)
0FFFFh 0FFFFh
(Reserved) (Reserved) Reset
Expansion Area
FFFFFh
NOTES: 1. The data flash block A (1 Kbytes) and B (1 Kbytes) are shown. 2. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21272SNFP, R5F21272SDFP R5F21274SNFP, R5F21274SDFP R5F21275SNFP, R5F21275SDFP R5F21276SNFP, R5F21276SDFP Size 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0E000h 0C000h 0A000h 08000h Internal RAM Size 512 bytes 1 Kbytes 1.5 Kbytes 1.5 Kbytes Address 0XXXXh 005FFh 007FFh 009FFh 009FFh
Figure 3.2
Memory Map of R8C/27 Group
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 14 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
4.
Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR information. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. Software reset, the watchdog timer reset, the voltage monitor 1 or the voltage monitor 2 reset does not affect this register. 3. Owing to Hardware reset. 4. Owing to Power-on reset or the voltage monitor 0 reset. 5. Software reset, the watchdog timer reset, the voltage monitor 1 or the voltage monitor 2 reset does not affect b2 and b3.
SFR Information(1)(1)
Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h 00h 01101000b 00100000b
Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PRCR OCD WDTR WDTS WDC RMAD0
00h 00000100b XXh XXh 000XXXXXb 00h 00h 00h 00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Register 1
AIER RMAD1
Count Source Protection Mode Register
CSPR
00h
High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
FRA0 FRA1 FRA2
00h When shipping 00h
Clock Prescaler Reset Flag
CPSRF
00h
Voltage Detection Register 1 (2) Voltage Detection Register 2 (2)
VCA1 VCA2
00001000b 00h (3) 01000000b (4)
Voltage Monitor 1 Circuit Control Register (5) Voltage Monitor 2 Circuit Control Register (5) Voltage Monitor 0 Circuit Control Register (2)
VW1C VW2C VW0C
00001000b 00h 00001000b (3) 01001001b (4)
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 15 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
SFR Information(2)(1)
Register Symbol After reset
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RE Interrupt Control Register
TREIC
XXXXX000b
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU / IIC Interrupt Control Register (2) UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register
KUPIC ADIC SSUIC / IICIC S0TIC S0RIC S1TIC S1RIC TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. Selected by the IICSEL bit in the PMR register.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 16 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
SFR Information(3)(1)
Register Symbol After reset
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
SS Control Register H / IIC bus Control Register 1(2) SS Control Register L / IIC bus Control Register 2(2) SS Mode Register / IIC bus Mode Register(2) SS Enable Register / IIC bus Interrupt Enable Register(2) SS Status Register / IIC bus Status Register(2) SS Mode Register 2 / Slave Address Register(2) SS Transmit Data Register / IIC bus Transmit Data Register(2) SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR
00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. Selected by the IICSEL bit in the PMR register.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 17 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
SFR Information(4)(1)
Register A/D Register AD Symbol XXh XXh After reset
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00h 00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register
P0 P1 PD0 PD1 P3 PD3 P4 P5 PD4 PD5
XXh XXh 00h 00h XXh 00h XXh XXh 00h 00h
Pin Select Register 1 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register
PINSR1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 DRR
00h 00h 00h 00h 00h 00h 00h 00h XX000000b 00h
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 18 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.5
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh
SFR Information(5)(1)
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh
Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Register Timer RE Time Data Register Timer RE Day Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Clock Source Select Register Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter Timer RC General Register A Timer RC General Register B Timer RC General Register C Timer RC General Register D Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER
00h 00h 00h 00h 00h 00h 00001000b 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 19 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.6
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh
SFR Information(6)(1)
Register Symbol After reset
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 20 of 22
Under development
Preliminary specification Specications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
4. Special Function Register (SFR)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh
SFR Information(7)(1)
Register Symbol After reset
Flash Memory Control Register 4 Flash Memory Control Register1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
01000000b 1000000Xb 00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. The OFS register cannot be changed by program. Use a flash programmer to write to it.
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 21 of 22
Under development
Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/26, R8C/27 Group
Package Dimensions
Package Dimensions
JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g
HD *1
D
24
17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
25
16
HE
E
c1
*2
c
Reference Dimension in Millimeters Symbol
Terminal cross section 32
1 ZD Index mark
8
ZE
9
A2
A
F
A1
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
y e
*3
Detail F bp x
Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0
Rev.0.10 Nov 14, 2005 REJ03B0168-0010
Page 22 of 22
c
REVISION HISTORY REVISION HISTORY
Rev. 0.10 Date Nov 14, 2005
R8C/26, R8C/27 Group Shortsheet R8C/26, R8C/27 Group Shortsheet
Description
Page - First Edition issued
Summary
A-1
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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(c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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