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PCI1410 GHK/GGU/PGE
PC Card Controllers
Data Manual
2000
PCIBus Solutions
Printed in U.S.A. 03/00
SCPS045C
PCI1410 PC Card Controllers Data Manual
Literature Number: SCPS045C March 2000
Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Contents
Section 1 Title Page 1-1 1-1 1-1 1-2 1-2 2-1 3-1 3-1 3-2 3-2 3-2 3-2 3-3 3-3 3-3 3-4 3-5 3-6 3-6 3-7 3-7 3-8 3-8 3-10 3-10 3-11 3-11 3-11 3-13 3-14 3-15 3-15 3-17 3-17 3-18 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . . 3.4.1 PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . . 3.5 PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 PC Card Insertion/Removal and Recognition . . . . . . . . . . . 3.5.2 P2C Power-Switch Interface (TPS2211) . . . . . . . . . . . . . . . 3.5.3 Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 Integrated Pullup Resistors For PC Card Interface . . . . . . 3.5.7 SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . . 3.5.8 LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . . 3.5.10 PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.11 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Serial Bus Interface Implementation . . . . . . . . . . . . . . . . . . . 3.6.2 Serial Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Accessing Serial Bus Devices Through Software . . . . . . . . 3.7 Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 PC Card Functional and Card Status Change Interrupts . 3.7.2 Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.3 Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.4 Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
2 3
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4
3.7.5 Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . . 3.7.6 SMI Support in the PCI1410 . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 CardBus PC Card Power Management . . . . . . . . . . . . . . . . 3.8.3 16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . . 3.8.4 Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.5 Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . . 3.8.6 Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.7 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.8 CardBus Bridge Power Management . . . . . . . . . . . . . . . . . . 3.8.9 ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.10 Master List of PME Context Bits and Global Reset Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . . 4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 PC Card 16-bit I/F Legacy-Mode Base-Address Register . . . . . . . . . 4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-18 3-18 3-19 3-19 3-19 3-19 3-20 3-21 3-21 3-22 3-23 3-23 3-24 4-1 4-1 4-2 4-2 4-3 4-4 4-5 4-5 4-5 4-6 4-6 4-6 4-7 4-7 4-8 4-9 4-9 4-9 4-10 4-10 4-11 4-11 4-12 4-12 4-13 4-14 4-15 4-15 4-15 4-16
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4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41
5
Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.42 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . 4.44 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . 4.45 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.47 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.48 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.49 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . 5.2 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . 5.5 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . 5.7 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 5.8 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . . 5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . . 5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . . 5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . . 5.13 ExCA Memory Windows 0-4 Start-Address Low-Byte Registers . . . 5.14 ExCA Memory Windows 0-4 Start-Address High-Byte Registers . . . 5.15 ExCA Memory Windows 0-4 End-Address Low-Byte Registers . . . . 5.16 ExCA Memory Windows 0-4 End-Address High-Byte Registers . . . 5.17 ExCA Memory Windows 0-4 Offset-Address Low-Byte Registers . . 5.18 ExCA Memory Windows 0-4 Offset-Address High-Byte Registers . 5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . 5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . .
4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-26 4-27 4-28 4-29 4-29 4-30 4-31 4-32 4-33 4-33 4-34 4-34 4-35 5-1 5-4 5-5 5-6 5-8 5-9 5-10 5-11 5-12 5-13 5-13 5-14 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23
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6
7
8
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5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5-23 5.23 ExCA Memory Windows 0-4 Page Register . . . . . . . . . . . . . . . . . . . . 5-24 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.3 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.4 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.6 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 DDMA Current Address/Base-Address Register . . . . . . . . . . . . . . . . . 7-1 7.2 DDMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3 DDMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . 7-2 7.4 DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.5 DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.6 DDMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.7 DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.8 DDMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.9 DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . 8-4 8.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . 8-4 8.6 PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
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List of Illustrations
Figure Title 2-1 PCI-to-CardBus Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 PCI-to-PC Card (16-Bit) Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 GGU Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 GHK Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 PCI1410 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 TPS2211 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 TPS2211 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Zoomed Video Implementation Using PCI1410 . . . . . . . . . . . . . . . . . . . . . . . 3-6 Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . . . 3-8 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Serial Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . . 3-11 Serial Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Serial Bus Protocol - Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Serial Bus Protocol - Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . . 3-15 EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Suspend Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . . Page 2-1 2-2 2-3 2-3 3-1 3-2 3-4 3-5 3-5 3-6 3-8 3-8 3-11 3-12 3-12 3-13 3-13 3-13 3-14 3-18 3-20 3-21 3-22 3-24 5-1 5-1 6-1
vii
List of Tables
Table Title 2-1 CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number . . 2-2 CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number . . . 2-3 CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number . . . 2-4 CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . 2-13 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . . 2-15 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . 2-16 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . 3-1 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . . 3-2 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PC/PCI Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 I/O Addresses Used for PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . . 3-7 PCI1410 Registers Used to Program Serial Bus Devices . . . . . . . . . . . . . . . 3-8 Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 2-4 2-5 2-6 2-8 2-10 2-12 2-12 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 3-4 3-9 3-10 3-10 3-11 3-13 3-14 3-16 3-16 3-18 3-23 4-1 4-2 4-3 4-4 4-8 4-14 4-17 4-19 4-20
viii
4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17
Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Bridge Support Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 ExCA Power Control Register 82365SL Support . . . . . . . . . . . . . . . . . . . . . . 5-5 ExCA Power Control Register 82365SL-DF Support . . . . . . . . . . . . . . . . . . . 5-6 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . . . . . . 5-9 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 ExCA Memory Windows 0-4 Start-Address High-Byte Registers . . . . . . . 5-12 ExCA Memory Windows 0-4 End-Address High-Byte Registers . . . . . . . . 5-13 ExCA Memory Windows 0-4 Offset-Address High-Byte Registers . . . . . . 5-14 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . . . . . . 5-15 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-21 4-22 4-23 4-24 4-25 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-33 4-34 4-34 4-35 5-2 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-16 5-18 5-20 5-21 5-22 6-1 6-2 6-3 6-4 6-7 6-8 6-9
ix
7-1 7-2 7-3 7-4 7-5
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1 7-3 7-3 7-4 7-5
x
1 Introduction
1.1 Description
The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required. The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is register compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1410, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption.
1.2 Features
The PCI1410 supports the following features: * * * * * * * * Ability to wake from D3hot and D3cold Fully compatible with the Intel 430TX (Mobile Triton II) chipset A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball grid array (GGU) package, or 209-terminal MicroStar BGA (GHK) package 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards Single PC Card or CardBus slot with hot insertion and removal Burst transfers to maximize data throughput on the PCI bus and the CardBus bus Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts
TI is a trademark of Texas Instruments. MicroStar BGA is a trademark of Texas Instruments. Intel is a trademark of Intel Corporation. Other trademarks are the property of their respective owners.
1-1
* * * * * * * * * * * * * * * *
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID Pipelined architecture allows greater than 130-Mbps sustained throughput from CardBus to PCI and from PCI to CardBus Interface to parallel single-slot PC Card power interface switches like the TI TPS2211 Up to five general-purpose I/Os Programmable output select for CLKRUN Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket Two I/O windows and two memory windows available to the CardBus socket Exchangeable card architecture (ExCA) compatible registers are mapped in memory and I/O space Intel 82365SL-DF and 82365SL register compatible Distributed DMA (DDMA) and PC/PCI DMA 16-Bit DMA on the PC Card socket Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN Socket activity LED pins PCI bus lock (LOCK) Advanced submicron, low-power CMOS technology Internal ring oscillator
1.3 Related Documents
* * * * * * * * * * Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0) PCI Bus Power Management Interface Specification (Revision 1.1) PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (Revision 0.6) PCI Local Bus Specification (Revision 2.2) PCI Mobile Design Guide (Revision 1.0) PCI14xx Implementation Guide for D3 Wake-Up 1997 PC Card Standard PC 98 PC 99 Serialized IRQ Support for PCI Systems (Revision 6)
1.4 Ordering Information
ORDERING NUMBER PCI1410 NAME PC Card Controller VOLTAGE 3.3-V, 5-V tolerant I/Os PACKAGE 144-terminal LQFP 144-terminal PBGA 209-terminal PBGA
1-2
2 Terminal Descriptions
The PCI1410 is packaged in either a 144-terminal GGU MicroStar BGA or a 144-terminal PGE package. It is also packaged in a 209-terminal GHK MicroStar BGA that is pin compatible with the TI PCI4410. The PCI4410 is a single-socket CardBus bridge with integrated OHCI link. Figure 2-1 is a PGE-package terminal diagram showing PCI-to-CardBus signal names, and Figure 2-2 is a PGE-package terminal diagram showing PCI-to-PC Card signal names. Figure 2-3 and Figure 2-4 are terminal diagrams for the GGU and GHK packages, respectively.
PGE LOW-PROFILE QUAD FLAT PACKAGE (TOP VIEW)
CCLK CDEVSEL CGNT CSTOP CPERR CBLOCK V CC CPAR CRSVD CC/BE1 CAD16 CAD14 CAD15 CAD12 GND CAD13 CAD11 CAD10 VCCCB CAD9 CC/BE0 CAD8 V CC CAD7 CRSVD CAD5 CAD6 CAD3 CAD4 CAD1 GND CAD2 CAD0 CCD1 VCCD1 VCCD0
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
CTRDY CIRDY CFRAME CC/BE2 CAD17 GND CAD18 CAD19 CVS2 CAD20 CRST CAD21 CAD22 VCC CREQ CAD23 CC/BE3 VCCCB CAD24 CAD25 CAD26 GND CVS1 CINT CSERR CAUDIO CSTSCHG CCLKRUN CCD2 VCC CAD27 CAD28 CAD29 CAD30 CRSVD CAD31
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
VPPD1 VPPD0 SUSPEND MFUNC6 MFUNC5 MFUNC4 GRST MFUNC3 MFUNC2 VCCI SPKROUT MFUNC1 MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 VCC AD7 C/BE0 AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 AD15 C/BE1
REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 PRST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR
Figure 2-1. PCI-to-CardBus Terminal Diagram
2-1
PGE LOW-PROFILE QUAD FLAT PACKAGE (TOP VIEW)
ADDR16 ADDR21 WE ADDR20 ADDR14 ADDR19 V CC ADDR13 ADDR18 ADDR8 ADDR17 ADDR9 IOWR ADDR11 GND IORD OE CE2 VCCCB ADDR10 CE1 DATA15 V CC DATA7 DATA14 DATA6 DATA13 DATA5 DATA12 DATA4 GND DATA11 DATA3 CD1 VCCD1 VCCD0
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
ADDR22 ADDR15 ADDR23 ADDR12 ADDR24 GND ADDR7 ADDR25 VS2 ADDR6 RESET ADDR5 ADDR4 VCC INPACK ADDR3 REG VCCCB ADDR2 ADDR1 ADDR0 GND VS1 READY(IREQ) WAIT BVD2(SPKR) BVD1(STSCHG/RI) WP(IOIS16) CD2 VCC DATA0 DATA8 DATA1 DATA9 DATA2 DATA10
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
VPPD1 VPPD0 SUSPEND MFUNC6 MFUNC5 MFUNC4 GRST MFUNC3 MFUNC2 VCCI SPKROUT MFUNC1 MFUNC0 RI_OUT/PME GND AD0 AD1 AD2 AD3 AD4 AD5 AD6 VCC AD7 C/BE0 AD8 AD9 AD10 VCCP AD11 GND AD12 AD13 AD14 AD15 C/BE1
2-2
REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 PRST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR
Figure 2-2. PCI-to-PC Card (16-Bit) Terminal Diagram
N M L K J H G F E D C B A
1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 2-3. GGU Package Terminal Diagram
W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Figure 2-4. GHK Package Terminal Diagram Table 2-1 shows the terminal assignments for the 144-terminal GGU CardBus and 16-bit PC Card signal names. Table 2-2 shows the terminal assignments for the 144-terminal PGE CardBus and 16-bit PC Card signal names. Table 2-3 shows the terminal assignments for the 209-terminal GHK CardBus and 16-bit PC Card signal names. Table 2-4 shows the CardBus PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers. Table 2-5 shows the 16-bit PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers.
2-3
Table 2-1. CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number
SIGNAL NAME TERM. TERM NO. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CARD BUS REQ CRSVD CAD28 CCD2 CSERR CAD26 VCCCB CAD23 CAD21 CAD19 CC/BE2 CIRDY CTRDY GNT CAD31 CAD29 VCC CAUDIO GND CC/BE3 CREQ CRST CAD18 CFRAME CCLK CDEVSEL AD30 AD31 CAD30 CAD27 CSTSCHG CVS1 CAD24 VCC CAD20 GND 16-BIT REQ DATA2 DATA8 CD2 WAIT ADDR0 VCCCB ADDR3 ADDR5 ADDR25 ADDR12 ADDR15 ADDR22 GNT DATA10 DATA1 VCC BVD2 (SPKR) GND REG INPACK RESET ADDR7 ADDR23 ADDR16 ADDR21 AD30 AD31 DATA9 DATA0 BVD1 (STSCHG/RI) VS1 ADDR2 VCC ADDR6 GND TERM. TERM NO. C11 C12 C13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 E1 E2 E3 E4 E10 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4 SIGNAL NAME CARD BUS CGNT CSTOP CPERR AD27 AD28 GND AD29 CCLKRUN CINT CAD25 CAD22 CVS2 CAD17 CBLOCK VCC CPAR C/BE3 AD24 AD25 AD26 CRSVD CC/BE1 CAD16 CAD14 AD22 AD23 VCC IDSEL CAD15 CAD12 GND CAD13 VCCP AD21 AD20 PRST 16-BIT WE ADDR20 ADDR14 AD27 AD28 GND AD29 WP (IOIS16) READY (IREQ) ADDR1 ADDR4 VS2 ADDR24 ADDR19 VCC ADDR13 C/BE3 AD24 AD25 AD26 ADDR18 ADDR8 ADDR17 ADDR9 AD22 AD23 VCC IDSEL IOWR ADDR11 GND IORD VCCP AD21 AD20 PRST TERM. TERM NO. G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J4 J10 J11 J12 J13 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 L1 L2 L3 SIGNAL NAME CARD BUS CAD11 CAD10 CAD9 VCCCB PCLK GND AD19 AD18 CAD7 VCC CAD8 CC/BE0 AD17 AD16 C/BE2 FRAME CAD3 CAD6 CAD5 CRSVD IRDY VCC TRDY AD12 AD10 AD7 AD1 MFUNC0 MFUNC2 CAD2 GND CAD1 CAD4 DEVSEL STOP PERR 16-BIT OE CE2 ADDR10 VCCCB PCLK GND AD19 AD18 DATA7 VCC DATA15 CE1 AD17 AD16 C/BE2 FRAME DATA5 DATA13 DATA6 DATA14 IRDY VCC TRDY AD12 AD10 AD7 AD1 MFUNC0 MFUNC2 DATA11 GND DATA4 DATA12 DEVSEL STOP PERR TERM. TERM NO. L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 SIGNAL NAME CARD BUS GND AD9 VCC AD2 RI_OUT/ PME VCCI MFUNC4 SUSPEND CCD1 CAD0 SERR PAR AD14 AD11 AD8 AD6 AD4 GND SPKROUT GRST MFUNC6 VPPD1 VCCD1 C/BE1 AD15 AD13 VCCP C/BE0 AD5 AD3 AD0 MFUNC1 MFUNC3 MFUNC5 VPPD0 VCCD0 16-BIT GND AD9 VCC AD2 RI_OUT/ PME VCCI MFUNC4 SUSPEND CD1 DATA3 SERR PAR AD14 AD11 AD8 AD6 AD4 GND SPKROUT GRST MFUNC6 VPPD1 VCCD1 C/BE1 AD15 AD13 VCCP C/BE0 AD5 AD3 AD0 MFUNC1 MFUNC3 MFUNC5 VPPD0 VCCD0
2-4
Table 2-2. CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number
SIGNAL NAME TERM TERM. NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CARD BUS REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 PRST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR 16-BIT REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL VCC AD23 AD22 AD21 VCCP AD20 PRST PCLK GND AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY VCC TRDY DEVSEL STOP PERR SERR PAR TERM TERM. NO. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SIGNAL NAME CARD BUS C/BE1 AD15 AD14 AD13 AD12 GND AD11 VCCP AD10 AD9 AD8 C/BE0 AD7 VCC AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND RI_OUT/ PME MFUNC0 MFUNC1 SPKROUT VCCI MFUNC2 MFUNC3 GRST MFUNC4 MFUNC5 MFUNC6 SUSPEND VPPD0 VPPD1 16-BIT C/BE1 AD15 AD14 AD13 AD12 GND AD11 VCCP AD10 AD9 AD8 C/BE0 AD7 VCC AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND RI_OUT/ PME MFUNC0 MFUNC1 SPKROUT VCCI MFUNC2 MFUNC3 GRST MFUNC4 MFUNC5 MFUNC6 SUSPEND VPPD0 VPPD1 TERM TERM. NO. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 SIGNAL NAME CARD BUS VCCD0 VCCD1 CCD1 CAD0 CAD2 GND CAD1 CAD4 CAD3 CAD6 CAD5 CRSVD CAD7 VCC CAD8 CC/BE0 CAD9 VCCCB CAD10 CAD11 CAD13 GND CAD12 CAD15 CAD14 CAD16 CC/BE1 CRSVD CPAR VCC CBLOCK CPERR CSTOP CGNT CDEVSEL CCLK 16-BIT VCCD0 VCCD1 CD1 DATA3 DATA11 GND DATA4 DATA12 DATA5 DATA13 DATA6 DATA14 DATA7 VCC DATA15 CE1 ADDR10 VCCCB CE2 OE IORD GND ADDR11 IOWR ADDR9 ADDR17 ADDR8 ADDR18 ADDR13 VCC ADDR19 ADDR14 ADDR20 WE ADDR21 ADDR16 TERM TERM. NO. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 SIGNAL NAME CARD BUS CTRDY CIRDY CFRAME CC/BE2 CAD17 GND CAD18 CAD19 CVS2 CAD20 CRST CAD21 CAD22 VCC CREQ CAD23 CC/BE3 VCCCB CAD24 CAD25 CAD26 GND CVS1 CINT CSERR CAUDIO CSTSCHG CCLKRUN CCD2 VCC CAD27 CAD28 CAD29 CAD30 CRSVD CAD31 16-BIT ADDR22 ADDR15 ADDR23 ADDR12 ADDR24 GND ADDR7 ADDR25 VS2 ADDR6 RESET ADDR5 ADDR4 VCC INPACK ADDR3 REG VCCCB ADDR2 ADDR1 ADDR0 GND VS1 READY (IREQ) WAIT BVD2 (SPKR) BVD1 (STSCHG/RI) WP (IOIS16) CD2 VCC DATA0 DATA8 DATA1 DATA9 DATA2 DATA10
2-5
Table 2-3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number
TERM. NO. A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D19 E1 E2 E3 E6 E7 E8 SIGNAL NAME CARDBUS NC NC NC NC CAD30 CCD2 CINT CAD24 VCCCB VCC CAD20 GND CTRDY NC NC NC CRSVD VCC CSERR CAD25 CC/BE3 CAD22 CAD19 CAD17 NC NC NC CAD31 CAD27 CAUDIO CAD26 CAD23 CAD21 CAD18 CIRDY NC CCLK NC NC NC NC NC NC NC NC NC NC DATA9 CD2 READY(IREQ) ADDR2 VCCCB VCC ADDR6 GND ADDR22 NC NC NC DATA2 VCC WAIT ADDR1 REG ADDR4 ADDR25 ADDR24 NC NC NC DATA10 DATA0 BVD2(SPKR) ADDR0 ADDR3 ADDR5 ADDR7 ADDR15 NC ADDR16 NC NC NC NC NC NC 16-BIT TERM. NO. E9 E10 E11 E12 E13 E14 E17 E18 E19 F1 F2 F3 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F17 F18 F19 G1 G2 G3 G5 G6 G14 G15 G17 G18 G19 H1 H2 H3 H5 H6 H14 H15 SIGNAL NAME CARDBUS CAD29 CSTSCHG GND CREQ CVS2 CFRAME CDEVSEL CSTOP CBLOCK NC NC NC NC NC NC NC CAD28 CCLKRUN CVS1 CRST CC/BE2 CPERR CGNT VCC CRSVD CC/BE1 NC NC NC NC NC CAD16 CPAR CAD14 CAD15 CAD12 GNT REQ NC NC NC CAD13 GND 16-BIT DATA1 BVD1(STSCHG/RI) GND INPACK VS2 ADDR23 ADDR21 ADDR20 ADDR19 NC NC NC NC NC NC NC DATA8 WP(IOIS16) VS1 RESET ADDR12 ADDR14 WE VCC ADDR18 ADDR8 NC NC NC NC NC ADDR17 ADDR13 ADDR9 IOWR ADDR11 GNT REQ NC NC NC IORD GND TERM. NO. H17 H18 H19 J1 J2 J3 J5 J6 J14 J15 J17 J18 J19 K1 K2 K3 K5 K6 K14 K15 K17 K18 K19 L1 L2 L3 L5 L6 L14 L15 L17 L18 L19 M1 M2 M3 M5 M6 M14 M15 M17 M18 M19 SIGNAL NAME CARDBUS CAD11 CAD10 VCCCB AD31 AD30 AD29 GND AD28 CC/BE0 CAD9 CAD8 VCC CAD7 AD27 AD26 AD25 AD24 C/BE3 CRSVD CAD5 CAD6 CAD3 CAD4 IDSEL VCC AD23 AD21 AD22 CAD1 GND CAD2 CAD0 CCD1 VCCP AD20 PRST GND PCLK NC NC NC VCCD0 VCCD1 OE CE2 VCCCB AD31 AD30 AD29 GND AD28 CE1 ADDR10 DATA15 VCC DATA7 AD27 AD26 AD25 AD24 C/BE3 DATA14 DATA6 DATA13 DATA5 DATA12 IDSEL VCC AD23 AD21 AD22 DATA4 GND DATA11 DATA3 CD1 VCCP AD20 PRST GND PCLK NC NC NC VCCD0 VCCD1 16-BIT
2-6
Table 2-3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number (Continued)
TERM. NO. N1 N2 N3 N5 N6 N14 N15 N17 N18 N19 P1 P2 P3 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P17 P18 P19 SIGNAL NAME CARDBUS AD19 AD18 AD17 IRDY AD16 NC NC NC NC NC C/BE2 FRAME VCC PERR DEVSEL AD13 AD8 RI_OUT/PME MFUNC2 MFUNC5 NC NC NC NC NC NC NC 16-BIT AD19 AD18 AD17 IRDY AD16 NC NC NC NC NC C/BE2 FRAME VCC PERR DEVSEL AD13 AD8 RI_OUT/PME MFUNC2 MFUNC5 NC NC NC NC NC NC NC TERM. NO. R1 R2 R3 R6 R7 R8 R9 R10 R11 R12 R13 R14 R17 R18 R19 T1 T19 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 SIGNAL NAME CARDBUS TRDY STOP SERR AD14 AD10 AD6 GND VCCI MFUNC6 NC NC NC NC NC NC PAR NC AD15 AD11 C/BE0 AD5 AD0 SPKROUT MFUNC4 VPPD1 NC NC 16-BIT TRDY STOP SERR AD14 AD10 AD6 GND VCCI MFUNC6 NC NC NC NC NC NC PAR NC AD15 AD11 C/BE0 AD5 AD0 SPKROUT MFUNC4 VPPD1 NC NC TERM. NO. U15 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 SIGNAL NAME CARDBUS NC AD12 VCCP AD7 AD4 AD1 MFUNC1 GRST VPPD0 NC NC NC C/BE1 GND AD9 VCC AD3 AD2 MFUNC0 MFUNC3 SUSPEND NC NC NC NC NC AD12 VCCP AD7 AD4 AD1 MFUNC1 GRST VPPD0 NC NC NC C/BE1 GND AD9 VCC AD3 AD2 MFUNC0 MFUNC3 SUSPEND NC NC NC NC 16-BIT
2-7
Table 2-4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO. SIGNAL NAME AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 GGU N8 K7 L7 N7 M7 N6 M6 K6 M5 L5 K5 M4 K4 N3 M3 N2 J2 J1 H4 H3 G3 G2 F1 F2 E2 E3 E4 D1 D2 D4 C1 C2 L13 K12 K10 J10 K13 J12 J11 H10 H12 G12 G11 PGE 57 56 55 54 53 52 51 49 47 46 45 43 41 40 39 38 26 25 24 23 19 17 16 15 11 10 9 8 7 5 4 3 76 79 77 81 80 83 82 85 87 89 91 GHK U9 V9 W9 W8 V8 U8 R8 V7 P8 W6 R7 U6 V5 P7 R6 U5 N6 N3 N2 N1 M2 L5 L6 L3 K5 K3 K2 K1 J6 J3 J2 J1 L18 L14 L17 K18 K19 K15 K17 J19 J17 J15 H18 SIGNAL NAME CAD11 CAD12 CAD13 CAD14 CAD15 CAD16 CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31 CAUDIO C/BE0 C/BE1 C/BE2 C/BE3 CBLOCK CC/BE0 CC/BE1 CC/BE2 CC/BE3 CCD1 CCD2 CCLK CCLKRUN CDEVSEL CFRAME CGNT CINT CIRDY CPAR CPERR CREQ GGU G10 F11 F13 E13 F10 E12 D10 B10 A10 C9 A9 D8 A8 C7 D7 A6 C4 A3 B3 C3 B2 B5 N5 N1 J3 E1 D11 H13 E11 A11 B7 L12 A4 B12 D5 B13 B11 C11 D6 A12 D13 C13 B8 TERM. NO. PGE 92 95 93 97 96 98 113 115 116 118 120 121 124 127 128 129 139 140 141 142 144 134 48 37 27 12 103 88 99 112 125 75 137 108 136 107 111 106 132 110 101 104 123 GHK H17 G19 H14 G17 G18 G14 B15 C14 B14 A14 C13 B13 C12 A11 B11 C11 C9 F9 E9 A8 C8 C10 U7 W4 P1 K6 E19 J14 F19 F13 B12 L19 A9 D19 F10 E17 E14 F15 A10 C15 G15 F14 E12 SIGNAL NAME CRST CRSVD CRSVD CRSVD CSERR CSTOP CSTSCHG CTRDY CVS1 CVS2 DEVSEL FRAME GND GND GND GND GND GND GND GND GNT GRST IDSEL IRDY MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 PAR PCLK PERR PRST REQ RI_OUT/PME SERR SPKROUT STOP SUSPEND TRDY VCC GGU B9 A2 E10 J13 A5 C12 C5 A13 C6 D9 L1 J4 D3 H2 L4 M8 K11 F12 C10 B6 B1 M10 F4 K1 K8 N9 K9 N10 L10 N11 M11 M2 H1 L3 G4 A1 L8 M1 M9 L2 L11 K3 F3 TERM. NO. PGE 119 143 100 84 133 105 135 109 131 117 32 28 6 22 42 58 78 94 114 130 2 66 13 29 60 61 64 65 67 68 69 36 21 34 20 1 59 35 62 33 70 31 14 GHK F12 B8 F18 K14 B10 E18 E10 A16 F11 E13 P6 P2 A15 E11 H15 J5 L15 M5 R9 W5 H1 V11 L1 N5 W10 V10 P10 W11 U11 P11 R11 T1 M6 P5 M3 H2 P9 R3 U10 R2 W12 R1 A13
2-8
Table 2-4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number (Continued)
TERM. NO. SIGNAL NAME VCC VCC VCC VCC VCC GGU K2 L6 H11 D12 C8 PGE 30 50 86 102 122 GHK B9 F17 J18 L2 P3 SIGNAL NAME VCC VCCCB VCCCB VCCD0 VCCD1 GGU B4 G13 A7 N13 M13 TERM. NO. PGE 138 90 126 73 74 GHK W7 A12 H19 M18 M19 SIGNAL NAME VCCI VCCP VCCP VPPD0 VPPD1 GGU L9 G1 N4 N12 M12 TERM. NO. PGE 63 18 44 71 72 GHK R10 M1 V6 V12 U12
2-9
Table 2-5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO. SIGNAL NAME AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 GGU N8 K7 L7 N7 M7 N6 M6 K6 M5 L5 K5 M4 K4 N3 M3 N2 J2 J1 H4 H3 G3 G2 F1 F2 E2 E3 E4 D1 D2 D4 C1 C2 A6 D7 C7 A8 D8 A9 C9 B10 E11 E13 G12 PGE 57 56 55 54 53 52 51 49 47 46 45 43 41 40 39 38 26 25 24 23 19 17 16 15 11 10 9 8 7 5 4 3 129 128 127 124 121 120 118 115 99 97 89 GHK U9 V9 W9 W8 V8 U8 R8 V7 P8 W6 R7 U6 V5 P7 R6 U5 N6 N3 N2 N1 M2 L5 L6 L3 K5 K3 K2 K1 J6 J3 J2 J1 C11 B11 A11 C12 B13 C13 A14 C14 F19 G17 J15 SIGNAL NAME ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 ADDR24 ADDR25 BVD1(STSCHG/RI) BVD2(SPKR) C/BE0 C/BE1 C/BE2 C/BE3 CD1 CD2 CE1 CE2 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DEVSEL FRAME F11 A11 D13 C13 A12 B12 E12 E10 D11 C12 B13 A13 B11 D10 A10 C5 B5 N5 N1 J3 E1 L12 A4 H13 G11 C4 B3 A2 L13 K12 J10 J12 H10 A3 C3 B2 K10 K13 J11 J13 H12 L1 J4 TERM. NO. GGU PGE 95 112 101 104 110 108 98 100 103 105 107 109 111 113 116 135 134 48 37 27 12 75 137 88 91 139 141 143 76 79 81 83 85 140 142 144 77 80 82 84 87 32 28 GHK G19 F13 G15 F14 C15 D19 G14 F18 E19 E18 E17 A16 E14 B15 B14 E10 C10 U7 W4 P1 K6 L19 A9 J14 H18 C9 E9 B8 L18 L14 K18 K15 J19 F9 A8 C8 L17 K19 K17 K14 J17 P6 P2 SIGNAL NAME GND GND GND GND GND GND GND GND GNT GRST IDSEL INPACK IORD IOWR IRDY MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 OE PAR PCLK PERR PRST READY(IREQ) REG REQ RESET RI_OUT/PME SERR SPKROUT STOP SUSPEND TRDY VCC VCC VCC VCC VCC VCC D3 H2 L4 M8 K11 F12 C10 B6 B1 M10 F4 B8 F13 F10 K1 K8 N9 K9 N10 L10 N11 M11 G10 M2 H1 L3 G4 D6 B7 A1 B9 L8 M1 M9 L2 L11 K3 F3 K2 L6 H11 D12 C8 TERM. NO. GGU PGE 6 22 42 58 78 94 114 130 2 66 13 123 93 96 29 60 61 64 65 67 68 69 92 36 21 34 20 132 125 1 119 59 35 62 33 70 31 14 30 50 86 102 122 GHK A15 E11 H15 J5 L15 M5 R9 W5 H1 V11 L1 E12 H14 G18 N5 W10 V10 P10 W11 U11 P11 R11 H17 T1 M6 P5 M3 A10 B12 H2 F12 P9 R3 U10 R2 W12 R1 A13 B9 F17 J18 L2 P3
2-10
Table 2-5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number (Continued)
TERM. NO. SIGNAL NAME VCC VCCCB VCCCB VCCD0 VCCD1 GGU B4 G13 A7 N13 M13 PGE 138 90 126 73 74 GHK W7 A12 H19 M18 M19 SIGNAL NAME VCCI VCCP VCCP VPPD0 VPPD1 L9 G1 N4 N12 M12 TERM. NO. GGU PGE 63 18 44 71 72 GHK R10 M1 V6 V12 U12 SIGNAL NAME VS1 VS2 WAIT WE WP(IOIS16) C6 D9 A5 C11 D5 TERM. NO. GGU PGE 131 117 133 106 136 GHK F11 E13 B10 F15 F10
2-11
The terminals are grouped in tables by functionality (see Table 2-6 through Table 2-16), such as PCI system function and power-supply function. The terminal numbers are also listed for convenient reference. Table 2-6. Power Supply Terminals
TERMINAL NUMBER NAME GGU B6, C10, D3, F12, H2, K11, L4, M8 B4, C8, D12, F3, H11, K2, L6 A7, G13 L9 G1, N4 PGE 6, 22, 42, 58, 78, 94, 114, 130 14, 30, 50, 86, 102, 122, 138 90, 126 63 18, 44 GHK A15, E11, H15, J5, L15, M5, R9, W5 A13, B9, F17, J18, L2, P3, W7 A12, H19 R10 M1, V6 DESCRIPTION
GND
Device ground terminals
VCC VCCCB VCCI VCCP
Power supply terminal for core logic (3.3 V)
Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V. Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V Clamp voltage for PCI signaling, 5 V or 3.3 V
Table 2-7. PC Card Power Switch Terminals
TERMINAL NUMBER NAME VCCD0 VCCD1 VPPD0 VPPD1 GGU N13 M13 N12 M12 PGE 73 74 71 72 GHK M18 M19 V12 U12 O O Logic controls to the TPS2211 PC Card power interface switch to control AVCC. Logic controls to the TPS2211 PC Card power interface switch to control AVPP. I/O DESCRIPTION
Table 2-8. PCI System Terminals
TERMINAL NAME NUMBER GGU PGE GHK Global reset. When the global reset is asserted, the GRST signal causes the PCI1410 to place all output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST will normally be asserted only during initial boot. PRST should be used following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST should be tied to PRST. When the SUSPEND mode is enabled, the device is protected from the GRST, and the internal registers are preserved. All outputs are placed in a high-impedance state. PCLK H1 21 M6 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1410 to place all output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1410 is in a default state. When the SUSPEND mode is enabled, the device is protected from the PRST, and the internal registers are preserved. All outputs are placed in a high-impedance state. I/O DESCRIPTION
GRST
M10
66
V11
I
PRST
G4
20
M3
I
2-12
Table 2-9. PCI Address and Data Terminals
TERMINAL NUMBER NAME AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3 C/BE2 C/BE1 C/BE0 GGU C2 C1 D4 D2 D1 E4 E3 E2 F2 F1 G2 G3 H3 H4 J1 J2 N2 M3 N3 K4 M4 K5 L5 M5 K6 M6 N6 M7 N7 L7 K7 N8 E1 J3 N1 N5 PGE 3 4 5 7 8 9 10 11 15 16 17 19 23 24 25 26 38 39 40 41 43 45 46 47 49 51 52 53 54 55 56 57 12 27 37 48 GHK J1 J2 J3 J6 K1 K2 K3 K5 L3 L6 L5 M2 N1 N2 N3 N6 U5 R6 P7 V5 U6 R7 W6 P8 V7 R8 U8 V8 W8 W9 V9 U9 K6 P1 W4 U7 I/O DESCRIPTION
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data.
I/O
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3-C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7-AD0), C/BE1 applies to byte 1 (AD15-AD8), C/BE2 applies to byte 2 (AD23-AD16), and C/BE3 applies to byte 3 (AD31-AD24). PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates even parity across the AD31-AD0 and C/BE3-C/BE0 buses. As an initiator during PCI cycles, the PCI1410 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
PAR
M2
36
T1
I/O
2-13
Table 2-10. PCI Interface Control Terminals
TERMINAL NUMBER NAME GGU L1 PGE 32 GHK P6 I/O PCI device select. The PCI1410 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1410 monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort. PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register (offset 04h, see Section 4.4). PCI bus request. REQ is asserted by the PCI1410 to request access to the PCI bus as an initiator. PCI system error. SERR is an output that is pulsed from the PCI1410 when enabled through bit 8 of the command register (offset 04h, see Section 4.4) indicating a system error has occurred. The PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. I/O DESCRIPTION
DEVSEL
FRAME
J4
28
P2
I/O
GNT
B1
2
H1
I
IDSEL
F4
13
L1
I
IRDY
K1
29
N5
I/O
PERR REQ
L3 A1
34 1
P5 H2
I/O O
SERR
M1
35
R3
O
STOP
L2
33
R2
I/O
TRDY
K3
31
R1
I/O
2-14
Table 2-11. Multifunction and Miscellaneous Terminals
TERMINAL NUMBER NAME GGU K8 PGE 60 GHK W10 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. MFUNC1 N9 61 V10 I/O Serial data (SDA). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC1 terminal provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications. Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. See Section 4.30, Multifunction Routing Register, for configuration details. Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. MFUNC4 L10 67 U11 I/O Serial clock (SCL). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC4 terminal provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications. Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details. Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME signals. Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1410 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is asserted. See Section 3.8.4, Suspend Mode, for details. I/O DESCRIPTION
MFUNC0
MFUNC2
K9
64
P10
I/O
MFUNC3
N10
65
W11
I/O
MFUNC5
N11
68
P11
I/O
MFUNC6 RI_OUT/PME
M11 L8
69 59
R11 P9
I/O O
SPKROUT
M9
62
U10
O
SUSPEND
L11
70
W12
I
2-15
Table 2-12. 16-Bit PC Card Address and Data Terminals
TERMINAL NUMBER NAME ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GGU A10 D10 B11 A13 B13 C12 D11 E10 E12 B12 A12 C13 D13 A11 F11 G12 E13 E11 B10 C9 A9 D8 A8 C7 D7 A6 H12 J13 J11 K13 K10 B2 C3 A3 H10 J12 J10 K12 L13 A2 B3 C4 PGE 116 113 111 109 107 105 103 100 98 108 110 104 101 112 95 89 97 99 115 118 120 121 124 127 128 129 87 84 82 80 77 144 142 140 85 83 81 79 76 143 141 139 GHK B14 B15 E14 A16 E17 E18 E19 F18 G14 D19 C15 F14 G15 F13 G19 J15 G17 F19 C14 A14 C13 B13 C12 A11 B11 C11 J17 K14 K17 K19 L17 C8 A8 F9 J19 K15 K18 L14 L18 B8 E9 C9 I/O DESCRIPTION
O
PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit.
I/O
PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.
2-16
Table 2-13. 16-Bit PC Card Interface Control Terminals
TERMINAL NUMBER NAME GGU PGE GHK Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1410 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 CE1 CE2 L12 A4 H13 G11 75 137 88 91 L19 A9 J14 H18 I Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see Section 5.2, ExCA Interface Status Register. Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. INPACK B8 123 E12 I DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation. I/O read. IORD is asserted by the PCI1410 to enable 16-bit I/O PC Card data output during host I/O read cycles. IORD F13 93 H14 O DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IORD during DMA transfers from the PC Card to host memory. I/O write. IOWR is driven low by the PCI1410 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. IOWR F10 96 G18 O DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IOWR during transfers from host memory to the PC Card. Output enable. OE is driven low by the PCI1410 to enable 16-bit memory PC Card data output during host memory read cycles. OE G10 92 H17 O DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts OE to indicate TC for a DMA write operation. I/O DESCRIPTION
BVD1 (STSCHG/RI)
C5
135
E10
I
BVD2 (SPKR)
B5
134
C10
I
O
2-17
Table 2-13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL NAME NUMBER GGU PGE GHK Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET VS1 VS2 WAIT B9 C6 D9 A5 119 131 117 133 F12 F11 E13 B10 O I/O I PC Card reset. RESET forces a hard reset to a 16-bit PC Card. Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the PC Card. Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in progress. Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts WE to indicate TC for a DMA read operation. Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. WP (IOIS16) D5 136 F10 I I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation. I/O DESCRIPTION
READY (IREQ)
D6
132
A10
I
REG
B7
125
B12
O
WE
C11
106
F15
O
Table 2-14. CardBus PC Card Interface System Terminals
TERMINAL NUMBER NAME GGU PGE GHK CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1410 to indicate that the CCLK frequency is going to be decreased. CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the PCI1410 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. I/O DESCRIPTION
CCLK
B12
108
D19
O
CCLKRUN
D5
136
F10
I/O
CRST
B9
119
F12
O
2-18
Table 2-15. CardBus PC Card Address and Data Terminals
TERMINAL NUMBER NAME CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 CC/BE3 CC/BE2 CC/BE1 CC/BE0 GGU B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13 B7 A11 E11 H13 PGE 144 142 141 140 139 129 128 127 124 121 120 118 116 115 113 98 96 97 93 95 92 91 89 87 85 82 83 80 81 77 79 76 125 112 99 88 GHK C8 A8 E9 F9 C9 C11 B11 A11 C12 B13 C13 A14 B14 C14 B15 G14 G18 G17 H14 G19 H17 H18 J15 J17 J19 K17 K15 K19 K18 L17 L14 L18 B12 F13 F19 J14 I/O DESCRIPTION
I/O
CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31-CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31-CAD0 contain data. CAD31 is the most significant bit.
I/O
CardBus bus commands and byte enables. CC/BE3-CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3-CC/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7-CAD0), CC/BE1 applies to byte 1 (CAD15-CAD8), CC/BE2 applies to byte 2 (CAD23-CAD16), and CC/BE3 applies to byte 3 (CAD31-CAD24). CardBus parity. In all CardBus read and write cycles, the PCI1410 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1410 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator's parity indicator; a compare error results in a parity error assertion.
CPAR
D13
101
G15
I/O
2-19
Table 2-16. CardBus PC Card Interface Control Terminals
TERMINAL NUMBER NAME GGU B5 D11 L12 A4 PGE 134 103 75 137 GHK C10 E19 L19 A9 I I/O I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1410 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. CardBus lock. CBLOCK is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CardBus device select. The PCI1410 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort. CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CardBus bus grant. CGNT is driven by the PCI1410 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK. The PCI1410 can report CSERR to the system by assertion of SERR on the PCI interface. CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a wake-up mechanism. CardBus target ready. CTRDY indicates the ability of the CardBus target ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. I/O DESCRIPTION
CAUDIO CBLOCK CCD1 CCD2
CDEVSEL
B13
107
E17
I/O
CFRAME
B11
111
E14
I/O
CGNT CINT
C11 D6
106 132
F15 A10
O I
CIRDY
A12
110
C15
I/O
CPERR
C13
104
F14
I/O
CREQ
B8
123
E12
I
CSERR
A5
133
B10
I
CSTOP
C12
105
E18
I/O
CSTSCHG
C5
135
E10
I
CTRDY
A13
109
A16
I/O
CVS1 CVS2
C6 D9
131 117
F11 E13
I/O
2-20
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1410. Figure 3-1 shows a simplified block diagram of the PCI1410. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power management control signal), and SPKROUT.
PCI Bus INTA Activity LED Interrupt Controller
TPS2211 Power Switch
4
PCI1410
IRQSER
PCI950 IRQSER Deserializer
IRQ2-15
3 PC Card Socket
68 23 PCI930 ZV Switch
Zoomed Video 19
VGA Controller
Zoomed Video External ZV Port 4
Audio Subsystem
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode 23 terminals are used for routing the ZV signals to the VGA controller and audio subsystem.
Figure 3-1. PCI1410 Simplified Block Diagram
3.1 Power Supply Sequencing
The PCI1410 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltages. The core power supply is always 3.3 V. The clamp voltages can be either 3.3 V or 5 V, depending on the interface. The following power-up and power-down sequences are recommended. The power-up sequence is: 1. Apply 3.3-V power to the core. 2. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply. 3. Apply the clamp voltage. The power-down sequence is: 1. Use GRST to switch outputs to a high-impedance state. 2. Remove the clamp voltage. 3. Remove the 3.3-V power from the core.
3-1
3.2 I/O Characteristics
Figure 3-2 shows a 3-state bidirectional buffer. Section 8.2, Recommended Operating Conditions, provides the electrical characteristics of the inputs and outputs. NOTE:The PCI1410 meets the ac specifications of the 1997 PC Card Standard and PCI Local Bus Specification.
Tied for Open Drain OE Pad VCCP
Figure 3-2. 3-State Bidirectional Buffer NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1410 will be interfaced with: 3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI signaling can be either 3.3 V or 5 V, and the PCI1410 must reliably accommodate both voltage levels. This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply. The PCI1410 requires three separate clamping voltages because it supports a wide range of features. The three voltages are listed and defined in Section 8.2, Recommended Operating Conditions.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1410 is fully compliant with the PCI Local Bus Specification. The PCI1410 provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1410 provides the optional interrupt signal INTA.
3.4.1
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on the PCI1410 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register. See Section 4.30, Multifunction Routing Register, for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
3-2
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI1410 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using LOCK.
3.4.2
Loading Subsystem Identification
The subsystem vendor ID register (see Section 4.26) and subsystem ID register (see Section 4.27) make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 99 requirement. The PCI1410 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting bit 5 (SUBSYSRW) in the system control register (see Section 4.29) at PCI offset 80h. Once this bit is set, the BIOS can write a subsystem identification value into the registers at PCI offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM). In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM. The PCI1410 loads the data from the serial EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1410 core, including the serial bus state machine (see Section 3.8.4, Suspend Mode, for details on using SUSPEND). The PCI1410 provides a two-line serial bus host controller that can interface to a serial EEPROM. See Section 3.6, Serial Bus Interface, for details on the two-wire serial bus controller and applications.
3.5 PC Card Applications
This section describes the PC Card interfaces of the PCI1410: * * * * * * * * Card insertion/removal and recognition P2C power-switch interface Zoomed video support Speaker and audio applications LED socket activity indicators PC Card-16 DMA support PC Card controller programming model CardBus socket registers
3.5.1
PC Card Insertion/Removal and Recognition
The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined. The scheme uses the card detect and voltage sense signals. The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and in Table 3-1.
3-3
Table 3-1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2 Ground Ground Ground Ground Ground Ground Connect to CVS2 Connect to CVS1 Ground Connect to CVS2 Ground Connect to CVS1 Ground Ground CD1//CCD1 Ground Ground Ground Ground Connect to CVS1 Ground Ground Ground Ground Ground Connect to CVS2 Ground Connect to CVS1 Connect to CVS2 VS2//CVS2 Open Open Ground Open Open Ground Connect to CCD2 Ground Ground Connect to CCD2 Connect to CCD1 Open Ground Connect to CCD1 VS1//CVS1 Open Ground Ground Ground Connect to CCD1 Ground Ground Connect to CCD2 Open Open Open Connect to CCD2 Connect to CCD1 Ground KEY 5V 5V 5V LV LV LV LV LV LV LV LV LV INTERFACE 16-bit PC Card 16-bit PC Card 16-bit PC Card 16-bit PC Card CardBus PC Card 16-bit PC Card CardBus PC Card CardBus PC Card 16-bit PC Card CardBus PC Card CardBus PC Card CardBus PC Card Reserved Reserved VOLTAGE 5V 5 V and 3.3 V 5 V, 3.3 V, and X.X V 3.3 V 3.3 V 3.3 V and X.X V 3.3 V and X.X V 3.3 V, X.X V, and Y.Y V Y.Y V Y.Y V X.X V and Y.Y V Y.Y V
3.5.2
P2C Power-Switch Interface (TPS2211)
The PCI1410 provides a P2C (PCMCIA peripheral control) interface for control of the PC Card power switch. The VCCD and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to provide power switch support. Figure 3-3 shows terminal assignments for the TPS2211. Figure 3-4 illustrates a typical application, where the PCI1410 represents the PC Card controller.
VCCD0 VCCD1 3.3V 3.3V 5V 5V GND OC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHDN VPPD0 VPPD1 AVCC AVCC AVCC AVPP 12V
Figure 3-3. TPS2211 Terminal Assignments The PCI1410 also includes support for the Maxim 1602 single-channel CardBus and PCMCIA power-switching network. Application of this power switch would be similar to the TPS2211.
Maxim is a trademark of Maxim Integrated Products, Inc.
3-4
Power Supply 12 V 5V 3.3 V Supervisor 12V 5V 3.3V SHDN SHDN VCCD0 VCCD1 VPPD0 VPPD1 OC TPS2211
AVPP AVCC
VPP1 VPP2 VCC VCC
PC Card
PCI1410 (PC Card Controller)
Figure 3-4. TPS2211 Typical Application
3.5.3
Zoomed Video Support
The PCI1410 allows for the implementation of zoomed video for PC Cards. Zoomed video is supported by setting bit 6 (ZVENABLE) in the card control register (see Section 4.32) on a per-socket function basis. Setting this bit puts PC Card 16 address lines ADDR25-ADDR4 of the PC Card interface in the high-impedance state. These lines can then transfer video and audio data directly to the appropriate controller. Card address lines ADDR3-ADDR0 can still access PC Card CIS registers for PC Card configuration. Figure 3-5 illustrates a PCI1410 ZV implementation.
CRT Motherboard PCI Bus VGA Controller Audio Codec Zoomed Video Port PCM Audio Input 19 PCI1410 4 PC Card 19 PC Card Interface Video Audio 4 Speakers
Figure 3-5. Zoomed Video Implementation Using PCI1410 Not shown in Figure 3-5 is the multiplexing scheme used to route a socket ZV source or an external ZV source to the graphics controller. A typical external source might be provided from a high-speed serial bus like IEEE 1394. The PCI1410 provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers. Figure 3-6 shows an implementation for switching between two ZV streams using external logic.
3-5
PCI1410 ZVSTAT ZVSEL0
Figure 3-6. Zoomed Video Switching Application Figure 3-6 illustrates an implementation using standard three-state bus drivers with active-low output enables. ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled. ZVSTAT is an active-high output indicating that the PCI1410 socket is enabled for ZV mode. The implementation shown in Figure 3-6 can be used if PC Card ZV is prioritized over other sources.
3.5.4
Ultra Zoomed Video
Ultra zoomed video is an enhancement to the PCI1410 DMA engine and is intended to improve the 16-bit bandwidth for MPEG I and MPEG II decoder PC Cards. This enhancement allows the PCI1410 to fetch 32 bits of data from memory versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to the 16-bit PC Card because the PCI1410 prefetches an extra 16 bits (32 bits total) during each PCI read transaction. If the PCI bus becomes busy, then the PCI1410 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the PC Card before having to fetch more data. This feature is built into the DMA engine and software is not required to enable this enhancement. NOTE: The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to support MPEG II PC Card decoders, but it was decided to improve the bandwidth even more in the 14XX series CardBus controllers.
3.5.5
Internal Ring Oscillator
The internal ring oscillator provides an internal clock option for the PCI1410 so that the PCI clock is not required in order for the PCI1410 to power down a socket or interrogate a PC Card. This internal oscillator operates nominally at 16 kHz and can be enabled by setting bit 27 (P2CCLK) of the system control register (offset 80h, see Section 4.29) to 1. This function is disabled by default.
3-6
3.5.6
Integrated Pullup Resistors For PC Card Interface
The 1997 PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit card configurations. Unlike the PCI1210/1211 which required external pullup resistors, the PCI1410 has integrated all of these pullup resistors.
PIN NUMBER SIGNAL NAME ADDR14/CPERR READY/CINT ADDR15/CIRDY CD1/CCD1 VS1/CVS1 ADDR19/CBLOCK ADDR20/CSTOP ADDR21/CDEVSEL ADDR22/CTRDY VS2/CVS2 RESET/CRST WAIT/CSERR INPACK/CREQ BVD2(SPKR)/CAUDIO BVD1(STSCHG)/CSTSCHG CD2/CCD2 GGU C13 D6 A12 L12 C6 D11 C12 B13 A13 D9 B9 A5 B8 B5 C5 A4 PGE 104 132 110 75 131 103 105 107 109 117 119 133 123 134 135 137 GHK F14 A10 C15 L19 F11 E19 E18 E17 A16 E13 F12 B10 E12 C10 E10 A9
3.5.7
SPKROUT and CAUDPWM Usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1410. The CardBus CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket is used in the PCI1410 to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (see Section 4.32). Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI1410 implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2 (AUD2MUX) located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals. Figure 3-7 illustrates a sample application using SPKROUT and CAUDPWM.
3-7
System Core Logic BINARY_SPKR SPKROUT Speaker Subsystem PCI1410 CAUDPWM PWM_SPKR
Figure 3-7. Sample Application of SPKROUT and CAUDPWM
3.5.8
LED Socket Activity Indicators
The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LED_SKT signal can be routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to indicate socket activity. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals. The LED signal is active high and is driven in pulses of 64-ms duration. When the LED is not being driven high, it is driven to a low state. Either of the two circuits shown in Figure 3-8 can be implemented to provide LED signaling and it is left for the board designer to implement the circuit that best fits the application. The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, CIRDY, or CREQ is active.
Current Limiting R 500 PCI1410 LED
ApplicationSpecific Delay PCI1410
Current Limiting R 500 LED
Figure 3-8. Two Sample LED Circuits As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state. If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains driven. If socket activity is frequent (at least once every 64 ms), then the LED signal remains driven.
3.5.9
PC Card-16 Distributed DMA Support
The PCI1410 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA) slave register set provides the programmability necessary for the slave DDMA engine. Table 3-2 provides the DDMA register configuration.
3-8
Two socket-function-dependent PCI configuration header registers that are critical for DDMA are the socket DMA register 0 (offset 94h, see Section 4.35) and the socket DMA register 1 (offset 98h, see Section 4.36). Distributed DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card-16 terminal (SPKR, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. Refer to the programming model and register descriptions (see Section 7 for details). Table 3-2. Distributed DMA Registers
TYPE R W R W R W R W Reserved N/A Mode Multichannel Mask Reserved Reserved Reser ed Reserved N/A Request N/A Master clear Reserved 0Ch Reserved Page REGISTER NAME Current address Base address Current count Base count Status Command 08h 04h 00h DDMA BASE ADDRESS OFFSET
The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1410 implements these obsolete register bits as read-only, nonfunctional bits. The reserved registers shown in Table 3-2 are implemented as read-only and return 0s when read. Write transactions to reserved registers have no effect. The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an 8237 controller, and the PCI1410 awaits a DREQ assertion from the PC Card requesting a DMA transfer. DMA writes transfer data from the PC Card-to-PCI memory addresses. The PCI1410 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal. Once the PCI bus is granted in an idle state, the PCI1410 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1410 accepts the next byte(s) from the PC Card until the transfer count expires. DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the PCI1410 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1410 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the PC Card cycle, the PCI1410 requests access to the PCI bus again until the transfer count has expired. The PCI1410 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1410 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register (DDMA offset 08h, see Section 7.5). At the PC Card interface, the PCI1410 supports demand mode transfers. The PCI1410 asserts DACK during the transfer unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to the WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA register 0.
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3.5.10 PC Card-16 PC/PCI DMA
Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI1410 acts as a PCI target device to certain DMA related I/O addresses. The PCI1410 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals. Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1410) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices. PC/PCI DMA is enabled for each PC Card-16 slot by setting bit 19 (CDREQEN) in the respective system control register (see Section 4.29). On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 (CDMA_EN) of the system control register is a global enable for PC/PCI DMA, and is set at power up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for each PC Card-16 slot must be configured through bits 18-16 (CDMACHAN field) in the system control register. The channels are configured as indicated in Table 3-3. Table 3-3. PC/PCI Channel Assignments
SYSTEM CONTROL REGISTER BIT 18 0 0 0 0 1 1 1 1 BIT 17 0 0 1 1 0 0 1 1 BIT16 0 1 0 1 0 1 0 1 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 DMA CHANNEL CHANNEL TRANSFER DATA WIDTH 8-bit DMA transfers 8-bit DMA transfers 8-bit DMA transfers 8-bit DMA transfers Not used 16-bit DMA transfers 16-bit DMA transfers 16-bit DMA transfers
As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0 (offset 94h, see Section 4.35). The data transfer width is a function of channel number and the DDMA slave registers are not used. When a DREQ is received from a PC Card and the channel has been granted, the PCI1410 decodes the I/O addresses listed in Table 3-4 and performs actions dependent upon the address. Table 3-4. I/O Addresses Used for PC/PCI DMA
DMA I/O ADDRESS 00h 04h C0h C4h DMA CYCLE TYPE Normal Normal TC Verify Verify TC TERMINAL COUNT 0 1 0 1 PCI CYCLE TYPE I/O read/write I/O read/write I/O read I/O read
When the PC/PCI DMA is used as a PC Card-16 DMA mechanism, it may not provide the performance levels of DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason.
3.5.11 CardBus Socket Registers
The PCI1410 contains all registers for compatibility with the latest 1997 PC Card Standard. These registers exist as the CardBus socket registers and are listed in Table 3-5.
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Table 3-5. CardBus Socket Registers
REGISTER NAME Socket event Socket mask Socket present state Socket force event Socket control Reserved Reserved Reserved Socket power management OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h
3.6 Serial Bus Interface
The PCI1410 provides a serial bus interface to load subsystem identification and select register defaults through a serial EEPROM and to provide a PC Card power switch interface alternative to P2C. See Section 3.5.2, P 2C Power-Switch Interface (TPS2211), for details. The PCI1410 serial bus interface is compatible with various I2C and SMBus components.
3.6.1
Serial Bus Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4 terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (offset B3h, see Section 4.50) is set. The SBDETECT bit is cleared by a writeback of 1. The PCI1410 implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal and the SDA signal is mapped to the MFUNC1 terminal. The PCI1410 drives SCL at nearly 100 kHz during data transfers, which is the maximum specified frequency for standard mode I2C. The serial EEPROM must be located at address A0h. Figure 3-9 illustrates an example application implementing the two-wire serial bus.
VCC Serial EEPROM A2 A1 A0 SCL SDA MFUNC4 MFUNC1 5V PCI1410 VCCD0 VCCD1
Figure 3-9. Serial EEPROM Application Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other devices that may enhance the user's PC Card experience. The serial EEPROM device and PC Card power switches are discussed in the sections that follow.
3.6.2
Serial Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3-9. The PCI1410 supports up to 100 Kb/s data transfer rate and is compatible with standard mode I2C using 7-bit addressing.
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All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start condition, which is signalled when the SDA line transitions to a low state while SCL is in the high state, as illustrated in Figure 3-10. The end of a requested data transfer is indicated by a stop condition, which is signalled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-10. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or a stop condition.
SDA
SCL
Start Condition
Stop Condition
Data Line Stable, Data Valid
Change of Data Allowed
Figure 3-10. Serial Bus Start/Stop Conditions and Bit Transfers Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 3-11 illustrates the acknowledge protocol.
SCL From Master 1 2 3 7 8 9
SDA Output By Transmitter
SDA Output By Receiver
Figure 3-11. Serial Bus Protocol Acknowledge The PCI1410 is a serial bus master; all other devices connected to the serial bus external to the PCI1410 are slave devices. As the bus master, the PCI1410 drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle states. Typically, the PCI1410 masters byte reads and byte writes under software control. Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See Section 3.6.3, Serial Bus EEPROM Application, for details on how the PCI1410 automatically loads the subsystem identification and other register defaults through a serial bus EEPROM. Figure 3-12 illustrates a byte write. The PCI1410 issues a start condition and sends the 7-bit slave device address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1410, then bit 6 is set in the serial bus control and status register (offset B3h, see Section 4.50). The word address byte is then sent by the PCI1410 and another slave acknowledgment is expected. Then the PCI1410 delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition.
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Slave Address S b6 b5 b4 b3 b2 b1 b0 0 A
Word Address b7 b6 b5 b4 b3 b2 b1 b0
Data Byte A b7 b6 b5 b4 b3 b2 b1 b0 A P
R/W A = Slave Acknowledgement S/P = Start/Stop Condition
Figure 3-12. Serial Bus Protocol - Byte Write Figure 3-13 illustrates a byte read. The read protocol is very similar to the write protocol except the R/W command bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1410 master must acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers. The SCL signal remains driven by the PCI1410 master.
Slave Address S b6 b5 b4 b3 b2 b1 b0 1 A Word Address b7 b6 b5 b4 b3 b2 b1 b0 A
R/W
Slave Address b6 b5 b4 b3 b2 b1 b0
Data Byte A b7 b6 b5 b4 b3 b2 b1 b0 M P
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3-13. Serial Bus Protocol - Byte Read Figure 3-14 illustrates EEPROM interface doubleword data collection protocol.
Slave Address S Start 1 0 1 0 0 0 0 0 R/W A Word Address b7 b6 b5 b4 b3 b2 b1 b0 A S 1 0 Slave Address 1 0 0 0 0 1 R/W A
Restart
Data Byte 3
M
Data Byte 2
M
Data Byte 1
M
Data Byte 0
M
P
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3-14. EEPROM Interface Doubleword Data Collection
3.6.3
Serial Bus EEPROM Application
When the PCI bus is reset and the serial bus interface is detected, the PCI1410 attempts to read the subsystem identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be loaded with defaults through the EEPROM are provided in Table 3-6. Table 3-6. Registers and Bits Loadable Through Serial EEPROM
OFFSET REFERENCE 01h 02h 03h 04h PCI OFFSET 40h 80h 8Ch 90h REGISTER Subsystem vendor ID, subsystem ID System control Multifunction routing Retry status, card control, device control, diagnostic BITS LOADED FROM EEPROM 31-0 31-30, 27, 26, 24, 15, 14, 6-3, 1 27-0 31, 28-24, 22, 19-16, 15, 7, 6
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Figure 3-15 details the EEPROM data format. This format must be followed for the PCI1410 to properly load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR bit (bit 0) in the serial bus control and status register (offset B3h, see Section 4.50).
Slave Address = 1010 000
Reference(0) Byte 3 (0) Byte 2 (0) Byte 1 (0) Byte 0 (0) RSVD RSVD RSVD Reference(1)
Word Address 00h Word Address 01h Word Address 02h Word Address 03h Word Address 04h Reference(n) Byte 3 (n) Byte 2 (n) Byte 1 (n) Byte 0 (n) RSVD RSVD Word Address 08h RSVD EOL Word Address 8 x (n) Word Address 8 x (n-1) Word Address 8 x (n-1) + 1 Word Address 8 x (n-1) + 2 Word Address 8 x (n-1) + 3 Word Address 8 x (n-1) + 4
Figure 3-15. EEPROM Data Format The byte at the EEPROM word address 00h must either contain a valid offset reference, as listed in Table 3-6, or an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the PCI1410. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 3-9) assumes the 1010b high address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 3-14. The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word addresses align with the data format illustrated in Figure 3-15. The PCI1410 continues to load data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures. Note, the eight-byte data structure is important to provide correct addressing per the doubleword read format shown in Figure 3-14. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h, 03h, 04h. If the offsets are not sequential, then the registers will be loaded incorrectly.
3.6.4
Accessing Serial Bus Devices Through Software
The PCI1410 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3-7 lists the registers used to program a serial bus device through software. Table 3-7. PCI1410 Registers Used to Program Serial Bus Devices
PCI OFFSET B0h B1h B2h B3h REGISTER NAME Serial bus data Serial bus index Serial bus slave address Serial bus control and status DESCRIPTION Contains the data byte to send on write commands or the received data byte on read commands The content of this register is sent as the word address on byte writes or reads. This register is not used in the quick command protocol. Write transactions to this register initiate a serial bus transaction. The slave device address and the R/W command selector are programmed through this register. Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol select bit is programmed through this register.
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To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be programmed with the byte address, and the serial bus slave address register must be programmed with the 7-bit slave address (SLAVADDR field) and bit 0 (RWCMD) must be reset. On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register must be programmed with the 7-bit slave address (SLAVADDR field) and bit 0 (RWCMD) must be set, and bit 5 (REQBUSY) in the serial bus control and status register (see Section 4.50) must be polled until clear. Then the contents of the serial bus data register are valid read data from the serial bus interface.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1410. The PCI1410 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1410 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI1410 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1410, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI1410 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1410 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0-MFUNC6.
3.7.1
PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1410 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 3-8 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: * * * 16-bit memory card 16-bit I/O card CardBus cards
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Table 3-8. Interrupt Mask and Flag Registers
CARD TYPE 16 bit 16-bit memory EVENT Battery conditions (BVD1, BVD2) Wait states (READY) Change in card status (STSCHG) 16-bit 16 bit I/O Interrupt request (IREQ) Power cycle complete Change in card status (CSTSCHG) Interrupt request (CINT) Power cycle complete Card insertion or removal MASK ExCA offset 05h/805h bits 1 and 0 ExCA offset 05h/805h bit 2 ExCA offset 05h/805h bit 0 Always enabled ExCA offset 05h/805h bit 3 Socket mask bit 0 Always enabled Socket mask bit 3 Socket mask bits 2 and 1 FLAG ExCA offset 04h/804h bits 1 and 0 ExCA offset 04h/804h bit 2 ExCA offset 04h/804h bit 0 PCI configuration offset 91h bit 0 ExCA offset 04h/804h bit 3 Socket event bit 0 PCI configuration offset 91h bit 0 Socket event bit 3 Socket event bits 2 and 1
All 16-bit PC Cards
CardBus
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the card type. Table 3-9 describes the PC Card interrupt events. Table 3-9. PC Card Interrupt Events and Description
CARD TYPE EVENT Battery conditions (BVD1, BVD2) Wait states (READY) Change in card status (STSCHG) 16 bit I/O 16-bit Interrupt request (IREQ) Change in card status (CSTSCHG) CardBus Interrupt request (CINT) Card insertion or removal Power cycle complete TYPE SIGNAL BVD1(STSCHG)//CSTSCHG CSC BVD2(SPKR)//CAUDIO CSC CSC Functional CSC Functional READY(IREQ)//CINT BVD1(STSCHG)//CSTSCHG READY(IREQ)//CINT BVD1(STSCHG)//CSTSCHG READY(IREQ)//CINT CD1//CCD1, CD2//CCD2 N/A DESCRIPTION A transition on BVD1 indicates a change in the PC Card battery conditions. A transition on BVD2 indicates a change in the PC Card battery conditions. A transition on READY indicates a change in the ability of the memory PC Card to accept or provide data. The assertion of STSCHG indicates a status change on the PC Card. The assertion of IREQ indicates an interrupt request from the PC Card. The assertion of CSTSCHG indicates a status change on the PC Card. The assertion of CINT indicates an interrupt request from the PC Card. A transition on either CD1//CCD1 or CD2//CCD2 indicates an insertion or removal of a 16-bit or CardBus PC Card. An interrupt is generated when a PC Card power-up cycle has completed.
16-bit memory
CSC
All PC Cards
CSC
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a double slash (//).
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The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI1410 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1410 interrupt scheme can be used to notify the host system (see Table 3-9), denoted by the power cycle complete event. This interrupt source is considered a PCI1410 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2
Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3-9 by setting the appropriate bits in the PCI1410. By individually masking the interrupt sources listed, software can control those events that cause a PCI1410 interrupt. Host software has some control over the system interrupt the PCI1410 asserts by programming the appropriate routing registers. The PCI1410 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. When an interrupt is signaled by the PCI1410, the interrupt service routine must determine which of the events listed in Table 3-8 caused the interrupt. Internal registers in the PCI1410 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 3-8 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI1410 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. Table 3-8 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 (IFCMODE) in the ExCA global control register (see Section 5.20), located at ExCA offset 1Eh/81Eh, and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket force event register (see Section 6.4). Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning.
3.7.3
Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6-MFUNC0, implemented in the PCI1410 may be routed to obtain a subset of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register (offset 92h, see Section 4.33), located at PCI offset 92h, to select the parallel IRQ signaling scheme. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions. As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11, and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3-16. Not shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel PCI interrupts to the host.
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PCI1410 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6
PIC IRQ3 IRQ4 IRQ5 IRQ10 IRQ11 IRQ15
Figure 3-16. IRQ Implementation Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration of a system implementing the PCI1410. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction terminals. The parallel ISA type IRQ signaling from the MFUNC6-MFUNC0 terminals is compatible with those input directly into the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints may demand more MFUNC6-MFUNC0 IRQ terminals than the PCI1410 makes available.
3.7.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling mode, and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed to INTA (MFUNC0).
3.7.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1410 uses a single terminal to communicate all interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems.
3.7.6
SMI Support in the PCI1410
The PCI1410 provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme. SMI interrupts are generated by the PCI1410, when enabled, after a write cycle to either the socket control register (see Section 6.5) of the CardBus register set or the ExCA power control register (ExCA offset 02h, see Section 5.3) causes a power cycle change sequence sent on the power switch interface. The SMI control is programmed through three bits in the system control register (offset 80h, see Section 4.29). These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3-10 describes the SMI control bits function. Table 3-10. SMI Control
BIT NAME SMIROUTE SMISTATUS SMIENB FUNCTION This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. When set, SMI interrupt generation is enabled.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC. The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit (bit 1) in the ExCA global control register (ExCA offset 1Eh, see Section 5.20). If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNC1, MFUNC3, or MFUNC6 through the multifunction routing register (offset 8Ch, see Section 4.30).
3-18
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1410, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section.
3.8.1
Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1410. CLKRUN signalling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not always available to the system designer, and alternate power-saving features are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide. The PCI1410 does not permit the central resource to stop the PCI clock under any of the following conditions: * * * * * * * * * * * Bit 1 (KEEPCLK) in the system control register (offset 80h, see Section 4.29) is set. The PC Card-16 resource manager is busy. The PCI1410 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1410 master is busy. There may be posted data from CardBus to PCI in the PCI1410. Interrupts are pending. The CardBus CCLK for either socket has not been stopped by the PCI1410 CCLKRUN manager.
The PCI1410 restarts the PCI clock using the CLKRUN protocol under any of the following conditions: A PC Card-16 IREQ or a CardBus CINT has been asserted. A CardBus CBWAKE (CSTSCHG) or PC Card-16 STSCHG/RI event occurs. A CardBus attempts to start the CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ.
3.8.2
CardBus PC Card Power Management
The PCI1410 implements its own card power management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management.
3.8.3
16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h, see Section 5.3) and PWRDWN bit (bit 0) of the ExCA global control register (ExCA offset1Eh, see Section 5.20) are provided for 16-bit PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDWN bit will not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes.
3-19
3.8.4
Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global reset) signal from the PCI1410. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI1410 in order to minimize power consumption. Gating PCLK does not create any issues with respect to the power switch interface in the PCI1410. This is because the PCI1410 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock the power switch interface in the PCI1410: * * Use an external clock to the PCI1410 PCLK terminal Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine. Figure 3-17 is a logic diagram.
xRST xRSTIN PCI1410 Core SUSPEND GNT PCLK SUSPENDIN
PCLKIN
Figure 3-17. Suspend Logic Diagram Figure 3-18 is a signal diagram of the suspend function.
3-20
xRST
GNT
SUSPEND
PCLK
External Terminals Internal Signals
xRSTIN
SUSPENDIN
PCLKIN
Figure 3-18. Signal Diagram of Suspend Function
3.8.5
Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which would require the reconfiguration of the PCI1410 by software. Asserting the SUSPEND signal places the controller PCI outputs in a high impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI1410 when SUSPEND is asserted because the outputs are in a high-impedance state. The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the appropriate PCI1410 registers.
3.8.6
Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform requirements. RI_OUT on the PCI1410 can be asserted under any of the following conditions: * * * A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call. A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up. A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery voltage levels.
Figure 3-19 shows various enable bits for the PCI1410 RI_OUT function; however, it does not show the masking of CSC events. See Table 3-8 for a detailed description of CSC interrupt masks and flags.
3-21
RI_OUT Function CSTSMASK PC Card Socket Card I/F RIENB RINGEN
RI_OUT
CDRESUME
Figure 3-19. RI_OUT Functional Diagram RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when a 16-bit card is powered in the socket. The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask bit (bit 0, CSTSMASK) is programmed through the socket mask register (CardBus offset 04h, see Section 6.2) in the CardBus socket registers.
3.8.7
PCI Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software-visible power management states that result in varying levels of power savings. The four power management states of PCI functions are: * * * D0 - Fully-on state D1 and D2 - Intermediate states D3 - Off state
Similarly, bus power states of the PCI bus are B0-B3. The bus power states B0-B3 are derived from the device power state of the originating bridge device. For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should support four power management operations. These operations are: * * * * Capabilities reporting Power status reporting Setting the power state System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (offset 06h, see Section 4.5). The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1410, a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more items in the list, then the next item pointer should be set to 0. The registers following the next item pointer are specific to the capabilities of their corresponding power management functions. The PCI power management capability implements the register block outlined in Table 3-11.
3-22
Table 3-11. Power Management Registers
REGISTER NAME Power management capabilities PM data PMCSR bridge support extensions Next-item pointer Capability ID OFFSET A0h A4h
Power management control/status
The power management capabilities register (offset A2h, see Section 4.39) provides information on the capabilities of the function related to power management. The power management control/status register (offset A4h, see Section 4.40) enables control of power management states and enables/monitors power management events. The data register is an optional register that can provide dynamic data. For more information on PCI power management, see the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges.
3.8.8
CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold without losing wake-up context (also called PME context). The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake up are as follows: * Preservation of device context: The specification states that a reset must occur when transitioning from D3 to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear the PME context registers. Power source in D3cold if wake-up support is required from this state. Two resets are provided to handle preservation of PME context bits: - - Global reset (GRST) is used only on the initial boot up of the system after power up. It places the PCI1410 in its default state and requires BIOS to configure the device before becoming fully functional. PCI reset (PRST) now has dual functionality based on whether PME is enabled or not. If PME is enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset. Please see the master list of PME context bits in Section 3.8.10.
* *
The Texas Instruments PCI1410 addresses these D3 wake-up issues in the following manner:
*
Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an auxiliary power source must be supplied to the PCI1410 VCC pins. Consult the PCI14xx Implementation Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information.
3.8.9
ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver. The PCI1410 offers a generic interface that is compliant with ACPI design rules. Two doublewords of general-purpose ACPI programming bits reside in PCI1410 PCI configuration space at offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event status and enable bits reside in general-purpose event status (offset A8h, see Section 4.43) and general-purpose event enable (offset AAh, see Section 4.44) registers. The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3-20.
3-23
Status Bit Event Input Enable Bit Event Output
Figure 3-20. Block Diagram of a Status/Enable Cell The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the pending status bit. The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. A hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report events. For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.10 Master List of PME Context Bits and Global Reset Only Bits
If the PME enable bit (bit 8) of the power management control/status register (PCI offset A4h, see Section 4.40) is asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted, then the PME context bits are cleared with PRST. The PME context bits are: * * * * * * * * * * Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6 Power management capabilities register (PCI offset A2h, see Section 4.39): bit 15 Power management control/status register (PCI offset A4h, see Section 4.40): bits 15, 8 ExCA power control register (ExCA offset 802h, see Section 5.3): bits 4, 3, 1, 0 ExCA interrupt and general control (ExCA offset 803h, see Section 5.4): bits 6, 5 ExCA card status-change-interrupt configuration register (ExCA offset 805h, see Section 5.6): bits 3-0 CardBus socket event register (CardBus offset 00h, see Section 6.1): bits 3-0 CardBus socket mask register (CardBus offset 04h, see Section 6.2): bits 3-0 CardBus socket present state register (CardBus offset 08h, see Section 6.3): bits 13-10, 7, 5-0 CardBus socket control register (CardBus offset 10h, see Section 6.5): bits 6-4, 2-0
Global reset will place all registers in their default state regardless of the state of the PME enable bit. The GRST signal is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally, thus preserving all register contents. The registers cleared by GRST are: * * * * * * * * * * * * * * * * * * * * Subsystem vendor ID (PCI offset 40h, see Section 4.26): bits 15-0 Subsystem ID (PCI offset 42h, see Section 4.27): bits 15-0 PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31-1 System control register (PCI offset 80h, see Section 4.29): bits 31, 30, 27, 26, 24-14, 7-0 Multifunction routing register (PCI offset 8Ch, see Section 4.30): bits 27-0 Retry status register (PCI offset 90h, see Section 4.31): bits 7, 6, 3, 1 Card control register (PCI offset 91h, see Section 4.32): bits 7-5, 2-0 Device control register (PCI offset 92h, see Section 4.33): bits 7-5, 3-0 Diagnostic register (PCI offset 93h, see Section 4.34): bits 7-0 Socket DMA register 0 (PCI offset 94h, see Section 4.35): bits 1-0 Socket DMA register 1 (PCI offset 98h, see Section 4.36): bits 15-4, 2-0 General-purpose event enable register (PCI offset AAh, see Section 4.44): bits 15, 11, 8, 4-0 General-purpose output (PCI offset AEh, see Section 4.46): bits 4-0 Serial bus data (PCI offset B0h, see Section 4.47): bits 7-0 Serial bus index (PCI offset B1h, see Section 4.48): bits 7-0 Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7-0 Serial bus control and status register (PCI offset B3h, see Section 4.50): bits 7, 2 ExCA identification and revision register (ExCA offset 00h, see Section 5.1): bits 7-0 ExCA card status change register (ExCA offset 804h, see Section 5.5): bits 3-0 ExCA global control register (ExCA offset 1Eh, see Section 5.20): bits 3-0
3-24
4 PC Card Controller Programming Model
This section describes the PCI1410 PCI configuration registers that make up the 256-byte PCI configuration header for each PCI1410 function. As noted, some bits are global in nature and are accessed only through function 0.
4.1 PCI Configuration Registers
The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99 compliant as well. Table 4-1 shows the PCI configuration header, which includes both the predefined portion of the configuration space and the user-definable registers. Table 4-1. PCI Configuration Registers
REGISTER NAME Device ID Status PCI class code BIST Secondary status CardBus latency timer Subordinate bus number Header type Latency timer Reserved CardBus bus number Memory base register 0 Memory limit register 0 Memory base register 1 Memory limit register 1 I/O base register 0 I/O limit register 0 I/O base register 1 I/O limit register 1 Bridge control Subsystem ID Reserved System control Reserved Multifunction routing Diagnostic Device control Card control Retry status Socket DMA register 0 Socket DMA register 1 Reserved Power management capabilities Power management data Power management control/status bridge support extensions Next-item pointer Capability ID Interrupt pin PC Card 16-bit I/F legacy-mode base address Interrupt line Subsystem vendor ID CardBus socket/ExCA base-address Capability pointer PCI bus number Vendor ID Command Revision ID Cache line size OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h-7Ch 80h 84h-88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h-FCh
Power management control/status General-purpose event status General-purpose input Serial bus index Serial bus data
General-purpose event enable General-purpose output Serial bus control and status Serial bus slave address Reserved
4-1
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates bit field names, a detailed field description, and field access tags, which appear in the type column of the bit description table. Table 4-2 describes the field access tags. Table 4-2. Bit Field Access Tag Descriptions
ACCESS TAG R W S C U NAME Read Write Set Clear Field may be read by software. Field may be written by software to any value. Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of 1. Writes of 0 have no effect. MEANING
Update Field may be autonomously updated by the PCI1410. A bit may display either of two types of behavior when read. After having been read it can maintain the value it had previously, or the read process can cause it to be reset to 0.
4.2 Vendor ID Register
This 16-bit register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch.
Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 0 3 R 1 2 R 1 1 R 0 0 R 0 Vendor ID
Register: Offset: Type: Default:
Vendor ID 00h Read-only 104Ch
4.3 Device ID Register
This 16-bit register contains a value assigned to the PCI1410 by TI. The device identification for the PCI1410 is AC50h.
Bit Name Type Default R 1 R 0 R 1 R 0 R 1 R 1 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 1 3 R 0 2 R 0 1 R 0 0 R 0 Device ID
Register: Offset: Type: Default:
Device ID 02h Read-only AC50h
4-2
4.4 Command Register
The command register provides control over the PCI1410 interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification. See Table 4-3 for the complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R/W 0 4 R 0 3 R 0 2 R/W 0 1 R/W 0 0 R/W 0 Command
Register: Offset: Type: Default:
BIT 15-10 9 SIGNAL RSVD FBB_EN
Command 04h Read-only, Read/Write 0000h Table 4-3. Command Register
TYPE R R Reserved. Bits 15-10 return 0s when read. Fast back-to-back enable. The PCI1410 does not generate fast back-to-back transactions; therefore, bit 9 returns 0 when read. System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the PCI1410 to report address parity errors. 0 = Disable SERR output driver (default) 1 = Enable SERR output driver Address/data stepping control. The PCI1410 does not support address/data stepping; therefore, bit 7 is hardwired to 0. Parity error response enable. Bit 6 controls the response of the PCI1410 to parity errors through PERR. Data parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting SERR. 0 = PCI1410 ignores detected parity error (default) 1 = PCI1410 responds to detected parity errors VGA palette snoop. When bit 5 is set to 1, palette snooping is enabled (that is, the PCI1410 does not respond to palette register writes and snoops the data). When bit 5 is 0, the PCI1410 treats all palette accesses like all other accesses. Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write and invalidate commands. The PCI1410 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1410 does not respond to special cycle operations; therefore, this bit is hardwired to 0. Bus master control. Bit 2 controls whether or not the PCI1410 can act as a PCI bus initiator (master). The PCI1410 can take control of the PCI bus only when this bit is set. 0 = Disables the ability of the PCI1410 to generate PCI bus accesses (default) 1 = Enables the ability of the PCI1410 to generate PCI bus accesses Memory space enable. Bit 1 controls whether or not the PCI1410 can claim cycles in PCI memory space. 0 = Disables the PCI1410 from responding to memory space accesses (default) 1 = Enables the PCI1410 to respond to memory space accesses I/O space control. Bit 0 controls whether or not the PCI1410 can claim cycles in PCI I/O space. 0 = Disables the PCI1410 from responding to I/O space accesses (default) 1 = Enables the PCI1410 to respond to I/O space accesses FUNCTION
8
SERR_EN
R/W
7
STEP_EN
R
6
PERR_EN
R/W
5
VGA_EN
R/W
4
MWI_EN
R
3
SPECIAL
R
2
MAST_EN
R/W
1
MEM_EN
R/W
0
IO_EN
R/W
4-3
4.5 Status Register
The status register provides device information to the host system. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each function. See Table 4-4 for a complete description of the register contents.
Bit Name Type Default R/C 0 R/C 0 R/C 0 R/C 0 R/C 0 R 0 R 1 0 15 14 13 12 11 10 9 8 Status R/C R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0
Register: Offset: Type: Default:
BIT 15 14 13 12 11 10-9 SIGNAL PAR_ERR SYS_ERR MABORT TABT_REC TABT_SIG PCI_SPEED
Status 06h Read-only, Read/Clear 0210h Table 4-4. Status Register
TYPE R/C R/C R/C R/C R/C R FUNCTION Detected parity error. Bit 15 is set when a parity error is detected (either address or data). Signaled system error. Bit 14 is set when SERR is enabled and the PCI1410 signals a system error to the host. Received master abort. Bit 13 is set when a cycle initiated by the PCI1410 on the PCI bus has been terminated by a master abort. Received target abort. Bit 12 is set when a cycle initiated by the PCI1410 on the PCI bus was terminated by a target abort. Signaled target abort. Bit 11 is set by the PCI1410 when it terminates a transaction on the PCI bus with a target abort. DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the PCI1410 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses. Data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred, and the following conditions were met: a. PERR was asserted by any PCI device including the PCI1410. b. The PCI1410 was the bus master during the data parity error. c. The parity error response bit is set in the command register (offset 04h, see Section 4.4). Fast back-to-back capable. The PCI1410 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. User-definable feature support. The PCI1410 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 66-MHz capable. The PCI1410 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI capabilities are implemented. The linked list of PCI power management capabilities is implemented in this function. Reserved. Bits 3-0 return 0s when read.
8
DATAPAR
R/C
7 6 5
FBB_CAP UDF 66MHZ
R R R
4 3-0
CAPLIST RSVD
R R
4-4
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI1410.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Revision ID R 0 R 0 R 0 R 1 3 2 1 0
Register: Offset: Type: Default:
Revision ID 08h Read-only 01h
4.7 PCI Class Code Register
The class code register recognizes the PCI1410 as a bridge device (06h) and CardBus bridge device (07h) with a 00h programming interface.
Bit Name Base class Type Default R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 0 R 0 R 0 R 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI class code Subclass R 0 R 0 R 1 R 1 R 1 R 0 R 0 Programming interface R 0 R 0 R 0 R 0 R 0 R 0
Register: Offset: Type: Default:
PCI class code 09h Read-only 06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Cache line size
Register: Offset: Type: Default:
Cache line size 0Ch Read/Write 00h
4-5
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI1410 in units of PCI clock cycles. When the PCI1410 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the PCI1410 transaction has terminated, then the PCI1410 terminates the transaction when its GNT is deasserted.
Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 Latency timer R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0
Register: Offset: Type: Default:
Latency timer 0Dh Read/Write 00h
4.10 Header Type Register
This register returns 02h when read, indicating that the PCI1410 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h-FFh are user-definable extension registers.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Header type R 0 R 0 R 1 R 0 3 2 1 0
Register: Offset: Type: Default:
Header type 0Eh Read-only 02h
4.11 BIST Register
Because the PCI1410 does not support a built-in self-test (BIST), this register returns the value of 00h when read.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 BIST R 0 R 0 R 0 R 0 3 2 1 0
Register: Offset: Type: Default:
BIST 0Fh Read-only 00h
4-6
4.12 CardBus Socket/ExCA Base-Address Register
The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31-12 are read/write and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11-0 are read-only, returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 0 10 31 30 29 28 27 26 R/W 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 CardBus socket/ExCA base-address
CardBus socket/ExCA base-address
Register: Offset: Type: Default:
CardBus socket/ExCA base-address 10h Read-only, Read/Write 0000 0000h
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. The socket has its own capability pointer register. This register returns A0h when read.
Bit Name Type Default R 1 R 0 R 1 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Capability pointer
Register: Offset: Type: Default:
Capability pointer 14h Read-only A0h
4-7
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates CardBus-related device information to the host system. This register is very similar to the PCI status register (offset 06h); status bits are cleared by writing a 1. See Table 4-5 for a complete description of the register contents.
Bit Name Type Default R/C 0 R/C 0 R/C 0 R/C 0 R/C 0 R 0 R 1 15 14 13 12 11 10 9 8 R/C 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Secondary status
Register: Offset: Type: Default:
BIT 15 14 13 12 11 10-9 SIGNAL CBPARITY CBSERR CBMABORT REC_CBTA SIG_CBTA CB_SPEED
Secondary status 16h Read-only, Read/Clear 0200h Table 4-5. Secondary Status Register
TYPE R/C R/C R/C R/C R/C R FUNCTION Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1410 does not assert CSERR. Received master abort. Bit 13 is set when a cycle initiated by the PCI1410 on the CardBus bus has been terminated by a master abort. Received target abort. Bit 12 is set when a cycle initiated by the PCI1410 on the CardBus bus is terminated by a target abort. Signaled target abort. Bit 11 is set by the PCI1410 when it terminates a transaction on the CardBus bus with a target abort. CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the PCI1410 asserts CB_SPEED at a medium speed. CardBus data parity error detected. 0 = The conditions for setting bit 8 have not been met. 1 = A data parity error occurred and the following conditions were met: a. CPERR was asserted on the CardBus interface. b. The PCI1410 was the bus master during the data parity error. c. The parity error response bit is set in the bridge control. Fast back-to-back capable. The PCI1410 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. User-definable feature support. The PCI1410 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 66-MHz capable. The PCI1410 CardBus interface operates at a maximum CCLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Reserved. Bits 4-0 return 0s when read.
8
CB_DPAR
R/C
7 6 5 4-0
CBFBB_CAP CB_UDF CB66MHZ RSVD
R R R R
4-8
4.15 PCI Bus Number Register
This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1410 is connected. The PCI1410 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 PCI bus number
Register: Offset: Type: Default:
PCI bus number 18h Read/Write 00h
4.16 CardBus Bus Number Register
This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1410 is connected. The PCI1410 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 CardBus bus number
Register: Offset: Type: Default:
CardBus bus number 19h Read/Write 00h
4.17 Subordinate Bus Number Register
This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1410 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Subordinate bus number
Register: Offset: Type: Default:
Subordinate bus number 1Ah Read/Write 00h
4-9
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the PCI1410 CardBus interface in units of CCLK cycles. When the PCI1410 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins counting. If the latency timer expires before the PCI1410 transaction has terminated, then the PCI1410 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 CardBus latency timer
Register: Offset: Type: Default:
CardBus latency timer 1Bh Read/Write 00h
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used by the PCI1410 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31-12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11-0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register (offset 3Eh, see Section 4.25) specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1410 to claim any memory transactions through the CardBus memory windows (that is, these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 Memory base registers 0, 1
Memory base registers 0, 1
Register: Offset: Register: Offset: Type: Default:
Memory base register 0 1Ch Memory base register 1 24h Read-only, Read/Write 0000 0000h
4-10
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used by the PCI1410 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31-12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11-0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1410 to claim any memory transactions through CardBus memory windows (that is, these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R 0 24 R/W 0 8 R 0 23 R/W 0 7 R 0 22 R/W 0 6 R 0 21 R/W 0 5 R 0 20 R/W 0 4 R 0 19 R/W 0 3 R 0 18 R/W 0 2 R 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0 Memory limit registers 0, 1
Memory limit registers 0, 1
Register: Offset: Type: Default:
Memory limit registers 0, 1 20h, 28h Read-only, Read/Write 0000 0000h
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the PCI1410 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of these registers locate the bottom of the I/O window within a 64-Kbyte page, and the upper 16 bits (31-16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31-2 are read/write. Bits 1 and 0 are read-only and always return 0s, forcing the I/O window to be aligned on a natural doubleword boundary. NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 0 9 R/W 31 30 29 28 27 26 25 R/W 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R 0 16 R/W 0 0 R 0
I/O base registers 0, 1
I/O base registers 0, 1
Register: Offset: Type: Default:
I/O base registers 0, 1 2Ch, 34h Read-only, Read/Write 0000 0000h
4-11
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1410 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI. The lower 16 bits of these registers locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15-2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31-16 of the appropriate I/O base) on doubleword boundaries. Bits 31-16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1 and 0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write transactions to read-only bits have no effect. The PCI1410 assumes that the lower 2 bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 R/W 31 30 29 28 27 26 25 24 R 0 8 R/W 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R 0 16 R 0 0 R 0
I/O limit registers 0, 1
I/O limit registers 0, 1
Register: Offset: Type: Default:
I/O limit registers 0, 1 30h, 38h Read-only, Read/Write 0000 0000h
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information.
Bit Name Type Default R/W 1 R/W 1 R/W 1 1 7 6 5 4 Interrupt line R/W R/W 1 R/W 1 R/W 1 R/W 1 3 2 1 0
Register: Offset: Type: Default:
Interrupt line 3Ch Read/Write FFh
4-12
4.24 Interrupt Pin Register
The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode, selected through bits 2-1 (INTMODE field) of the device control register (offset 92h, see Section 4.33). The PCI1410 defaults to serialized PCI and ISA interrupt mode.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Interrupt pin R 0 R 0 R 0 R 1 3 2 1 0
Register: Offset: Type: Default:
Interrupt pin 3Dh Read-only 01h
4-13
4.25 Bridge Control Register
The bridge control register provides control over various PCI1410 bridging functions. See Table 4-6 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 1 15 14 13 12 11 10 9 8 R/W 1 7 R/W 0 6 R/W 1 5 R/W 0 4 R 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Bridge control
Register: Offset: Type: Default:
Bridge control 3Eh Read-only, Read/Write 0340h Table 4-6. Bridge Control Register
BIT 15-11 10
SIGNAL RSVD POSTEN
TYPE R R/W Reserved. Bits 15-11 return 0s when read.
FUNCTION Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst cycles. Note that burst write data can be posted, but various write transactions may not. Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket dependent. Bit 9 is encoded as: 0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default). Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is encoded as: 0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default). PCI interrupt - IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers. 0 = Functional interrupts routed to PCI interrupts (default) 1 = Functional interrupts routed by ExCAs CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted by passing a PRST assertion to CardBus. 0 = CRST deasserted 1 = CRST asserted (default) Master abort mode. Bit 5 controls how the PCI1410 responds to a master abort when the PCI1410 is an initiator on the CardBus interface. 0 = Master aborts not reported (default) 1 = Signal target abort on PCI and SERR (if enabled) Reserved. Bit 4 returns 0 when read. VGA enable. Bit 3 affects how the PCI1410 responds to VGA addresses. When this bit is set, accesses to VGA addresses are forwarded. ISA mode enable. Bit 2 affects how the PCI1410 passes I/O cycles within the 64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI1410 does not forward the last 768 bytes of each 1K I/O range to CardBus. CSERR enable. Bit 1 controls the response of the PCI1410 to CSERR signals on the CardBus bus. This bit is common between the two sockets. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. CardBus parity error response enable. Bit 0 controls the response of the PCI1410 to CardBus parity errors. This bit is common between the two sockets. 0 = CardBus parity errors are ignored. 1 = CardBus parity errors are reported using CPERR.
9
PREFETCH1
R/W
8
PREFETCH0
R/W
7
INTR
R/W
6
CRST
R/W
5
MABTMODE
R/W
4 3
RSVD VGAEN
R R/W
2
ISAEN
R/W
1
CSERREN
R/W
0
CPERREN
R/W
4-14
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (offset 80h, see Section 4.29).
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Subsystem vendor ID
Register: Offset: Type: Default:
Subsystem vendor ID 40h Read-only (Read/Write if enabled by SUBSYSRW) 0000h
4.27 Subsystem ID Register
The subsystem ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (offset 80h, see Section 4.29).
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Subsystem ID
Register: Offset: Type: Default:
Subsystem ID 42h Read-only (Read/Write if enabled by SUBSYSRW) 0000h
4.28 PC Card 16-bit I/F Legacy-Mode Base-Address Register
The PCI1410 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See Section 5, ExCA Compatibility Registers, for register offsets.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 31 30 29 28 27 26 R/W 0 10 R/W 0 25 R/W 0 9 R/W 0 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R 1 PC Card 16-bit I/F legacy-mode base address
PC Card 16-bit I/F legacy-mode base address
Register: Offset: Type: Default:
PC Card 16-bit I/F legacy-mode base address 44h Read-only, Read/Write 0000 0001h
4-15
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. See Table 4-7 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R/W 1 R/W 0 R 0 R 1 R 0 R 0 R 0 R/W 0 15 R/W 0 14 R 0 13 R 0 12 R/W 0 11 R/W 0 10 R/C 0 9 31 30 29 28 27 26 25 24 R/W 0 8 R 0 23 R 0 7 R/W 0 22 R/W 1 6 R/W 1 21 R/W 0 5 R/W 1 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 1 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 System control
System control
Register: Type: Offset: Default:
System control Read-only, Read/Write, Read/Clear 80h 0044 9060h
4-16
Table 4-7. System Control Register
BIT SIGNAL TYPE FUNCTION Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31 and 30 are encoded as follows: 31-30 SER_STEP R/W 00 = INTA signaled in INTA IRQSER slots 01 = INTA signaled in INTB IRQSER slots 10 = INTA signaled in INTC IRQSER slots 11 = INTA signaled in INTD IRQSER slots Reserved. Bits 29 and 28 return 0s when read. Internal oscillator enable. 0 = Internal oscillator disabled (default) 1 = Internal oscillator enabled. SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket. 0 = PC Card power change interrupts routed to IRQ2 (default) 1 = A CSC interrupt is generated on PC Card power changes. SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket power. Writing a 1 to bit 25 clears the status. 0 = SMI interrupt signaled (default) 1 = SMI interrupt not signaled SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt signaling is enabled and generates an interrupt. This bit is shared and defaults to 0 (disabled). Reserved. Bit 23 returns 0 when read. CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus terminals are driven low. When this bit is 0, these signals are placed in a high-impedance state. 0 = Place CardBus RSVD in a high`-impedance state 1 = Drive Cardbus RSVD low (default) VCC protection enable. 0 = VCC protection enabled for 16-bit cards (default) 1 = VCC protection disabled for 16-bit cards Reduced zoomed video enable. When this bit is enabled, pins ADDR25-ADDR22 of the card interface for PC Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This bit is encoded as: 0 = Reduced zoomed video disabled (default) 1 = Reduced zoomed video enabled PC/PCI DMA card enable. When bit 19 is set, the PCI1410 allows 16-bit PC Cards to request PC/PCI DMA using the DREQ signaling. DREQ is selected through the socket DMA register (offset 94h, see Section 4.35). 0 = Ignore DREQ signaling from PC Cards (default) 1 = Signal DMA request on DREQ PC/PCI DMA channel assignment. Bits 18-16 are encoded as: 0-3 = 8-bit DMA channels 4 = Not used (default) 5-7 = 16-bit DMA channels Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst downstream. 0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default). Memory read burst enable upstream. When bit 14 is set, the PCI1410 allows memory read transactions to burst upstream. 0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled.
29-28 27
RSVD OSEN
R R/W
26
SMIROUTE
R/W
25
SMISTATUS
R/C
24 23
SMIENB RSVD
R/W R
22
CBRSVD
R/W
21
VCCPROT
R/W
20
REDUCEZV
R/W
19
CDREQEN
R/W
18-16
CDMACHAN
R/W
15
MRBURSTDN
R/W
14
MRBURSTUP
R/W
4-17
Table 4-7. System Control Register (Continued)
BIT SIGNAL TYPE FUNCTION Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and is cleared upon read of this status bit. 0 = No socket activity (default) 1 = Socket activity Reserved. Bit 12 returns 1 when read. Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch is in progress and a powering change has been requested. This bit is cleared when the power stream is complete. 0 = Power stream is complete and delay has expired. 1 = Power stream is in progress. Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay has expired. Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been sent to the power switch and proper power may not yet be stable. This bit is cleared when the power-down delay has expired. Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when interrogation completes. This bit is socket dependent. 0 = Interrogation not in progress (default) 1 = Interrogation in progress Auto power switch enable. 0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3) is disabled (default). 1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3) is enabled. Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock, then the applicable CB state machine will not be clocked. Subsystem ID (see Section 4.27), subsystem vendor ID (see Section 4.26), ExCA identification and revision (see Section 5.1) registers read/write enable. 0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write. 1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only (default). CardBus data parity SERR signaling enable 0 = CardBus data parity not signaled on PCI SERR 1 = CardBus data parity signaled on PCI SERR PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC0-MFUNC6 are configured for centralized DMA. 0 = Centralized DMA disabled (default) 1 = Centralized DMA enabled ExCA power control bit. Enabled by selecting the 82365SL mode. 0 = Enables 3.3 V 1 = Enables 5 V Keep clock. This bit works with PCI and CB CLKRUN protocols. 0 = Allows normal functioning of both CLKRUN protocols (default) 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols RI_OUT/PME multiplex enable. 0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled at the same time, then RI_OUT has precedence over PME. 1 = Only PME is routed to the RI_OUT/PME terminal.
13
SOCACTIVE
R
12
RSVD
R
11
PWRSTREAM
R
10
DELAYUP
R
9
DELAYDOWN
R
8
INTERROGATE
R
7
AUTOPWRSWEN
R/W
6
PWRSAVINGS
R/W
5
SUBSYSRW
R/W
4
CB_DPAR
R/W
3
CDMA_EN
R/W
2
ExCAPower
R/W
1
KEEPCLK
R/W
0
RIMUX
R/W
4-18
4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0-MFUNC6 terminals. These terminals may be configured for various functions. All multifunction terminals default to the general-purpose input configuration. This register is intended to be programmed once at power-on initialization. The default value for this register may also be loaded through a serial bus EEPROM. See Table 4-8 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 R 0 15 R 0 14 R 0 13 R 0 12 R/W 0 11 R/W 0 10 0 9 R/W 31 30 29 28 27 26 25 R/W 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Multifunction routing
Multifunction routing
Register: Offset: Type: Default:
BIT 31-28 SIGNAL RSVD
Multifunction routing 8Ch Read-only, Read/Write 0000 0000h Table 4-8. Multifunction Routing Register
TYPE R Bits 31-28 return 0s when read. Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0001 = CLKRUN 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal as follows: 0000 = GPI4 0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT 0001 = GPO4 0101 = RSVD 1001 = IRQ9 1101 = LED_SKT 0010 = PCGNT 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15 Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal as follows: NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the MFUNC4 terminal provides the SCL signaling. 0000 = GPI3 0001 = GPO3 0010 = LOCK PCI 0011 = IRQ3 0100 = IRQ4 0101 = IRQ5 0110 = ZVSTAT 0111 = ZVSEL0 1000 = CAUDPWM 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1100 = RI_OUT 1101 = LED_SKT 1110 = GPE 1111 = IRQ15 FUNCTION
27-24
MFUNC6
R/W
23-20
MFUNC5
R/W
19-16
MFUNC4
R/W
15-12
MFUNC3
R/W
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal as follows: 0000 = RSVD 0100 = IRQ4 1000 = IRQ8 1100 = IRQ12 0001 = IRQSER 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = IRQ2 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal as follows: 0000 = GPI2 0100 = IRQ4 1000 = CAUDPWM 1100 = RI_OUT 0001 = GPO2 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = PCREQ 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ7
11-8
MFUNC2
R/W
4-19
Table 4-8. Multifunction Routing Register (Continued)
BIT SIGNAL TYPE FUNCTION Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal as follows: NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the MFUNC1 terminal provides the SDA signaling. 0000 = GPI1 0001 = GPO1 0010 = RSVD 0011 = IRQ3 0100 = IRQ4 0101 = IRQ5 0110 = ZVSTAT 0111 = ZVSEL0 1000 = CAUDPWM 1001 = IRQ9 1010 = IRQ10 1011 = IRQ11 1100 = LED_SKT 1101 = IRQ13 1110 = GPE 1111 = IRQ15
7-4
MFUNC1
R/W
3-0
MFUNC0
R/W
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal as follows: 0000 = GPI0 0100 = IRQ4 1000 = CAUDPWM 1100 = LED_SKT 0001 = GPO0 0101 = IRQ5 1001 = IRQ9 1101 = IRQ13 0010 = INTA 0110 = ZVSTAT 1010 = IRQ10 1110 = GPE 0011 = IRQ3 0111 = ZVSEL0 1011 = IRQ11 1111 = IRQ15
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set when the PCI1410 retries a PCI or CardBus master request and the master does not return within 215 PCI clock cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI command, PCI status, and bridge control registers by the PCI SIG. See Table 4-9 for a complete description of the register contents.
Bit Name Type Default R/W 1 R/W 1 R 0 R 0 7 6 5 4 Retry status R/C 0 R 0 R/C 0 R 0 3 2 1 0
Register: Offset: Type: Default:
BIT 7 SIGNAL PCIRETRY
Retry status 90h Read-only, Read/Write, Read/Clear C0h Table 4-9. Retry Status Register
TYPE R/W FUNCTION PCI retry timeout counter enable. Bit 7 is encoded: 0 = PCI retry counter disabled 1 = PCI retry counter enabled (default) CardBus retry timeout counter enable. Bit 6 is encoded: 0 = CardBus retry counter disabled 1 = CardBus retry counter enabled (default) Reserved. Bits 5 and 4 return 0s when read. CardBus target retry expired. Write a 1 to clear bit 3. 0 = Inactive (default) 1 = Retry has expired. Reserved. Bit 2 returns 0 when read. PCI target retry expired. Write a 1 to clear bit 1. 0 = Inactive (default) 1 = Retry has expired. Reserved. Bit 0 returns 0 when read.
6 5-4 3 2 1 0
CBRETRY RSVD TEXP_CB RSVD TEXP_PCI RSVD
R/W R R/C R R/C R
4-20
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See Table 4-10 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 R 0 7 6 5 4 Card control R 0 R/W 0 R/W 0 R/C 0 3 2 1 0
Register: Offset: Type: Default:
BIT SIGNAL
Card control 91h Read-only, Read/Write, Read/Clear 00h Table 4-10. Card Control Register
TYPE FUNCTION Ring indicate output enable. 0 = Disables any routing of RI_OUT signal (default). 1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when bit 0 (RIMUX) in the system control register (see Section 4.29) is set to 0, and for routing to MFUNC2 or MFUNC4. Compatibility ZV mode enable. When set, the PC Card socket interface ZV terminals enter a high-impedance state. This bit defaults to 0. This bit has no assigned function. Reserved. Bits 4 and 3 return 0 when read. CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding multifunction terminal which may be configured for CAUDPWM. Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The SPKROUT terminal drives data only when the socket SPKROUTEN bit is set. This bit is encoded as: 0 = SPKR to SPKROUT not enabled (default) 1 = SPKR to SPKROUT enabled Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected.
7
RIENB
R/W
6 5 4-3 2
ZVENABLE No function RSVD AUD2MUX
R/W R/W R R/W
1
SPKROUTEN
R/W
0
IFG
R/C
4-21
4.33 Device Control Register
The device control register is provided for PCI1130 compatibility. The interrupt mode select and the socket-capable force bits are programmed through this register. See Table 4-11 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 1 R/W 1 R 0 7 6 5 4 Device control R/W 0 R/W 1 R/W 1 R/W 0 3 2 1 0
Register: Offset: Type: Default:
BIT 7 SIGNAL SKTPWR_LOCK
Device control 92h Read-only, Read/Write 66h Table 4-11. Device Control Register
TYPE R/W FUNCTION Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card socket while in D3. This may be necessary to support wake on LAN or RING if the operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state. 3-V socket capable force 0 = Not 3-V capable 1 = 3-V capable (default) Diagnostic bit. This bit defaults to 1. Reserved. Bit 4 returns 0 when read. TI test. Only a 0 should be written to bit 3. Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling mode bits are encoded: 00 = Parallel PCI interrupts only 01 = Parallel IRQ and parallel PCI interrupts 10 = IRQ serialized interrupts and parallel PCI interrupt 11 = IRQ and PCI serialized interrupts (default) Reserved. Bit 0 is reserved for test purposes. Only 0 should be written to this bit.
6 5 4 3
3VCAPABLE IO16V2 RSVD TEST
R/W R/W R R/W
2-1
INTMODE
R/W
0
RSVD
R/W
4-22
4.34 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s should be written to it. See Table 4-12 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 1 R/W 0 7 6 5 4 Diagnostic R/W 0 R/W 0 R/W 0 R/W 1 3 2 1 0
Register: Offset: Type: Default:
BIT 7 6 SIGNAL TRUE_VAL RSVD
Diagnostic 93h Read/Write 21h Table 4-12. Diagnostic Register
TYPE R/W R/W FUNCTION This bit defaults to 0. This bit is encoded as: 0 = Reads true values in PCI vendor ID and PCI device ID registers (default) 1 = Reads all 1s in the PCI vendor ID and PCI device ID registers Reserved. Bit 6 returns 0 when read. CSC interrupt routing control 0 = CSC interrupts routed to PCI if ExCA 803 (see Section 5.4) bit 4 = 1 1 = CSC interrupts routed to PCI if ExCA 805 (see Section 5.6) bits 7-4 = 0000b (default) In this case, the setting of ExCA 803 bit 4 is a don't care. Diagnostic RETRY_DIS. Delayed transaction disable. Diagnostic RETRY_EXT. Extends the latency from 16 to 64. Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. Asynchronous interrupt enable. 0 = CSC interrupt is not generated asynchronously 1 = CSC interrupt is generated asynchronously (default)
5
CSC
R/W
4 3 2 1 0
DIAG4 DIAG3 DIAG2 DIAG1 ASYNCINT
R/W R/W R/W R/W R/W
4-23
4.35 Socket DMA Register 0
The socket DMA register 0 provides control over the PC Card DMA request (DREQ) signaling. See Table 4-13 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Socket DMA register 0
Socket DMA register 0
Register: Offset: Type: Default:
BIT 31-2 SIGNAL RSVD
Socket DMA register 0 94h Read-only, Read/Write 0000 0000h Table 4-13. Socket DMA Register 0
TYPE R Reserved. Bits 31-2 return 0s when read. DMA request (DREQ). Bits 1 and 0 indicate which pin on the 16-bit PC Card interface acts as DREQ during DMA transfers. This field is encoded as: 00 = Socket not configured for DMA (default). 01 = DREQ uses SPKR. 10 = DREQ uses IOIS16. 11 = DREQ uses INPACK. FUNCTION
1-0
DREQPIN
R/W
4-24
4.36 Socket DMA Register 1
The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI I/O address space. See Table 4-14 for a complete description of the register contents. NOTE:32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 R/W 31 30 29 28 27 26 25 24 R 0 8 R/W 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Socket DMA register 1
Socket DMA register 1
Register: Offset: Type: Default:
BIT 31-16 SIGNAL RSVD
Socket DMA register 1 98h Read-only, Read/Write 0000 0000h Table 4-14. Socket DMA Register 1
TYPE R Reserved. Bits 31-16 return 0s when read. DMA base address. Locates the socket's DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode. Thus, the window is aligned to a natural 16-byte boundary. Extended addressing. This feature is not supported by the PCI4410 and always returns a 0. Transfer size. Bits 2 and 1 specify the width of the DMA transfer on the PC Card interface and are encoded as: 00 = Transfers are 8 bits (default). 01 = Transfers are 16 bits. 10 = Reserved 11 = Reserved DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value of bits 15-4 (DMABASE field). 0 = Disabled (default) 1 = Enabled FUNCTION
15-4
DMABASE
R/W
3
EXTMODE
R
2-1
XFERSIZE
R/W
0
DDMAEN
R/W
4-25
4.37 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Capability ID R 0 R 0 R 0 R 1 3 2 1 0
Register: Offset: Type: Default:
Capability ID A0h Read-only 01h
4.38 Next-Item Pointer Register
The next-item pointer register indicates the next item in the linked list of the PCI power management capabilities. Because the PCI1410 functions include only one capabilities item, this register returns 0s when read.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Next-item pointer
Register: Offset: Type: Default:
Next-item pointer A1h Read-only 00h
4-26
4.39 Power Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. Both PCI1410 CardBus bridge functions support D0, D1, D2, and D3 power states. See Table 4-15 for a complete description of the register contents.
Bit Name Type Default R/W 1 R 1 R 1 R 1 R 1 R 1 15 14 13 12 11 10 9 R 1 8 R 0 7 R 0 6 R 0 5 R 1 4 R 0 3 R 0 2 R 0 1 R 0 0 R 1 Power management capabilities
Register: Offset: Type: Default:
BIT SIGNAL
Power management capabilities A2h Read/Write, Read-only FE21h Table 4-15. Power Management Capabilities Register
TYPE FUNCTION PME support. This 5-bit field indicates the power states from which the PCI1410 device functions may assert PME. A 0 (zero) for any bit indicates that the function cannot assert the PME signal while in that power state. These five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
R/W
Bit 15 defaults to the value 1 indicating the PME signal can be asserted from the D3cold state. This bit is R/W because wake-up support from D3cold is contingent on the system providing an auxiliary power source to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC terminals for D3cold wake-up support, then BIOS should write a 0 to this bit. Bit 14 contains the value 1, indicating that the PME signal can be asserted from D3hot state. Bit 13 contains the value 1, indicating that the PME signal can be asserted from D2 state. Bit 12 contains the value 1, indicating that the PME signal can be asserted from D1 state. Bit 11 contains the value 1, indicating that the PME signal can be asserted from the D0 state. D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device power state. D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device power state. Reserved. Bits 8-6 return 0s when read. Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function requires special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3cold) is set. When bit 4 is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary power source. PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1410 to generate PME. Version. Bits 2-0 return 001b when read, indicating that there are four bytes of general-purpose power management (PM) registers as described in the PCI Bus Power Management Interface Specification.
14-11
PME_Support
R
10 9 8-6 5
D2_Support D1_Support RSVD DSI
R R R R
4
AUX_PWR
R
3 2-0
PMECLK VERSION
R R
4-27
4.40 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI1410 CardBus function. The contents of this register are not affected by the internally-generated reset caused by the transition from D3hot to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3hot to D0 state transition. TI-specific registers, PCI power management registers, and the legacy base address register are not reset. See Table 4-16 for a complete description of the register contents.
Bit Name Type Default R/C 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R/W 0 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R/W 0 0 R/W 0 Power management control/status
Register: Offset: Type: Default:
BIT 15 SIGNAL PMESTAT
Power management control/status A4h Read-only, Read/Write, Read/Write to Clear 0000h Table 4-16. Power Management Control/Status Register
TYPE R/C FUNCTION PME status. Bit 15 is set when the CardBus function would normally assert PME, independent of the state of bit 8 (PME_EN). Bit 15 is cleared by a write back of 1, and this also clears the PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by bit 4 (DYN_DATA_PME_EN). Data select. This 4-bit field returns 0s when read. The CardBus function does not return any dynamic data as indicated by bit 4 (DYN_DATA_PME_EN). PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. Reserved. Bits 7-5 return 0s when read. Dynamic data PME enable. Bit 4 returns 0 when read since the CardBus function does not report dynamic data. Reserved. Bits 3-2 return 0s when read. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. This field is encoded as: 00 = D0 01 = D1 10 = D2 11 = D3hot
14-13 12-9 8 7-5 4 3-2
DATASCALE DATASEL PME_EN RSVD DYN_DATA_PME_EN RSVD
R R R/W R R R
1-0
PWR_STATE
R/W
4-28
4.41 Power Management Control/Status Bridge Support Extensions Register
The power management control/status register bridge support extensions support PCI bridge specific functionality. See Table 4-17 for a complete description of the register contents.
Bit Name Type Default R 1 R 1 7 6 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Power management control/status bridge support extensions
Register: Offset: Type: Default:
BIT SIGNAL
Power management control/status bridge support extensions A6h Read-only C0h
TYPE FUNCTION BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read. This bit is encoded as: 0 = Bus power/clock control is disabled. 1 = Bus power/clock control is enabled (default). A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled, the bridge power management control/status register power state field (see Section 4.40, bits 1-0) cannot be used by the system software to control the power or the clock of the bridge secondary bus. A 1 indicates that the bus power/clock control mechanism is enabled. B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded as: 0 = When the bridge is programmed to D3hot, its secondary bus will have its power removed (B3). 1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock will be stopped (B2). (Default) Reserved. Bits 5-0 return 0s when read.
Table 4-17. Power Management Control/Status Bridge Support Extensions Register
7
BPCC_EN
R
6
B2_B3
R
5-0
RSVD
R
4.42 Power Management Data Register
The power management data register returns 0s when read, since the CardBus functions do not report dynamic data.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Power management data
Register: Offset: Type: Default:
Power management data A7h Read-only 00h
4-29
4.43 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1 to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit in the general-purpose enable register. See Table 4-18 for a complete description of the register contents.
Bit Name Type Default R/C 0 R 0 R 0 R 0 R/C 0 R 0 15 14 13 12 11 10 9 R 0 8 R/C 0 7 R 0 6 R 0 5 R 0 4 R/C 0 3 R/C 0 2 R/C 0 1 R/C 0 0 R/C 0 General-purpose event status
Register: Offset: Type: Default:
BIT 15 14-12 11 10-9 8 7-5 4 3 2 1 0 SIGNAL ZV_STS RSVD PWR_STS RSVD VPP12_STS RSVD GP4_STS GP3_STS GP2_STS GP1_STS GP0_STS
General-purpose event status A8h Read-only, Read/Write to Clear 0000h Table 4-18. General-Purpose Event Status Register
TYPE R/C R R/C R R/C R R/C R/C R/C R/C R/C FUNCTION PC card ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the card control register (offset 91h, see Section 4.32). Reserved. Bits 14-12 return 0s when read. Power change status. Bit 11 is set when software has changed the power state of the socket. A change in either VCC or VPP for the socket causes this bit to be set. Reserved. Bits 10 and 9 return 0s when read. 12-Volt VPP request status. Bit 8 is set when software has changed the requested Vpp level to or from 12 Volts for the PC Card socket. Reserved. Bits 7-5 return 0s when read. GPI4 status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. GPI3 status. Bit 3 is set on a change in status of the MFUNC4 terminal input level. GPI2 status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. GPI1 status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. GPI0 status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
4-30
4.44 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the multifunction terminals, MFUNC6-MFUNC0, is configured for GPE signaling. See Table 4-19 for a complete description of the register contents.
Bit Name Type Default R/W 0 R 0 R 0 R 0 R/W 0 R 0 15 14 13 12 11 10 9 R 0 8 R/W 0 7 R 0 6 R 0 5 R 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 General-purpose event enable
Register: Offset: Type: Default:
BIT 15 14-12 11 10-9 8 7-5 4 3 2 1 0 SIGNAL ZV_EN RSVD PWR_EN RSVD VPP12_EN RSVD GP4_EN GP3_EN GP2_EN GP1_EN GP0_EN
General-purpose event enable AAh Read-only, Read/Write 0000h Table 4-19. General-Purpose Event Enable Register
TYPE R/W R R/W R R/W R R/W R/W R/W R/W R/W FUNCTION PC card socket ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE) in the card control register (offset 91h, see Section 4.32). Reserved. Bits 14-12 return 0s when read. Power change enable. When bit 11 is set, a GPE is signaled when software has changed the power state of the socket. Reserved. Bits 10 and 9 return 0s when read. 12 Volt VPP request enable. When bit 8 is set, a GPE is signaled when software has changed the requested VPP level to or from 12 Volts for the card socket. Reserved. Bits 7-5 return 0s when read. GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5 terminal input level if configured as GPI4. GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4 terminal input level if configured as GPI3. GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2 terminal input if configured as GPI2. GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1 terminal input if configured as GPI1. GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0 terminal input if configured as GPI0.
4-31
4.45 General-Purpose Input Register
The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5, MFUNC4, and MFUNC2-MFUNC0. See Table 4-20 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 0 4 R X 3 R X 2 R X 1 R X 0 R X General-purpose input
Register: Offset: Type: Default:
BIT 15-5 4 3 2 1 0 SIGNAL RSVD GPI4_DATA GPI3_DATA GPI2_DATA GPI1_DATA GPI0_DATA
General-purpose input ACh Read-only 00XXh Table 4-20. General-Purpose Input Register
TYPE R R R R R R Reserved. Bits 15-5 return 0s when read. GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5 terminal. GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4 terminal. GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2 terminal. GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1 terminal. GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0 terminal. FUNCTION
4-32
4.46 General-Purpose Output Register
The general-purpose output register is used for control of the general-purpose outputs. See Table 4-21 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 R 0 8 R 0 7 R 0 6 R 0 5 R 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 General-purpose output
Register: Offset: Type: Default:
BIT 15-5 4 3 2 1 0 SIGNAL RSVD GPO4_DATA GPO3_DATA GPO2_DATA GPO1_DATA GPO0_DATA
General-purpose output AEh Read-only, Read/Write 0000h Table 4-21. General-Purpose Output Register
TYPE R R/W R/W R/W R/W R/W Reserved. Bits 15-5 return 0s when read. GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5 terminal if configured as GPO4. Read transactions return the last data value written. GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4 terminal if configured as GPO3. Read transactions return the last data value written. GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2 terminal if configured as GPO2. Read transactions return the last data value written. GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1 terminal if configured as GPO1. Read transactions return the last data value written. GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0 terminal if configured as GPO0. Read transactions return the last data value written. FUNCTION
4.47 Serial Bus Data Register
The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data when generating cycles on the serial bus interface. See Table 4-22 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 R/W 3 Serial bus data R/W 0 R/W 0 R/W 0 R/W 0 2 1 0
Register: Offset: Type: Default:
BIT 7-0 SIGNAL SBDATA
Serial bus data B0h Read/Write 00h Table 4-22. Serial Bus Data Register
TYPE R/W FUNCTION Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit (bit 5) in the serial bus control and status register (offset B3h, see Section 4.50) must be polled to verify that the contents of this register are valid.
4-33
4.48 Serial Bus Index Register
The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte address when generating cycles on the serial bus interface. See Table 4-23 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Serial bus index
Register: Offset: Type: Default:
BIT 7-0 SIGNAL SBINDEX
Serial bus index B1h Read/Write 00h Table 4-23. Serial Bus Index Register
TYPE R/W FUNCTION Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
4.49 Serial Bus Slave Address Register
The serial bus slave address register is for programmable serial bus byte read and write transactions. See Table 4-24 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Serial bus slave address
Register: Offset: Type: Default:
BIT 7-1 SIGNAL SLAVADDR
Serial bus slave address B2h Read/Write 00h Table 4-24. Serial Bus Slave Address Register
TYPE R/W FUNCTION Serial bus slave address. This bit field represents the slave address of a read or write transaction on the serial interface. Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read and write accesses 0 = A byte write access is requested to the serial bus interface 1 = A byte read access is requested to the serial bus interface
0
RWCMD
R/W
4-34
4.50 Serial Bus Control and Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register. See Table 4-25 for a complete description of the register contents.
Bit Name Type Default R/W 0 R 0 R 0 7 6 5 4 R 0 3 R/C 0 2 R/W 0 1 R/C 0 0 R/C 0 Serial bus control and status
Register: Offset: Type: Default:
BIT 7 6 SIGNAL PROT_SEL RSVD
Serial bus control and status B3h Read-only, Read/Write, Read/Clear 00h Table 4-25. Serial Bus Control and Status Register
TYPE R/W R FUNCTION Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte protocol is used on read commands. The word address byte (SBINDEX) in the serial bus index register (see Section 4.48) is not output by the PCI1410 when bit 7 is set. Reserved. Bit 6 returns 0 when read. Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write) is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see Section 4.49). Bit 5 must be polled on reads from the serial bus interface. After the byte read access has been requested, the read data is valid in the serial bus data register. Serial EEPROM busy status. Bit 4 indicates the status of the PCI1410 serial EEPROM circuitry. Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM. 0 = Serial EEPROM circuitry is not busy 1 = Serial EEPROM circuitry is busy Serial bus detect. Bit 3 is set when the serial bus interface is detected through pullup resistors on the VCCD0 and VCCD1 terminals after reset. If bit 3 is cleared, then the MFUNC4 and MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs. 0 = Serial bus interface not detected 1 = Serial bus interface detected Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes. 0 = Serial bus clock at normal operating frequency, 100 kHz (default) 1 = Serial bus clock frequency increased for test purposes Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1. 0 = No error detected during user requested byte read or write cycle 1 = Data error detected during user requested byte read or write cycle EEPROM data error status. Bit 0 indicates when a data error occurs on the serial bus interface during the auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on EEPROM data format. Bit 0 is cleared by a write back of 1. 0 = No error detected during auto-load from serial bus EEPROM 1 = Data error detected during auto-load from serial bus EEPROM
5
REQBUSY
R
4
ROMBUSY
R
3
SBDETECT
R/C
2
SBTEST
R/W
1
REQ_ERR
R/C
0
ROM_ERR
R/C
4-35
4-36
5 ExCA Compatibility Registers
The ExCA registers implemented in the PCI1410 are register-compatible with the Intel 82365SL-DF PCMCIA controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register (offset 44h, see Section 4.28). The offsets from this base address run contiguous from 00h to 3Fh for the socket. See Figure 5-1 for an ExCA I/O mapping illustration.
PCI1410 Configuration Registers Offset Offset PC Card ExCA Registers 00h Host I/O Space
CardBus Socket/ExCA Base Address
10h
Index Data
3Fh
16-Bit Legacy-Mode Base Address
44h
Figure 5-1. ExCA Register Access Through I/O The TI PCI1410 also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI memory space. They are located through the CardBus socket/ExCA base address register (offset 10h, see Section 4.12) at memory offset 800h. See Figure 5-2 for an ExCA memory mapping illustration. This illustration also identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h.
PCI1410 Configuration Registers Offset Host Memory Space Offset 00h CardBus Socket Registers 20h 800h 16-Bit Legacy-Mode Base Address 44h ExCA Registers 844h
CardBus Socket/ExCA Base Address
10h
Figure 5-2. ExCA Register Access Through Memory
5-1
The interrupt registers in the ExCA register set, as defined by the 82365SL-DL specification, control such card functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1410 to ensure that all possible PCI1410 interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to the interrupt signaling are the ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4) and the ExCA card status-change-interrupt configuration register (ExCA offset 05h, see Section 5.6). Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These are regions of host memory space into which the card memory space is mapped. These windows are defined by start, end, and offset addresses programmed in the ExCA registers described in this section. Table 5-1 identifies each ExCA register and its respective ExCA offset. Memory windows have 4K-byte granularity. Table 5-1. ExCA Registers and Offsets
EXCA REGISTER NAME Identification and revision Interface status Power control Interrupt and general control Card status-change Card status-change-interrupt configuration Address window enable I / O window control I / O window 0 start-address low-byte I / O window 0 start-address high-byte I / O window 0 end-address low-byte I / O window 0 end-address high-byte I / O window 1 start-address low-byte I / O window 1 start-address high-byte I / O window 1 end-address low-byte I / O window 1 end-address high-byte Memory window 0 start-address low-byte Memory window 0 start-address high-byte Memory window 0 end-address low-byte Memory window 0 end-address high-byte Memory window 0 offset-address low-byte Memory window 0 offset-address high-byte Card detect and general control Reserved Memory window 1 start-address low-byte Memory window 1 start-address high-byte Memory window 1 end-address low-byte Memory window 1 end-address high-byte Memory window 1 offset-address low-byte Memory window 1 offset-address high-byte PCI MEMORY ADDRESS OFFSET (HEX) 800 801 802 803 804 805 806 807 808 809 80A 80B 80C 80D 80E 80F 810 811 812 813 814 815 816 817 818 819 81A 81B 81C 81D ExCA OFFSET (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D
5-2
Table 5-1. ExCA Registers and Offsets (Continued)
EXCA REGISTER NAME Global control Reserved Memory window 2 start-address low-byte Memory window 2 start-address high-byte Memory window 2 end-address low-byte Memory window 2 end-address high-byte Memory window 2 offset-address low-byte Memory window 2 offset-address high-byte Reserved Reserved Memory window 3 start-address low-byte Memory window 3 start-address high-byte Memory window 3 end-address low-byte Memory window 3 end-address high-byte Memory window 3 offset-address low-byte Memory window 3 offset-address high-byte Reserved Reserved Memory window 4 start-address low-byte Memory window 4 start-address high-byte Memory window 4 end-address low-byte Memory window 4 end-address high-byte Memory window 4 offset-address low-byte Memory window 4 offset-address high-byte I/O window 0 offset-address low-byte I/O window 0 offset-address high-byte I/O window 1 offset-address low-byte I/O window 1 offset-address high-byte Reserved Reserved Reserved Reserved Reserved Reserved Memory window 0 page Memory window 1 page Memory window 2 page Memory window 3 page Memory window 4 page PCI MEMORY ADDRESS OFFSET (HEX) 81E 81F 820 821 822 823 824 825 826 827 828 829 82A 82B 82C 82D 82E 82F 830 831 832 833 834 835 836 837 838 839 83A 83B 83C 83D 83E 83F 840 841 842 843 844 ExCA OFFSET (HEX) 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F - - - - -
5-3
5.1 ExCA Identification and Revision Register
The ExCA identification and revision register provides host software with information on 16-bit PC Card support and Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register (see Section 4.29). See Table 5-2 for a complete description of the register contents.
Bit Name Type Default R 1 R 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 1 1 R/W 0 0 R/W 0 ExCA identification and revision
Register: Offset: Type: Default:
BIT 7-6 5-4 3-0 SIGNAL IFTYPE RSVD 365REV
ExCA identification and revision CardBus socket address + 800h; ExCA offset 00h Read-only, Read/Write 84h Table 5-2. ExCA Identification and Revision Register
TYPE R R/W R/W FUNCTION Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the PCI1410. The PCI1410 supports both I/O and memory 16-bit PC cards. Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation. Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI1410. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. Writing 0010b to this field puts the controller in 82365SL mode. This field defaults to 0100b upon PCI1410 reset.
5-4
5.2 ExCA Interface Status Register
The ExCA interface status register provides information on the current status of the PC Card interface. An X in the default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See Table 5-3 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R X 7 6 5 4 R X 3 R X 2 R X 1 R X 0 R X ExCA interface status
Register: Offset: Type: Default:
BIT 7 SIGNAL RSVD
ExCA interface status CardBus socket address + 801h; ExCA offset 01h Read-only 00XX XXXXb Table 5-3. ExCA Interface Status Register
TYPE R Reserved. Bit 7 returns 0 when read. Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA power control register (ExCA offset 02h, see Section 5.3) is programmed. Bit 6 is encoded as: 0 = VCC and VPP to the socket turned off (default) 1 = VCC and VPP to the socket turned on Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface. 0 = PC Card not ready for data transfer 1 = PC Card ready for data transfer Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to the PCI1410 whether or not the memory card is write protected. Furthermore, write protection for an entire PCI1410 16-bit memory window is available by setting the appropriate bit in the ExCA memory window offset-address high-byte register (see Section 5.18). 0 = WP is 0. PC Card is read/write. 1 = WP is 1. PC Card is read-only. Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and bit 2 (CDETECT1) to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted. Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and bit 3 (CDETECT2) to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted. Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0 reflects BVD1. 00 = Battery dead 01 = Battery dead 10 = Battery low; warning 11 = Battery good When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs. FUNCTION
6
CARDPWR
R
5
READY
R
4
CARDWP
R
3
CDETECT2
R
2
CDETECT1
R
1-0
BVDSTAT
R
5-5
5.3 ExCA Power Control Register
The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See Table 5-4 and Table 5-5 for a complete description of the register contents.
Bit Name Type Default R/W 0 R 0 R 0 7 6 5 4 R/W 0 3 R/W 0 2 R 0 1 R/W 0 0 R/W 0 ExCA power control
Register: Offset: Type: Default:
BIT SIGNAL
ExCA power control CardBus socket address + 802h; ExCA offset 02h Read-only, Read/Write 00h Table 5-4. ExCA Power Control Register 82365SL Support
TYPE FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled Reserved. Bit 6 returns 0 when read. Auto power switch enable. This bit is enabled by bit 7 of the system control register (offset 80h, see Section 4.29). 0 = Automatic socket power switching based on card detects is disabled. 1 = Automatic socket power switching based on card detects is enabled. PC Card power enable. 0 = VCC = VPP1 = VPP2 = No connection 1 = VCC is enabled and controlled by bit 2 (ExCAPower) of the system control register (offset 80h, see Section 4.29), VPP1 and VPP2 are controlled according to bits 1-0 (EXCAVPP field). Reserved. Bits 3 and 2 return 0s when read. PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI1410 ignores this field unless VCC to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as: 00 = No connection (default) 01 = VCC 10 = 12 V 11 = Reserved
7
COE
R/W
6
RSVD
R
5
AUTOPWRSWEN
R/W
4
CAPWREN
R/W
3-2
RSVD
R
1-0
EXCAVPP
R/W
5-6
Table 5-5. ExCA Power Control Register 82365SL-DF Support
BIT 7 6-5 SIGNAL COE RSVD TYPE R/W R FUNCTION Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410. This bit is encoded as: 0 = 16-bit PC Card outputs disabled (default) 1 = 16-bit PC Card outputs enabled Reserved. Bits 6 and 5 return 0s when read. VCC. Bits 4 and 3 are used to request changes to card VCC. This field is encoded as: 00 = 0 V (default) 01 = 0 V reserved 10 = 5 V 11 = 3.3 V Reserved. Bit 2 returns 0 when read. PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI1410 ignores this field unless VCC to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as: 00 = No connection (default) 01 = VCC 10 = 12 V 11 = Reserved
4-3
EXCAVCC
R/W
2
RSVD
R
1-0
EXCAVPP
R/W
5-7
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical 16-bit PC Card functions. See Table 5-6 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA interrupt and general control
Register: Offset: Type: Default:
BIT 7 SIGNAL RINGEN
ExCA interrupt and general control CardBus socket address + 803h; ExCA offset 03h Read/Write 00h Table 5-6. ExCA Interrupt and General Control Register
TYPE R/W FUNCTION Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as: 0 = Ring indicate disabled (default) 1 = Ring indicate enabled Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6 affects 16-bit cards only. This bit is encoded as: 0 = RESET signal asserted (default) 1 = RESET signal deasserted Card type. Bit 5 indicates the PC Card type. This bit is encoded as: 0 = Memory PC Card installed (default) 1 = I/O PC Card installed PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed to PCI interrupts. When low, the card status change interrupts are routed using bits 7-4 (CSCSELECT field) in the ExCA card status change interrupt configuration register (ExCA offset 05h, see Section 5.6). This bit is encoded as: 0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. Card interrupt select for I/O PC Card functional interrupts. Bits 3-0 select the interrupt routing for I/O PC Card functional interrupts. This field is encoded as: 0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. This bit setting is ORed with bit 4 (CSCROUTE) for backwards compatibility. 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0100 = IRQ6 enabled 0111 = IRQ7 enabled 1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled
6
RESET
R/W
5
CARDTYPE
R/W
4
CSCROUTE
R/W
3-0
INTSELECT
R/W
5-8
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (see Section 5.20). See Table 5-7 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 ExCA card status-change
Register: Offset: Type: Default:
BIT 7-4 SIGNAL RSVD
ExCA card status-change CardBus socket address + 804h; ExCA offset 04h Read-only 00h Table 5-7. ExCA Card Status-Change Register
TYPE R Reserved. Bits 7-4 return 0s when read. Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface. This bit is encoded as: 0 = No change detected on either CD1 or CD2 1 = Change detected on either CD1 or CD2 Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a PCI1410 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card is now ready to accept new data. This bit is encoded as: 0 = No low-to-high transition detected on READY (default) 1 = Detected low-to-high transition on READY When a 16-bit I/O card is installed, bit 2 is always 0. Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the source of a PCI1410 interrupt was due to a battery-low warning condition. This bit is encoded as: 0 = No battery warning condition (default) 1 = Detected battery warning condition When a 16-bit I/O card is installed, bit 1 is always 0. Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether the source of a PCI1410 interrupt was due to a battery dead condition. This bit is encoded as: 0 = STSCHG deasserted (default) 1 = STSCHG asserted Ring indicate. When the PCI1410 is configured for ring indicate operation, bit 0 indicates the status of RI. FUNCTION
3
CDCHANGE
R
2
READYCHANGE
R
1
BATWARN
R
0
BATDEAD
R
5-9
5.6 ExCA Card Status-Change-Interrupt Configuration Register
The ExCA card status-change-interrupt configuration register controls interrupt routing for card status-change interrupts, as well as masking CSC interrupt sources. See Table 5-8 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA status-change-interrupt configuration
Register: Offset: Type: Default:
BIT SIGNAL
ExCA card status-change-interrupt configuration CardBus socket address + 805h; ExCA offset 05h Read/Write 00h Table 5-8. ExCA Card Status-Change-Interrupt Configuration Register
TYPE FUNCTION Interrupt select for card status change. Bits 7-4 select the interrupt routing for card status change interrupts. 0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (offset 93h, see Section 4.34) is set to 1. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4) is a don't care . This is the default setting. 0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register (offset 93h, see Section 4.34) is set to 0. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA interrupt and general control register to 1 (see Section 5.4).
7-4
CSCSELECT
R/W
This field is encoded as: 0000 = No interrupt routing (default) 0001 = IRQ1 enabled 0010 = SMI enabled 0011 = IRQ3 enabled 0100 = IRQ4 enabled 0101 = IRQ5 enabled 0110 = IRQ6 enabled 0111 = IRQ7 enabled
1000 = IRQ8 enabled 1001 = IRQ9 enabled 1010 = IRQ10 enabled 1011 = IRQ11 enabled 1100 = IRQ12 enabled 1101 = IRQ13 enabled 1110 = IRQ14 enabled 1111 = IRQ15 enabled
3
CDEN
R/W
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as: 0 = Disables interrupts on CD1 or CD2 line changes (default) 1 = Enables interrupts on CD1 or CD2 line changes Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host interrupt. This interrupt source is considered a card status change. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt. This bit is encoded as: 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion of the STSCHG I/O PC Card signal to generate a CSC interrupt. 0 = Disables host interrupt generation (default) 1 = Enables host interrupt generation
2
READYEN
R/W
1
BATWARNEN
R/W
0
BATDEADEN
R/W
5-10
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By default, all windows to the card are disabled. The PCI1410 does not acknowledge PCI memory or I/O cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window start/end/offset address registers. See Table 5-9 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA address window enable
Register: Offset: Type: Default:
BIT 7 SIGNAL IOWIN1EN
ExCA address window enable CardBus socket address + 806h; ExCA offset 06h Read-only, Read/Write 00h Table 5-9. ExCA Address Window Enable Register
TYPE R/W FUNCTION I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as: 0 = I/O window 1 disabled (default) 1 = I/O window 1 enabled I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as: 0 = I/O window 0 disabled (default) 1 = I/O window 0 enabled Reserved. Bit 5 returns 0 when read. Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is encoded as: 0 = Memory window 4 disabled (default) 1 = Memory window 4 enabled Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is encoded as: 0 = Memory window 3 disabled (default) 1 = Memory window 3 enabled Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is encoded as: 0 = Memory window 2 disabled (default) 1 = Memory window 2 enabled Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is encoded as: 0 = Memory window 1 disabled (default) 1 = Memory window 1 enabled Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is encoded as: 0 = Memory window 0 disabled (default) 1 = Memory window 0 enabled
6 5
IOWIN0EN RSVD
R/W R
4
MEMWIN4EN
R/W
3
MEMWIN3EN
R/W
2
MEMWIN2EN
R/W
1
MEMWIN1EN
R/W
0
MEMWIN0EN
R/W
5-11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See Table 5-10 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O window control
Register: Offset: Type: Default:
ExCA I/O window control CardBus socket address + 807h; ExCA offset 07h Read/Write 00h Table 5-10. ExCA I/O Window Control Register
BIT
SIGNAL
TYPE
FUNCTION I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16. I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16 from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as: 0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16. I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is set. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.
7
WAITSTATE1
R/W
6
ZEROWS1
R/W
5
IOSIS16W1
R/W
4
DATASIZE1
R/W
3
WAITSTATE0
R/W
2
ZEROWS0
R/W
1
IOSIS16W0
R/W
0
DATASIZE0
R/W
5-12
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the start address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O windows 0 and 1 start-address low-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 start-address low-byte CardBus socket address + 808h; ExCA offset 08h ExCA I/O window 1 start-address low-byte CardBus socket address + 80Ch; ExCA offset 0Ch Read/Write 00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the start address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O windows 0 and 1 start-address high-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 start-address high-byte CardBus socket address + 809h; ExCA offset 09h ExCA I/O window 1 start-address high-byte CardBus socket address + 80Dh; ExCA offset 0Dh Read/write 00h
5-13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the end address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O windows 0 and 1 end-address low-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 end-address low-byte CardBus socket address + 80Ah; ExCA offset 0Ah ExCA I/O window 1 end-address low-byte CardBus socket address + 80Eh; ExCA offset 0Eh Read/Write 00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the end address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O windows 0 and 1 end-address high-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 end-address high-byte CardBus socket address + 80Bh; ExCA offset 0Bh ExCA I/O window 1 end-address high-byte CardBus socket address + 80Fh; ExCA offset 0Fh Read/write 00h
5-14
5.13 ExCA Memory Windows 0-4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the start address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 start-address low-byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 start-address low-byte CardBus socket address + 810h; ExCA offset 10h ExCA memory window 1 start-address low-byte CardBus socket address + 818h; ExCA offset 18h ExCA memory window 2 start-address low-byte CardBus socket address + 820h; ExCA offset 20h ExCA memory window 3 start-address low-byte CardBus socket address + 828h; ExCA offset 28h ExCA memory window 4 start-address low-byte CardBus socket address + 830h; ExCA offset 30h Read/Write 00h
5-15
5.14 ExCA Memory Windows 0-4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23-A20 of the start address. In addition, the memory window data width and wait states are set in this register. See Table 5-11 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 start-address high byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 start-address high-byte CardBus socket address + 811h; ExCA offset 11h ExCA memory window 1 start-address high-byte CardBus socket address + 819h; ExCA offset 19h ExCA memory window 2 start-address high-byte CardBus socket address + 821h; ExCA offset 21h ExCA memory window 3 start-address high-byte CardBus socket address + 829h; ExCA offset 29h ExCA memory window 4 start-address high-byte CardBus socket address + 831h; ExCA offset 31h Read/Write 00h
Table 5-11. ExCA Memory Windows 0-4 Start-Address High-Byte Registers
BIT 7 SIGNAL DATASIZE TYPE R/W FUNCTION Data size. Bit 7 controls the memory window data width. This bit is encoded as: 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. Scratch pad bits. Bits 5 and 4 have no effect on memory window operation. Start-address high nibble. Bits 3-0 represent the upper address bits A23-A20 of the memory window start address.
6
ZEROWAIT
R/W
5-4 3-0
SCRATCH STAHN
R/W R/W
5-16
5.15 ExCA Memory Windows 0-4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the end address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 end-address low-byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 end-address low-byte CardBus socket address + 812h; ExCA offset 12h ExCA memory window 1 end-address low-byte CardBus socket address + 81Ah; ExCA offset 1Ah ExCA memory window 2 end-address low-byte CardBus socket address + 822h; ExCA offset 22h ExCA memory window 3 end-address low-byte CardBus socket address + 82Ah; ExCA offset 2Ah ExCA memory window 4 end-address low-byte CardBus socket address + 832h; ExCA offset 32h Read/Write 00h
5-17
5.16 ExCA Memory Windows 0-4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The lower 4 bits of these registers correspond to bits A23-A20 of the end address. In addition, the memory window wait states are set in this register. See Table 5-12 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R 0 4 R 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 end-address high-byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 end-address high-byte CardBus socket address + 813h; ExCA offset 13h ExCA memory window 1 end-address high-byte CardBus socket address + 81Bh; ExCA offset 1Bh ExCA memory window 2 end-address high-byte CardBus socket address + 823h; ExCA offset 23h ExCA memory window 3 end-address high-byte CardBus socket address + 82Bh; ExCA offset 2Bh ExCA memory window 4 end-address high-byte CardBus socket address + 833h; ExCA offset 33h Read-only, Read/Write 00h
Table 5-12. ExCA Memory Windows 0-4 End-Address High-Byte Registers
BIT 7-6 5-4 3-0 SIGNAL MEMWS RSVD ENDHN TYPE R/W R R/W FUNCTION Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. Reserved. Bits 5 and 4 return 0s when read. End-address high nibble. Bits 3-0 represent the upper address bits A23-A20 of the memory window end address.
5-18
5.17 ExCA Memory Windows 0-4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The 8 bits of these registers correspond to bits A19-A12 of the offset address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 offset-address low-byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 offset-address low-byte CardBus socket address + 814h; ExCA offset 14h ExCA memory window 1 offset-address low-byte CardBus socket address + 81Ch; ExCA offset 1Ch ExCA memory window 2 offset-address low-byte CardBus socket address + 824h; ExCA offset 24h ExCA memory window 3 offset-address low-byte CardBus socket address + 82Ch; ExCA offset 2Ch ExCA memory window 4 offset-address low-byte CardBus socket address + 834h; ExCA offset 34h Read/Write 00h
5-19
5.18 ExCA Memory Windows 0-4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. The lower 6 bits of these registers correspond to bits A25-A20 of the offset address. In addition, the write protection and common/attribute memory configurations are set in this register. See Table 5-13 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 offset-address high-byte
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 offset-address high-byte CardBus socket address + 815h; ExCA offset 15h ExCA memory window 1 offset-address high-byte CardBus socket address + 81Dh; ExCA offset 1Dh ExCA memory window 2 offset-address high-byte CardBus socket address + 825h; ExCA offset 25h ExCA memory window 3 offset-address high-byte CardBus socket address + 82Dh; ExCA offset 2Dh ExCA memory window 4 offset-address high-byte CardBus socket address + 835h; ExCA offset 35h Read/Write 00h
Table 5-13. ExCA Memory Windows 0-4 Offset-Address High-Byte Registers
BIT SIGNAL TYPE FUNCTION Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is encoded as: 0 = Write operations are allowed (default). 1 = Write operations are not allowed. Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded as: 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. Offset-address high byte. Bits 5-0 represent the upper address bits A25-A20 of the memory window offset address.
7
WINWP
R/W
6
REG
R/W
5-0
OFFHB
R/W
5-20
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5-14 for a complete description of the register contents.
Bit Name Type Default R X R X R/W 0 7 6 5 4 R/W 0 3 R 0 2 R 0 1 R/W 0 0 R 0 ExCA I/O card detect and general control
Register: Offset: Type: Default:
ExCA card detect and general control CardBus socket address + 816h; ExCA offset 16h Read-only, Read/Write XX00 0000b Table 5-14. ExCA Card Detect and General Control Register
BIT
SIGNAL
TYPE
FUNCTION VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have a default value. 0 = VS2 low 1 = VS2 high VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have a default value. 0 = VS1 low 1 = VS1 high Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration register is set (ExCA offset 05h, see Section 5.6), then writing a 1 to bit 5 causes a card-detect card-status-change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration register is cleared to 0 (see Section 5.6), then writing a 1 to bit 5 has no effect. A read operation of this bit always returns 0. Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1 and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in the ExCA card status-change register is cleared (ExCA offset 04h, see Section 5.5). If this bit is a 0, then the card detect resume functionality is disabled. 0 = Card detect resume disabled (default) 1 = Card detect resume enabled Reserved. Bits 3 and 2 return 0s when read. Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card removal event. This bit is encoded as: 0 = No change to ExCA registers on card removal (default) 1 = Reset ExCA registers on card removal Reserved. Bit 0 returns 0 when read.
7
VS2STAT
R
6
VS1STAT
R
5
SWCSC
R/W
4
CDRESUME
R/W
3-2
RSVD
R
1
REGCONFIG
R/W
0
RSVD
R
5-21
5.20 ExCA Global Control Register
The ExCA global control register controls the PC Card socket. The host interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5-15 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA global control
Register: Offset: Type: Default:
ExCA global control CardBus socket address + 81Eh; ExCA offset 1Eh Read-only, Read/Write 00h Table 5-15. ExCA Global Control Register
BIT 7-5 4
SIGNAL RSVD No function
TYPE R R/W Reserved. Bits 7-5 return 0s when read. This bit has no assigned function.
FUNCTION
3
INTMODE
R/W
Level/edge interrupt mode select. Bit 3 selects the signaling mode for the PCI1410 host interrupt. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA card status change register (ExCA offset 04h, see Section 5.5). This bit is encoded as: 0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit writeback of 1. Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1410 host interrupt for card status changes. This bit is encoded as: 0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode. Power-down mode select. When bit 0 is set to 1, the PCI1410 is in power-down mode. In power-down mode, the PCI1410 card outputs are high impedance until an active cycle is executed on the card interface. Following an active cycle, the outputs are again high impedance. The PCI1410 still receives DMA requests, functional interrupts, and/or card status change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded as: 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled.
2
IFCMODE
R/W
1
CSCMODE
R/W
0
PWRDWN
R/W
5-22
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R 0 ExCA I/O windows 0 and 1 offset-address low-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 offset-address low-byte CardBus socket address + 836h; ExCA offset 36h ExCA I/O window 1 offset-address low-byte CardBus socket address + 838h; ExCA offset 38h Read-only, Read/Write 00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of these registers correspond to the upper 8 bits of the offset address.
Bit Name Type Default R/W 0 R/W 0 7 6 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA I/O windows 0 and 1 offset-address high-byte
Register: Offset: Register: Offset: Type: Default:
ExCA I/O window 0 offset-address high-byte CardBus socket address + 837h; ExCA offset 37h ExCA I/O window 1 offset-address high-byte CardBus socket address + 839h; ExCA offset 39h Read/Write 00h
5-23
5.23 ExCA Memory Windows 0-4 Page Register
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256 16-Mbyte regions in the 4G-byte PCI address space. These registers are only accessible when the ExCA registers are memory mapped, that is, these registers cannot be accessed using the index/data I/O scheme.
Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 ExCA memory windows 0-4 page
Register: Offset: Register: Offset: Register: Offset: Register: Offset: Register: Offset: Type: Default:
ExCA memory window 0 page CardBus socket address + 840h ExCA memory window 1 page CardBus socket address + 841h ExCA memory window 2 page CardBus socket address + 842h ExCA memory window 3 page CardBus socket address + 843h ExCA memory window 4 page CardBus socket address + 844h Read/Write 00h
5-24
6 CardBus Socket Registers
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and control socket-specific functions. The PCI1410 provides the CardBus socket/ExCA base address register (offset 10h, see Section 4.12) to locate these CardBus socket registers in PCI memory address space (see Figure 6-1). Table 6-1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address. The PCI1410 implements an additional register at offset 20h that provides power management control for the socket.
Host Memory Space
PCI1410 Configuration Registers
Offset
Offset 00h
CardBus Socket/ExCA Base Address
10h
CardBus Socket Registers 20h 800h
16-Bit Legacy-Mode Base Address
44h
ExCA Registers 844h
Figure 6-1. Accessing CardBus Socket Registers Through PCI Memory Table 6-1. CardBus Socket Registers
REGISTER NAME Socket event Socket mask Socket present state Socket force event Socket control Reserved Reserved Reserved Socket power management OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h
6-1
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the change is, only that one has occurred. Software must read the socket present state register (CardBus offset 08h, see Section 6.3) for current status. Bits 31-4 of this register are reserved and return 0 when read. The following discussion describes bits 3-0. Each bit can be cleared by writing a 1 to that bit. The bits can be set to a 1 by software by writing a 1 to the corresponding bit in the socket force event register (see Section 6.4). All bits are cleared by PCI reset. They can be immediately set again if, when coming out of PC Card reset, the bridge finds the status unchanged (that is, CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is not cleared when interrupts are enabled, then an interrupt is generated (but not masked) based on any bit that is set. See Table 6-2 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R/C 0 18 R 0 2 R/C 0 17 R 0 1 R/C 0 16 R 0 0 R/C 0 Socket event
Socket event
Register: Offset: Type: Default:
Socket event CardBus socket address + 00h Read-only, Read/Write to Clear 0000 0000h Table 6-2. Socket Event Register
BIT 31-4 3 2 1
SIGNAL RSVD PWREVENT CD2EVENT CD1EVENT
TYPE R R/C R/C R/C Reserved. Bits 31-4 return 0s when read.
FUNCTION Power cycle. Bit 3 is set when the PCI1410 detects that bit 3 (PWRCYCLE) in the socket present state register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1. CCD2. Bit 2 is set when the PCI1410 detects that bit 2 (CDETECT2) in the socket present state register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1. CCD1. Bit 3 is set when the PCI1410 detects that bit 1 (CDETECT1) in the socket present state register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1. CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h, see Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For 16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1.
0
CSTSEVENT
R/C
6-2
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt. The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register (CardBus offset 00h, see Section 6.1). See Table 6-3 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R/W 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Socket mask
Socket mask
Register: Type: Offset: Default:
Socket mask Read-only, Read/Write CardBus socket address + 04h 0000 0000h Table 6-3. Socket Mask Register
BIT 31-4
SIGNAL RSVD
TYPE R Reserved. Bits 31-4 return 0s when read.
FUNCTION Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present state register (CardBus offset 08h, see Section 6.3) from causing a status change interrupt. 0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present state register (CardBus offset 08h, see Section 6.3) from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 01 = Reserved (undefined) 10 = Reserved (undefined) 11 = Insertion/removal causes CSC interrupt. CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h, see Section 6.3) from causing a CSC interrupt. 0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt.
3
PWRMASK
R/W
2-1
CDMASK
R/W
0
CSTSMASK
R/W
6-3
6.3 Socket Present State Register
The socket present state register reports information about the socket interface. Write transactions to the socket force event register (CardBus offset 0Ch, see Section 6.4) are reflected here, as well as general socket interface status. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI1410 uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. See Table 6-4 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 1 13 R 1 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R X 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R X 17 R 0 1 R X 16 R 0 0 R X Socket present state
Socket present state
Register: Offset: Type: Default:
BIT 31 SIGNAL YVSOCKET
Socket present state CardBus socket address + 08h Read-only 3000 00XXh Table 6-4. Socket Present State Register
TYPE R FUNCTION YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1410 does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0. XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1410 does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0. 3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1410 does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event register (CardBus offset 0Ch, see Section 6.4). 5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1410 does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event register (CardBus offset 0Ch, see Section 6.4). Reserved. Bits 27-14 return 0s when read. YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V. Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = Normal operation (default) 1 = Invalid VCC request by host software Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1410. 0 = Normal operation (default) 1 = Potential data loss due to card removal Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not updated until a valid PC Card is inserted into the socket. 0 = Normal operation (default) 1 = Unrecognizable PC Card detected
30
XVSOCKET
R
29
3VSOCKET
R
28 27-14 13 12 11 10
5VSOCKET RSVD YVCARD XVCARD 3VCARD 5VCARD
R R R R R R
9
BADVCCREQ
R
8
DATALOST
R
7
NOTACARD
R
6-4
Table 6-4. Socket Present State Register (Continued)
BIT 6 SIGNAL IREQCINT TYPE R FUNCTION READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface. 0 = READY(IREQ)//CINT low 1 = READY(IREQ)//CINT high CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). 16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated until another card interrogation sequence occurs (card insertion). Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as: 0 = Socket powered down (default) 1 = Socket powered up CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD2 low (PC Card may be present) 1 = CCD2 high (PC Card not present) CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during card interrogation are not reflected here. 0 = CCD1 low (PC Card may be present) 1 = CCD1 high (PC Card not present) CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface. 0 = CSTSCHG low 1 = CSTSCHG high
5 4
CBCARD 16BITCARD
R R
3
PWRCYCLE
R
2
CDETECT2
R
1
CDETECT1
R
0
CARDSTS
R
6-5
6.4 Socket Force Event Register
The socket force event register is used to force changes to the socket event register (see Section 6.1) and the socket present state register (see Section 6.3). Bit 14 (CVSTEST) in this register must be written when forcing changes that require card interrogation. See Table 6-5 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 W 0 W 0 W 0 W 0 W 0 W 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 W 0 23 R 0 7 W 0 22 R 0 6 R 0 21 R 0 5 W 0 20 R 0 4 W 0 19 R 0 3 W 0 18 R 0 2 W 0 17 R 0 1 W 0 16 R 0 0 W 0 Socket force event
Socket force event
Register: Type: Offset: Default:
Socket force event Read-only, Write-only CardBus socket address + 0Ch 0000 0000h
6-6
Table 6-5. Socket Force Event Register
BIT 31-15 14 SIGNAL RSVD CVSTEST TYPE R W Reserved. Bits 31-15 return 0s when read. Card VS test. When bit 14 is set, the PCI1410 re-interrogates the PC Card, updates the socket present state register (CardBus offset 08h, see Section 6.3), and enables the socket control register (CardBus offset 10h, see Section 6.5). Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register (CardBus offset 10h, see Section 6.5). Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register (CardBus offset 10h, see Section 6.5). Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register (CardBus offset 10h, see Section 6.5). Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register (CardBus offset 10h, see Section 6.5). Force bad VCC request. Changes to bit 9 (BADVCCREQ) in the socket present state register (CardBus offset 08h, see Section 6.3) can be made by writing to bit 9. Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). Force not a card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). Reserved. Bit 6 returns 0 when read. Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present state register to be written (CardBus offset 08h, see Section 6.3). Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register to be written (CardBus offset 00h, see Section 6.1), and bit 3 (PWRCYCLE) in the socket present state register is unaffected (CardBus offset 08h, see Section 6.3). Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register to be written (CardBus offset 00h, see Section 6.1), and bit 2 (CDETECT2) in the socket present state register is unaffected (CardBus offset 08h, see Section 6.3). Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register to be written (CardBus offset 00h, see Section 6.1), and bit 1 (CDETECT1) in the socket present state register is unaffected (CardBus offset 08h, see Section 6.3). Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register to be written (CardBus offset 00h, see Section 6.1), and bit 0 (CARDSTS) in the socket present state register is unaffected (CardBus offset 08h, see Section 6.3). FUNCTION
13
FYVCARD
W
12
FXVCARD
W
11
F3VCARD
W
10
F5VCARD
W
9 8 7 6 5 4
FBADVCCREQ FDATALOST FNOTACARD RSVD FCBCARD F16BITCARD
W W W R W W
3
FPWRCYCLE
W
2
FCDETECT2
W
1
FCDETECT1
W
0
FCARDSTS
W
6-7
6.5 Socket Control Register
The socket control register provides control of the voltages applied to the socket and instructions for CB CLKRUN protocol. The PCI1410 ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6-6 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 R 0 9 31 30 29 28 27 26 25 24 R 0 8 R 0 23 R 0 7 R/W 0 22 R 0 6 R/W 0 21 R 0 5 R/W 0 20 R 0 4 R/W 0 19 R 0 3 R 0 18 R 0 2 R/W 0 17 R 0 1 R/W 0 16 R 0 0 R/W 0 Socket control
Socket control
Register: Offset: Type: Default:
BIT 31-8 SIGNAL RSVD
Socket control CardBus socket address + 10h Read-only, Read/Write 0000 0000h Table 6-6. Socket Control Register
TYPE R Reserved. Bits 31-8 return 0s when read. CB CLKRUN protocol instructions. 0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. VCC control. Bits 6-4 request card VCC changes. 000 = Request power off (default) 100 = Request VCC = X.X V 001 = Reserved 101 = Request VCC = Y.Y V 010 = Request VCC = 5 V 110 = Reserved 011 = Request VCC = 3.3 V 111 = Reserved Reserved. Bit 3 returns 0 when read. VPP control. Bits 2-0 request card VPP changes. 000 = Request power off (default) 100 = Request VPP = X.X V 001 = Request VPP = 12 V 101 = Request VPP = Y.Y V 010 = Request VPP = 5 V 110 = Reserved 011 = Request VPP = 3.3 V 111 = Reserved FUNCTION
7
STOPCLK
R/W
6-4
VCCCTRL
R/W
3
RSVD
R
2-0
VPPCTRL
R/W
6-8
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. See Table 6-7 for a complete description of the register contents.
Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R/W 0 0 R/W 0 Socket power management
Socket power management
Register: Offset: Type: Default:
BIT 31-26 SIGNAL RSVD
Socket power management CardBus socket address + 20h Read-only, Read/Write 0000 0000h Table 6-7. Socket Power Management Register
TYPE R Reserved. Bits 31-26 return 0s when read. Socket access status. This bit provides information on when a socket access has occurred. This bit is cleared by a read access. 0 = A PC card access has not occurred (default). 1 = A PC card access has occurred. Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. Reserved. Bits 23-17 return 0s when read. CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. Reserved. Bits 15-1 return 0s when read. CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock during idle states. Bit 16 (CLKCTRLEN) enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16. FUNCTION
25
SKTACCES
R
24 23-17 16 15-1
SKTMODE RSVD CLKCTRLEN RSVD
R R R/W R
0
CLKCTRL
R/W
6-9
6-10
7 Distributed DMA (DDMA) Registers
The DMA base address, programmable in PCI configuration space as bits 15-4 of socket DMA register 1 (offset 98h, see Section 4.36), points to a 16-byte region in PCI I/O space where the DDMA registers reside. The names and locations of these registers are summarized in Table 7-1. These PCI1410 register definitions are identical in function to, but different in location from, those of the 8237 DMA controller. The similarity between the register models retains some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when it forwards legacy DMA writes to DMA channels. While the DMA register definitions are identical to those in the 8237 of the same name, some register bits defined in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI1410 implements these obsolete register bits as read-only nonfunctional bits. The reserved registers shown in Table 7-1 are implemented as read-only and return 0s when read. Write transactions to reserved registers have no effect. Table 7-1. Distributed DMA Registers
REGISTER NAME Current address Reserved Reser ed Reserved N/A Mode Multichannel Mask Reserved Reserved Page Reserved N/A Request N/A Master clear Reserved 0Ch Base address Current count Base count Status Command 08h 04h 00h DDMA BASE ADDRESS OFFSET
7.1 DDMA Current Address/Base-Address Register
The DDMA current address/base address register sets the starting (base) memory address of a DDMA transfer. Read transactions from this register indicate the current memory address of a direct memory transfer. For the 8-bit DDMA transfer mode, the current address register contents are presented on AD15-AD0 of the PCI bus during the address phase. Bits 7-0 of the DDMA page register (see Section 7.2) are presented on AD23-AD16 of the PCI bus during the address phase. For the 16-bit DDMA transfer mode, the current address register contents are presented on AD16-AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7-1 of the DDMA page register (see Section 7.2) are presented on AD23-AD17 of the PCI bus during the address phase, and bit 0 is ignored.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 15 14 13 12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 DDMA current address/base-address
DDMA current address/base-address
Register: Offset: Type: Default:
DDMA current address/base-address DDMA base address + 00h Read/Write 0000h
7-1
7.2 DDMA Page Register
The DDMA page register sets the upper byte of the address of a DDMA transfer. Details of the address represented by this register are explained in Section 7.1, DDMA Current Address/Base Address Register.
Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 DDMA page R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0
Register: Offset: Type: Default:
DDMA page DDMA base address + 02h Read/Write 00h
7.3 DDMA Current Count/Base Count Register
The DDMA current count/base count register sets the total transfer count, in bytes, of a direct memory transfer. Read transactions to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer mode.
Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 15 14 13 12 R/W 0 4 R/W 0 11 R/W 0 3 R/W 0 10 R/W 0 2 R/W 0 9 R/W 0 1 R/W 0 8 R/W 0 0 R/W 0 DDMA current count/base count
DDMA current count/base count
Register: Offset: Type: Default:
DDMA current count/base count DDMA base address + 04h Read/Write 0000h
7-2
7.4 DDMA Command Register
The DDMA command register enables and disables the DDMA controller. Bit 2 (DMAEN) defaults to 0 enabling the DDMA controller. All other bits are reserved. See Table 7-2 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R/W 0 1 R 0 0 R 0 DDMA command
Register: Offset: Type: Default:
DDMA command DDMA base address + 08h Read-only, Read/Write 00h Table 7-2. DDMA Command Register
BIT 7-3
SIGNAL RSVD
TYPE R Reserved. Bits 7-3 return 0s when read.
FUNCTION DDMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1410 and defaults to the enabled state. 0 = DDMA controller enabled (default) 1 = DDMA controller disabled Reserved. Bits 1 and 0 return 0s when read.
2
DMAEN
R/W
1-0
RSVD
R
7.5 DDMA Status Register
The DDMA status register indicates the terminal count and DMA request (DREQ) status. See Table 7-3 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 DDMA status R 0 R 0 R 0 R 0 3 2 1 0
Register: Offset: Type: Default:
DDMA status DDMA base address + 08h Read-only 00h Table 7-3. DDMA Status Register
BIT
SIGNAL
TYPE
FUNCTION Channel request. In the 8237, bits 7-4 indicate the status of DREQ of each DMA channel. In the PCI1410, these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set when the PC Card asserts DREQ and are reset when DREQ is deasserted. The status of bit 0 (MASKBIT) in the DDMA multichannel/mask register (see Section 7.9) has no effect on these bits. Channel terminal count. The 8237 uses bits 3-0 to indicate the TC status of each of its four DMA channels. In the PCI1410, these bits report information about a single DMA channel; therefore, all four of these register bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset.
7-4
DREQSTAT
R
3-0
TC
R
7-3
7.6 DDMA Request Register
The DDMA request register requests a DDMA transfer through software. Any write to this register enables software requests, and this register is to be used in block mode only.
Bit Name Type Default W 0 W 0 W 0 0 7 6 5 4 DDMA request W W 0 W 0 W 0 W 0 3 2 1 0
Register: Offset: Type: Default:
DDMA request DDMA base address + 09h Write-only 00h
7.7 DDMA Mode Register
The DDMA mode register sets the DDMA transfer mode. See Table 7-4 for a complete description of the register contents.
Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 DDMA mode R/W R/W 0 R/W 0 R 0 R 0 3 2 1 0
Register: Offset: Type: Default:
DDMA mode DDMA base address + 0Bh Read-only, Read/Write 00h Table 7-4. DDMA Mode Register
BIT
SIGNAL
TYPE
FUNCTION Mode select. The PCI1410 uses bits 7 and 6 to determine the transfer mode. 00 = Demand mode select (default) 01 = Single mode select 10 = Block mode select 11 = Reserved Address increment/decrement. The PCI1410 uses bit 5 to select the memory address in the DDMA current address/base address register to increment or decrement after each data transfer. This is in accordance with the 8237 use of this register bit and is encoded as follows: 0 = Addresses increment (default). 1 = Addresses decrement. Auto initialization 0 = Auto initialization disabled (default) 1 = Auto initialization enabled Transfer type. Bits 3 and 2 select the type of direct memory transfer to be performed. A memory write transfer moves data from the PCI1410 PC Card interface to memory and a memory read transfer moves data from memory to the PCI1410 PC Card interface. The field is encoded as: 00 = No transfer selected (default) 01 = Write transfer 10 = Read transfer 11 = Reserved Reserved. Bits 1 and 0 return 0s when read.
7-6
DMAMODE
R/W
5
INCDEC
R/W
4
AUTOINIT
R/W
3-2
XFERTYPE
R/W
1-0
RSVD
R
7-4
7.8 DDMA Master Clear Register
The DDMA master clear register resets the DDMA controller and all DDMA registers.
Bit Name Type Default W 0 W 0 W 0 7 6 5 4 W 0 3 W 0 2 W 0 1 W 0 0 W 0 DDMA master clear
Register: Offset: Type: Default:
DDMA master clear DDMA base address + 0Dh Write-only 00h
7.9 DDMA Multichannel/Mask Register
The PCI1410 uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI1410 sets the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket's DMA controller or enabling the mask bit. See Table 7-5 for a complete description of the register contents.
Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R/W 0 DDMA multichannel/mask
Register: Offset: Type: Default:
BIT 7-1 SIGNAL RSVD
DDMA multichannel/mask DDMA base address + 0Fh Read-only 00h Table 7-5. DDMA Multichannel/Mask Register
TYPE R Reserved. Bits 7-1 return 0s when read. Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA requests from the card. When cleared (or reset), incoming DREQ assertions are serviced normally. 0 = DDMA service provided on card DREQ 1 = Socket DREQ signal ignored (default) FUNCTION
0
MASKBIT
R/W
7-5
7-6
8 Electrical Characteristics
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Clamping voltage range, VCCP, VCCCB, VCCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCCP + 0.5 V Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCCB + 0.5 V Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCCI + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to VCC + 0.5 V Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition.
8-1
8.2 Recommended Operating Conditions (see Note 3)
OPERATION VCC VCCP VCCCB VCCI Core voltage PCI I/O clamp voltage l lt PC C d I/O clamp voltage Card l lt Miscellaneous I/O clamp voltage Mi ll l lt Commercial Commercial Commercial Commercial PCI PC Card Miscellaneous Fail safe CD pinsk 3.3 V PCI PC Card Miscellaneous Fail safe CD pinsk PCI VI Input oltage Inp t voltage PC Card Miscellaneous Fail safe PCI VO PC Card Output oltage O tp t voltage Miscellaneous Fail safe PCI and PC Card Miscellaneous and fail safe 5V 3.3 V VIL Low level input Low-level in ut voltage 5V 3.3 V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V VIH High-level in ut voltage High level input 5V MIN 3 3 4.75 3 4.75 3 4.75 0.5 VCCP 2 0.475 VCCCB 2.4 2 2 2.4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 NOM 3.3 3.3 5 3.3 5 3.3 5 MAX 3.6 3.6 5.25 3.6 5.25 3.6 5.25 VCCP VCCP VCCCB VCCCB VCCI VCC VCC 0.3 VCCP 0.8 0.325 VCCCB 0.8 0.8 0.8 0.75 VCCP VCCCB VCCI VCC VCC VCC VCC VCC 4 6 ns V V V V V UNIT V
V
V
tt
Input transition time (tr and tf)
TA Operating ambient temperature range 0 25 70 C TJ# Virtual junction temperature 0 25 115 C Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous terminals are 70, 62, 59, 60, 61, 64, 65, 67, 68, and 69 for the PGE packaged device; L11, M9, L8, K8, N9, K9, N10, L10, N11, and M11 for the GGU packaged device; and W12, U10, P9, W10, V10, P10, W11, U11, P11, and R11 for the GHK packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals (MFUNC0-MFUNC6), and power switch control pins). Fail-safe terminals are 75, 117, 131, and 137 for the PGE packaged device; L12, D9, C6, and A4 for the GGU packaged device; and L19, E13, F11, and A9 for the GHK packaged device (card detect and voltage sense pins). Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. kCD terminals are 75 and 137 for the PGE packaged device; L12 and A4 for the GGU packaged device; and L19 and A9 for the GHK packaged device. NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
8-2
8.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TERMINALS PCI and Misc1 VOH Hi h l l t t lt ( Nt High-level output voltage (see Note 4) PC Card Misc2 Misc3# PCI and Misc1 VOL Low-level Low level output voltage PC Card Misc2 Misc3# IOZL IOZH 3-state out ut, high-im edance state output, high-impedance output current 3-state out ut, high-im edance state output, high-impedance output current L l li t t Low-level input current Out ut Output terminals Out ut Output terminals Input terminals IIL I/O terminals In ut Input terminals I/O terminals IIH High-level in ut current input Fail-safe terminals VCCD terminals|| 3.6 V 5.25 V 3.6 V 5.25 V 3.6 V 3.6 V 3.6 V 5.25 V 3.6 V 5.25 V 3.3 V 5V 3.3 V 5V OPERATION 3.3 V 5V 3.3 V 5V TEST CONDITIONS IOH = -0.5 mA IOH = -2 mA IOH = -0.15 mA IOH = -0.15 mA IOH = -12 mA IOH = -4 mA IOL = 1.5 mA IOL = 6 mA IOL = 0.7 mA IOL = 0.7 mA IOL = 12 mA IOL = 4 mA VI = VCC VI = VCC VI = VCC VI = VCC VI = GND VI = GND VI = VCC VI = VCC VI = VCC VI = VCC VI = VCC VI = VCC MIN 0.9VCC 2.4 0.9VCC 2.4 2.1 2.1 0.1VCC 0.55 0.1VCC 0.55 0.5 0.5 -1 -1 10 25 -1 -10 10 20 10 25 10 300 A A A A A A A V V MAX UNIT
For PCI terminals, VI = VCCP. For PC Card terminals, VI = VCCCB. For miscellaneous terminals, VI = VCCI For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. Misc1 includes MFUNC6(69), MFUNC5(68), MFUNC4(67), MFUNC3(65), and MFUNC2(64)for the PGE packaged device; M11, N11, L10, N10, and K9 for the GGU packaged device; and R11, P11, U11, W11, and P10 for the GHK packaged device. Misc2 includes MFUNC1(61), MFUNC0(60), and SERR(35) for the PGE packaged device; N9, K8, and M1 for the GGU packaged device; and V10, W10, and R3 for the GHK packaged device.. # Misc3 includes SPKROUT(62) and RI_OUT(59) for the PGE packaged device; M9 and L8 for the GGU packaged device; and U10 and P9 for the GHK packaged device. || VCCD pins include VCCD0(73) and VCCD1(74).
8-3
8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature
PARAMETER tc twH twL v/t tw tsu Cycle time, PCLK Pulse duration (width), PCLK high Pulse duration (width), PCLK low Slew rate, PCLK Pulse duration (width), RSTIN Setup time, PCLK active at end of RSTIN ALTERNATE SYMBOL tcyc thigh tlow tr, tf trst trst-clk TEST CONDITIONS MIN 30 11 11 1 1 100 4 MAX UNIT ns ns ns V/ns ms ms
8.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature
This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. The following are used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time.
PARAMETER PCLK-to-shared signal valid delay time tpd Propagation delay time See Note 4 time, PCLK-to-shared signal invalid delay time Enable time, high impedance-to-active delay time from PCLK Disable time, active-to-high impedance delay time from PCLK ALTERNATE SYMBOL tval tinv ton TEST CONDITIONS MIN 2 2 MAX 11 ns UNIT
CL = 50 pF, F, See Note 4
Delay time, ten td Delay time, tdis
2
ns
toff
28
ns
tsu Setup time before PCLK valid tsu 7 th Hold time after PCLK high th 0 NOTE 4: PCI shared signals are AD31-AD0, C/BE3-C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
ns ns
8.6 PC Card Cycle Timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. The PC Card address setup and hold times are a function of the wait-state bits. Table 8-1 shows address setup time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8-2 and Table 8-3 show command active time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8-4 shows address hold time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8-1. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITS I/O Memory Memory WS1 WS1 0 1 TS1 - 0 = 01 (PCLK/ns) 3/90 2/60 4/120
8-4
Table 8-2. PC Card Command Active Cycle Time, tc(A), 8-Bit PCI Cycles
WAIT-STATE BITS WS 0 I/O 1 0 00 01 Memory 10 11 00 ZWS 0 X 1 0 X X X 1 TS1 - 0 = 01 (PCLK/ns) 19/570 23/690 7/210 19/570 23/690 23/690 23/690 7/210
Table 8-3. PC Card Command Active Cycle Time, tc(A), 16-Bit PCI Cycles
WAIT-STATE BITS WS 0 I/O 1 0 00 01 Memory y 10 11 00 ZWS 0 X 1 0 X X X 1 TS1 - 0 = 01 (PCLK/ns) 7/210 11/330 N/A 9/270 13/390 17/510 23/630 5/150
Table 8-4. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles
WAIT-STATE BITS I/O Memory Memory WS1 WS1 0 1 TS1 - 0 = 01 (PCLK/ns) 2/60 2/60 3/90
8-5
8-6
9 Mechanical Information
The PCI1410 is packaged in either a 144-ball GGU MicroStar BGA or a 144-pin PGE package. It is also packaged in a 209-ball GHK MicroStar BGA that is pin compatible with the TI PCI4410. The PCI4410 is a single-socket CardBus bridge with an integrated OHCI link. The following shows the mechanical dimensions for the GGU, GHK, and PDV packages.
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
9,60 TYP 12,10 SQ 11,90 0,80
N M L K J H G F E D C B A
0,80
1 2 3 4 5 6 7 8 9 10 11 12 13 0,95 0,85
1,40 MAX
Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,10
0,45 0,35
4073221/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration
9-1
GHK (S-PBGA-N209)
16,10 SQ 15,90
PLASTIC BALL GRID ARRAY
14,40 TYP 0,80 W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0,80
0,95 0,85
1,40 MAX
Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,10
0,45 0,35
4145273-2/B 12/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration.
9-2
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72 0,27 0,17 0,08 M
0,50
144
37
0,13 NOM
1 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80
36 Gage Plane
0,05 MIN
0,25 0-7
1,45 1,35
0,75 0,45
Seating Plane 1,60 MAX 0,08
4040147/C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
9-3
9-4

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