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| PACNLT101 Non-Linear High Speed Termination IC Features * 16 channel, dual rail clamping action in a single package * Provides bus termination independent of line impedance or loading conditions * Uses CAMD's patented EZtermTM technology * 24-pin QSOP package saves board space and eases layout in space critical areas. * One IC replaces and outperforms up to 32 discrete components. * Enable pin included Applications * High speed, low voltage buses Product Description CAMD's non-linear termination IC is specifically designed to minimize overshoot/undershoot disturbances caused by impedance mismatch reflections and noise on high-speed transmission lines. Reflections on high-speed data lines lead to voltage overshoot and understoot disturbances, which may result in data loss or improper system operation. Resistive terminations, when used to terminate these highspeed data lines, increase power consumption and degrade output levels, resulting in reduced noise immunity. Clamping-type termination is the best overall solution for applications in which these may be considerations. This highly integrated non-linear termination IC provides very effective termination performance for high-speed data lines under variable loading conditions. The device supports up to 16 terminated lines per package - each of which are clamped to both ground and power supply rail. A typical application may use 4 devices to replace (and outperform) 64 conventional Schottky diode pairs; thus providing significant reductions in component and assembly costs, improvements in manufacturing efficiency and reliability, and savings in allocated board area for space-critical designs. Pin Configuration Top View NLT#1 NLT#2 NLT#3 GND NLT#4 NLT#5 NLT#6 NLT#7 GND NLT#8 NLT#9 NLT#10 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD NLT#16 GND NLT#15 NLT#14 NLT#13 NLT#12 GND NLT#11 Enable VDD PACNLT101 24-Pin QSOP Standard Part Ordering Information Package Pin 24 Style QSOP Ordering Part Number Tape & Reel Part Marking PACNLT101Q PACNLT101Q (c)2000 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices C1601100 215 Topaz Street, Milpitas, California 95035 11/17/2000 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 PACNLT101 Absolute Maximum Ratings Parameter Maximum DC Voltage on any pin Minimum DC Voltage on any pin Continuous current per channel Operating Temperature (Ambient) Storage Temperature (Ambient) Power Dissipation @ T = 25C Rating 3.6 -0.5 72 0 to 70 -65 to 150 0.9 Unit V V mA C C W Operating Characterisitcs - 3.3V: Temperature rated at 0C to 70C, VDD Enable rated 3.3V 0.3V Operating Characteristics -- 3.3V Parameter Signal Voltage VDD current Enable pin (pin 14) current Input Capacitance* ESD protection above VDD @ I = 50mA below GND @ I = 50mA all Channels floating all Channels floating Signal voltage = VDD Signal voltage = VDD/2 MIL-STD-883, method 3015* *These parameters are guaranteed by design and characterization. Conditions TYP 610 510 69 8 3.4 3.0 4 UNIT mV mV mA mA pF pF kV Operating Characterisitcs - 2.0V: Temperature rated at 0C to 70C, VDD Enable rated 2.0V 0.2V Operating Characteristics -- 2.0V Parameter Signal Voltage VDD current Enable pin (pin 14) current Input Capacitance* ESD protection above VDD @ I = 20mA below GND @ I = 20mA all Channels floating all Channels floating Signal voltage = VDD Signal voltage = VDD/2 MIL-STD-883, method 3015* *These parameters are guaranteed by design and characterization. Conditions TYP 390 300 21 3.5 3.5 3.2 4 UNIT mV mV mA mA pF pF kV (c)2000 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/17/2000 PACNLT101 VCC Non-Linear Clamp Termination Driver 74AC244 Transmission Line Receiver 74AC244 GND Figure 1. Example Circuit: Single-Driver/Single Receiver Tek 5.00GS/s 23 Acqs : 3.30V @: 0V C1 Rise 1.14ns C1 Fall 1.10ns C1 Max 4.42V C1 Min -1.36V 1.00V M 10.0ns Ch1 900mV 27 Jun 2000 13:18:51 Figure 2. 74AC244 Termination Only Tek 5.00GS/s 4933 Acqs : 3.30V @: 3.30V C1 Rise 1.04ns C1 Fall 940ps C1 Max 3.80V C1 Min -580V 1.00V M 10.0ns Ch1 840mV 13 Jun 2000 14:55:24 Figure 3. With PACNLT101 Termination (c)2000 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices 215 Topaz Street, Milpitas, California 95035 11/17/2000 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 PACNLT101 50 45 40 35 Current (mA) 30 25 20 15 10 5 0 0 100 200 300 400 500 600 VDD = 3.3V VDD = 2.0V Voltage above VDD (mV) Figure 4. DC I-V Curves for VDD = 2V and VDD = 3.3V Application Information Figure 5 shows one method of configuring the printed circuit board such that all 16 terminated signals are easily accessible. The decoupling capacitor should be a high-frequency type, 0.1F or larger, and placed as close to the IC as possible. This will minimize the positive overshoot voltage and also reduce EMI emissions. It should be noted that for optimum performance the PACNLT101 termination should be located as physically close to the receiving IC input as is possible. 1 2 3 24 23 22 21 20 19 18 17 16 15 14 13 VDD 0.1F GND GND 4 5 16 Terminated Signals GND 6 7 8 9 10 11 12 PACNLT101 GND via Enable Figure 5. Printed Circuit Board with Accessible Configuration for 16 Terminated Signals (c)2000 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/17/2000 PACNLT101 Enable pin The Enable pin has a dual function. If forced to ground or set to high impedance it will greatly reduce the supply current of the PACNLT101. The Enable pin can also be used to vary the supply current and clamping voltage. As the current into the Enable pin is increased the supply current will increase and the clamping voltage will be reduced. The minimum clamping voltage will occur when the Enable pin voltage PACNLT101 R1 Enable Powerdown equals the supply voltage. (The Enable pin voltage cannot exceed the supply voltage.) Users who cannot tolerate the supply current quoted in the Operating Characteristics can connect a resistor in series with the Enable pin to reduce the supply current, at the cost of increasing the clamping voltage. See Figure 6. Controller Figure 6. Resistor In Series with the Enable Pin The controller IC sets the powerdown pin to 0V to depower the PACNLT101, and sets the powerdown pin to VDD to power up the PACNLT101. The system designer 80 70 60 50 can vary the value of R1 to optimize the trade-off between power consumption and clamping voltage. See Figure 7 and Figure 8. IDD (mA) 40 30 20 10 0 0 100 180 Value of External Resistor R1 470 1000 Figure 7. Variation IDD with R1 720 700 680 Clamping Voltage (V) 660 640 620 600 580 560 0 100 180 Value of External Resistor R1 470 1000 Figure 8. Variation of Clamping Voltage with R1 (c)2000 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices 215 Topaz Street, Milpitas, California 95035 11/17/2000 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5 |
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