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INTEGRATED CIRCUITS
P82B96 Dual bi-directional bus buffer
Product specification IC12 Data Handbook 2001 Mar 06
Philips Semiconductors
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
FEATURES
* Dual Interface handles both SCL and SDA signals * Bi-directional data transfer * Splits I2C signal into forward/reverse Tx, Ty, Rx and Ry signals * Low power supply current. * Wide supply voltage range (I2C logic levels at Sx Sy independent
of IC supply voltage).
PIN CONFIGURATIONS 8-pin dual in-line or SO
Sx
1
8
VCC
Rx
2
7
Sy
* Inhibits data transfer (releases bus) if supply fails. * Supports 100 kHz clock speed on short busses.
TYPICAL INTERFACES
levels (e.g., 5V and 3V)
Tx
3
6
Ry
GND
4
5
Ty
SU01011
* Provides interface between I2C busses operating at different logic
differential bus hardware, e.g., via compatible PCA82C250.
* Interfaces with Opto-couplers to provide Opto isolation between
I2C bus nodes.
DESCRIPTION
The P82B96 is a bipolar IC which creates a non-latching, bi-directional, logic interface between the normal I2C bus and a range of other bus configurations. It can interface I2C bus logic signals to similar busses having different voltage and current levels. For example it can interface to the 350 mA SMB bus, to 3.3 V logic devices, and to 15 V levels and/or low impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C protocols or 100 kHz clock speed. The IC adds minimal loading to the I2C node, and loadings of the new bus or remote I2C nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bi-directional signal line with I2C properties.
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ORDERING INFORMATION
TYPE NUMBER NAME
P82B96PN P82B96TD
DIP8 SO8
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package; 8 leads; body width 3.9 mm
2001 Mar 06
2
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SYMBOL Sx Tx Ty Rx PIN 1 2 3 4 5 6 7 8 DESCRIPTION I2C Bus (SDA or SCL) Receive signal Transmit signal Transmit signal Receive signal GND Ry Sy Negative Supply I2C Bus (SDA or SCL) Positive supply VCC PACKAGE DESCRIPTION VERSION SOT97-1 SOT96-1 853-2241 25758
* Provides interface between I2C and SMB (350 mA) bus standard. * Simple conversion of I2C SDA or SCL signals to multi-drop
PINNING
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
BLOCK DIAGRAM
+VCC (2-15 V)
8
Sx (SDA) 1 3
Tx (TxD, SDA)
2
Rx (RxD, SDA)
Sy (SCL)
7
5
Ty (TxD, SCL)
6 P82B96 4
Ry (RxD, SCL)
GND
SU01012
FUNCTIONAL DESCRIPTION
The P82B96 has two identical buffers allowing buffering of both of the I2C (SDA and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the I2C interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I2C bus interface. Thus these paths are: 1. Sense the voltage state of the I2C pin Sx (or Sy) and transmit this state to the pin Tx (Ty resp.), and 2. Sense the state of the pin Rx (Ry) and pull the I2C pin low whenever Rx (Ry) is low. The rest of this discussion will address only the "x" side of the buffer: the "y" side is identical. The I2C pin (Sx) is designed to interface with a normal I2C bus. The logic threshold voltage levels on the I2C bus are independent of the IC supply VCC The maximum I2C bus supply voltage is 15 V and the guaranteed static sink current is 3 mA. The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC and logic HIGH is above 58 % of VCC: with a typical switching threshold of half VCC. Tx is an open collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the I2C pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C bus (Sx) to be pulled to a logic LOW level in accordance with I2C requirements (max. 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch low. The minimum LOW level this chip can achieve on the I2C bus by a LOW at Rx is typically 0.8 V. If the supply voltage Vcc fails then neither the I2C nor the Tx output will be held low. Their open collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on Sx and Rx also present no loading of external signals even when VCC is not present.
2001 Mar 06
3
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At Tamb = 25C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.
2001 Mar 06
CHARACTERISTICS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages with respect to pin GND (pin 4).
MAXIMUM RATINGS
Philips Semiconductors
ITx, ITy
ITx, ITy
ITx, ITy
VTx, VTy
ISx, ISy
ISx, ISy
ISx, ISy
ISx, ISy
VSx, VSy
Bus pull-up (load) voltages and currents
ICC
ICC
ICC
VCC
Power Supply
Tamb
Tstg
Rtot
I
VRx
VTx
Vbus
VCC to GND
SYMBOL
Dual bi-directional bus buffer
SYMBOL
Leakage current on buffered bus VTx, VTy = VCC = 15 V, and VSx, VSy = HIGH
Dynamic output sink capability, buffered bus: VTx, VTy > 1 V VSx, VSy = LOW on I2C bus = 0.4V
Static output loading on buffered bus VTx, VTy = 0.4 V VSx, VSy = LOW on I2C bus = 0.4V
Maximum output voltage level Open collector
Leakage current on I2C bus VSx, VSy = 15 V, and VRx, VRy = HIGH
Leakage current on I2C bus VSx, VSy = 5 V, and VRx, VRy = HIGH
Dynamic output sink capability on I2C bus VSx, VSy > 2 V VRx, VRy = LOW
Static output loading on I2C bus VSx, VSy = 1.2 V
Maximum input/output voltage level Open collector I2C bus and VRx, VRy = HIGH
Additional supply current per Tx or Ty LOW
Supply current at VCC = 15V, busses HIGH
Supply current, busses HIGH
Supply voltage (operating)
Operating ambient temperature range
Storage temperature range
Power dissipation
DC current (any pin)
Voltage range on receive input
Voltage range on buffered output
Voltage range on I2C Bus, SDA or SCL
Supply voltage range VCC
VRx, VRy = LOW
PARAMETER
PARAMETER
4 MIN. 0.2 2.0 60 -- -- -- -- -- -- -- -- -- 7 MIN. -0.3 -0.3 -0.3 -0.3 -40 -55 TYP. 100 1.7 1.1 0.9 18 -- -- -- -- -- -- 1 1 MAX. +125 +85 +18 +18 +18 +18 300 250 MAX. 3.5 2.5 1.8 30 15 15 15 -- -- -- -- 1 3 Product specification
P82B96
UNIT
mW
mA
UNIT
C
C
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA mA mA V V V
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Trise delay VRx to VSx VRy to VSy Tfall delay VRx to VSx VRy to VSy Trise delay VSx to VTx VSy to VTy Tfall delay VSx to VTx VSy to VTy Buffer response time dV/dT VSx, VSy, VTx, VTy Bus Release on VCC Failure VRx, VRy VRx, VRy VRx, VRy dVSx/dT, dVSy/dT VSx, VSy VSx, VSy VSx, VSy Input Thresholds IRx, IRy IRx, IRy ISx, ISy Input Currents
2001 Mar 06 Philips Semiconductors
Dual bi-directional bus buffer
SYMBOL
Buffer time delay on FALLING input between VRx = input switching threshold, and VSx output falling 50%. RSx pull up = 1600 W, no capacitive load, VCC = 5 V
VCC voltage at which all busses are guaranteed to be released
Buffer time delay on RISING input between VRx = input switching threshold, and VSx output reaching 50%. RSx pull up = 1600 W, no capacitive load, VCC = 5 V
Buffer time delay on RISING input between VSx = input switching threshold, and VTx output reaching 50%. RTx pull up = 160 W, no capacitive load, VCC = 5 V
Buffer time delay on FALLING input between VSx = input switching threshold: and VTx output falling 50%. RTx pull up = 160 W, no capacitive load, VCC = 5 V
Temperature coefficient of guaranteed release voltage
Input logic LOW level Fraction of applied VCC
Input threshold Fraction of applied VCC
Input logic HIGH level Fraction of applied VCC
Temperature coefficient of thresholds
Input logic level LOW threshold On normal I2C bus
Output logic level LOW, on normal I2C bus ISx, ISy = 0.2 mA
Output logic level LOW, on normal I2C bus ISx, ISy = 3 mA
Leakage current on buffered bus input VRx, VRy = VCC
Input current from buffered bus, bus LOW VRx, VRy = 0.4 V
Input current from I2C bus, bus LOW VRx, VRy = HIGH
PARAMETER
5 MIN. 0.58 600 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- TYP. 300 300 100 100 650 750 0.5 0.9 -1 -1 -- -- -- -4 -2 1 MAX. 0.42 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 Product specification
P82B96
mV/K
mV/K
UNIT
mV
mV
mA
mA
mA
ns ns ns ns V V
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
TYPICAL APPLICATIONS
+VCC (2-15 V) +5 V R1 I2C SDA Tx (SDA) `SDA' (NEW LEVELS)
Rx (SDA) 1/2 PB2B96
SU01013
Figure 1. Interfacing an
`I2C'
type of bus with different logic levels.
+VCC
+VCC1 R4
R2
R5 R3 I2C SDA +5 V R1 I2C SDA Rx (SDA)
Tx (SDA)
1/2 P82B96
SU01014
Figure 2. Galvanic isolation of
I2C
nodes via opto-couplers
2001 Mar 06
6
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2001 Mar 06
7
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
2001 Mar 06
8
Philips Semiconductors
Product specification
Dual bi-directional bus buffer
P82B96
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 03-01 Document order number: 9397 750 08122
Philips Semiconductors
2001 Mar 06 9

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