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OPA 688
OPA688
OPA
688
Unity Gain Stable, Wideband VOLTAGE LIMITING AMPLIFIER
TM
FEATURES
q q q q q q q HIGH LINEARITY NEAR LIMITING FAST RECOVERY FROM OVERDRIVE: 2.4ns LIMITING VOLTAGE ACCURACY: 15mV -3dB BANDWIDTH (G = +1): 530MHz SLEW RATE: 1000V/s 5V AND 5V SUPPLY OPERATION HIGH GAIN VERSION: OPA689
APPLICATIONS
q q q q q q q q FAST LIMITING ADC INPUT BUFFER CCD PIXEL CLOCK STRIPPING VIDEO SYNC STRIPPING HF MIXER IF LIMITING AMPLIFIER AM SIGNAL GENERATION NON-LINEAR ANALOG SIGNAL PROCESSING COMPARATOR
DESCRIPTION
The OPA688 is a wideband, unity gain stable voltage feedback op amp that offers bipolar output voltage limiting. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits. This new output limiting architecture holds the limiter offset error to 15mV. The op amp operates linearly to within 30mV of the output limit voltages. The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100mV of the desired linear output range. A fast 2.4ns recovery from limiting ensures that overdrive signals will be transparent to the signal channel. Implementing the limiting function at the output, as opposed to the input, gives the specified limiting accuracy for any gain, and allows the OPA688 to be used in all standard op amp applications. Non-linear analog signal processing will benefit from the OPA688's sharp transition from linear operation to output limiting. The quick recovery time supports high speed applications. The OPA688 is available in an industry standard pinout in 8-pin PDIP and SO-8 packages. For higher gain, or transimpedance applications requiring output limiting with fast recovery, consider the OPA689.
LIMITED OUTPUT RESPONSE 2.5 2.0
Input and Output Voltage (V)
DETAIL OF LIMITED OUTPUT VOLTAGE 2.10 2.05 2.00
VH = -VL = 2.0V G = +2
1.5
Output Voltage (V)
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5
VIN
VO
1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 Time (50ns/div)
VO
Time (200ns/div)
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
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1997 Burr-Brown Corporation
PDS-1424C 1
Printed in U.S.A. June, 1998
OPA688
SPECIFICATIONS-- VS = 5V
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted. OPA688U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
PARAMETER AC PERFORMANCE (see Figure 1) Small Signal Bandwidth
CONDITIONS
+25C
+25C
UNITS
Gain-Bandwidth Product (G +5) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response: Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Differential Gain Differential Phase Input Noise: Voltage Noise Density Current Noise Density DC PERFORMANCE (VCM = 0) Open Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift INPUT Common-Mode Rejection Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limit Voltage Minimum Limiter Separation (VH - VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude (5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Offset Op Amp Input Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8)
VO < 0.2Vp-p G = +1, RF = 25 G = +2 G = -1 VO < 0.2Vp-p G = +1, RF = 25, VO < 0.2Vp-p VO < 0.2Vp-p VO = 4Vp-p, VH = -VL = 2.5V 4V Step, VH = -VL = 2.5V 0.2V Step 2V Step f = 5MHz, VO = 2Vp-p NTSC, PAL, RL = 500 NTSC, PAL, RL = 500 f 1MHz f 1MHz VO = 0.5V
530 260 230 290 11 50 145 1000 1.2 7 66 0.02 0.01 6.3 2.0 54 2 -- +6 -- 0.3 -- 57 3.3 0.4 || 1 1 || 1
-- 150 -- 175 -- -- 100 800 2.6 -- 62 -- -- 7.2 2.5 48
-- 140 -- 170 -- -- 95 770 2.7 -- 58 -- -- 7.8 2.9 46 7 14 13 -60 3 10 49 3.2 -- -- 3.9 85 -65 -- -- 6 19 12.8 57 3.0 200 4.3 64 43 40 -- -- 40 -- -- -- -- 3.0 --
-- 135 -- 160
--
-- 90 650 3 -- 53 -- -- 8 3.6 45 9 14 20 -90 4 10 47 3.1 -- -- 3.8 80 -60 -- -- 6 20 11 55 2.9 200 4.3 66 41 45 -- -- 40 -- -- -- -- 3.2 --
MHz MHz MHz MHz dB MHz MHz V/s ns ns dB % nV/Hz pA/Hz dB mV V/C A nA/C A nA/C dB V M || pF M || pF V mA mA V V mA mA dB V mV V A A nA/C M || pF dB mV A MHz V/s mV ns mV
Typ Min Typ Min Typ Typ Min Min Max Typ Min Typ Typ Max Max Min Max Max Max Max Max Max Min Min Typ Typ Min Min Min Typ Typ Max Max Min Min Min Min Max Max Min Max Typ Typ Max Typ Typ Typ Typ Max Typ
C B C B C C B B B C B C C B B A A B A B A B A A C C A A A C C C A A A A B B A A B C C A C C C C B C
6
-- --
12 2
-- 50
Input Referred, VCM = 0.5V
3.2
-- --
VH = -VL = 4.3V RL 500 VO = 0 VO = 0 G = +1, RF = 25, f < 100kHz
4.1 105 -85 0.2 5 -- 15.8 15.8
3.9
90 -70 -- -- 6 17 14 58
+VS = 4.5V to 5.5V 65 Pins 5 and 8 Limiter Pins Open 3.3 200 -- 54 54 -- 2 || 1 -60 15 3 450 100 250 2.4 30
3.0
200 4.3 61 44 -- -- --
VO = 0
f = 5MHz VIN = 2V (VO - VH) or (VO - VL) VIN = 2V, VO < 0.02Vp-p 2x Overdrive VIN = 0 to 2V Step VIN = 2V to 0V Step f = 5MHz, VO = 2Vp-p
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-- -- -- -- 2.8 --
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OPA688
2
SPECIFICATIONS-- VS = 5V
(CONT)
OPA688U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
PARAMETER THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8
CONDITIONS
+25C
+25C
UNITS C C/W C/W
Specification: P, U Junction-to-Ambient
-40 to +85 100 125
-- -- --
-- -- --
-- -- --
Typ Typ Typ
C C C
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25C guaranteed specifications. Junction Temperature = Ambient Temperature + 23C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is positive, and IVL (VL bias current) is negative, under these conditions. See Note 3, Figure 1 and Figure 8 . (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: VIN = +2V, G = +2, VL = -2V, VH = step between 2V and 0V. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, VO = 0VDC 1Vp-p) centered between the limiter levels (VH and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
SPECIFICATIONS -- VS = +5V
G = +2, RL = 500 tied to VCM = 2.5V, RF = 402, VL = VCM -1.2V, VH = VCM +1.2V (Figure 2 for AC performance only), unless otherwise noted. OPA688U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
PARAMETER AC PERFORMANCE (see Figure 2) Small Signal Bandwidth
CONDITIONS
+25C
+25C
UNITS
Gain-Bandwidth Product (G +5) Gain Peaking 0.1dB Gain Flatness Bandwidth Large Signal Bandwidth Step Response: Slew Rate Rise/Fall Time Settling Time: 0.05% Spurious Free Dynamic Range Input Noise: Voltage Noise Density Current Noise Density DC PERFORMANCE Open Loop Voltage Gain (AOL) Input Offset Voltage Average Drift Input Bias Current(3) Average Drift Input Offset Current Average Drift
VO < 0.2Vp-p G = +1, RF = 25 G = +2 G = -1 VO < 0.2Vp-p G = +1, RF = 25, VO < 0.2Vp-p VO < 0.2Vp-p VO = 2Vp-p 2V Step 0.2V Step 1V Step f = 5MHz, VO = 2Vp-p f 1MHz f 1MHz VCM = 2.5V VO = 0.5V
515 240 190 275 10 50 240 1000 2.3 12 64 6.3 2.0 54 2 -- +6 -- 0.3 --
-- 110 -- 130 -- -- 110 800 2.6 -- 60 7.2 2.5 48 --
-- 105 -- 125 -- -- 105 770 2.7 -- 56 7.8 2.9 46 7 14 13 -60 3 10
-- 100 -- 120 -- -- 100 650 3 -- 51 8 3.6 45 9 14 20 -90 4 10
MHz MHz MHz MHz dB MHz MHz V/s ns ns dB nV/Hz pA/Hz dB mV V/C A nA/C A nA/C
Typ Min Typ Min Typ Typ Min Min Max Typ Min Max Max Min Max Max Max Max Max Max
C B C B C C B B B C B B B A A B A B A B
6 12 2
-- --
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3
OPA688
SPECIFICATIONS-- VS = +5V
(CONT)
OPA688U, P TYP GUARANTEED(1) 0C to +70C -40C to +85C MIN/ TEST MAX LEVEL(2)
G = +2, RL = 500 tied to VCM = 2.5V, RF = 402, VL = -1.2V, VH = +1.2V (Figure 2 for AC performance only), unless otherwise noted.
PARAMETER INPUT Common-Mode Rejection Common-Mode Input Range(4) Input Impedance Differential-Mode Common-Mode OUTPUT Output Voltage Range Current Output, Sourcing Sinking Closed-Loop Output Impedance POWER SUPPLY Operating Voltage, Specified Maximum Quiescent Current, Maximum Minimum Power Supply Rejection Ratio +PSR (Input Referred) OUTPUT VOLTAGE LIMITERS Default Limiter Voltage Minimum Limiter Separation (VH - VL) Maximum Limit Voltage Limiter Input Bias Current Magnitude(5) Maximum Minimum Average Drift Limiter Input Impedance Limiter Feedthrough(6) DC Performance in Limit Mode Limiter Voltage Accuracy Op Amp Bias Current Shift(3) AC Performance in Limit Mode Limiter Small Signal Bandwidth Limiter Slew Rate(7) Limited Step Response Overshoot Recovery Time Linearity Guardband(8) THERMAL CHARACTERISTICS Temperature Range Thermal Resistance P 8-Pin DIP U 8-Pin SO-8
CONDITIONS Input Referred, VCM = 0.5V
+25C
+25C
UNITS
55 VCM 0.8 0.4 || 1 1 || 1
48 VCM 0.7 -- -- VCM 1.4 60 -50 -- -- +12 15 11 -- VCM 0.6 200 VCM 1.8 60 0 -- -- --
47 VCM 0.7 -- -- VCM 1.4 55 -45 -- -- +12 15 10 -- VCM 0.6 200 VCM 1.8 70 0 30 -- -- 40 -- -- -- -- -- -- -- -- --
45 VCM 0.6 -- -- VCM 1.3 50 -40 -- -- +12 16 9 -- VCM 0.6 200 VCM 1.8 80 0 50 -- -- 40 -- -- -- -- -- -- -- -- --
dB V M || pF M || pF V mA mA V V mA mA dB V mV V A A nA/C M || pF dB mV A MHz V/s mV ns mV C C/W C/W
Min Min Typ Typ Min Min Min Typ Typ Max Max Min Typ Min Min Max Max Min Max Typ Typ Max Typ Typ Typ Typ Max Max Typ Typ Typ
A A C C A A A C C A A A C A B B A A B C C A C C C C C C C C C
VH = VCM +1.8V, VL = = VCM -1.8V RL 500 VO = 2.5V VO = 2.5V G = +1, RF = 25, f < 100kHz Single Supply Operation
VCM 1.6 70 -60 0.2 +5 -- 13 13
VS = 4.5V to 5.5V 65 Pins 5 and 8 Limiter Pins Open VCM 0.9 200 -- 35 35 -- 2 || 1 -60 15 5 300 20 55 15 30 -40 to +85 100 125
VO = 2.5V
f = 5MHz VIN = VCM 1.2V (VO - VH) or (VO - VL) VIN = VCM 1.2V, VO < 0.02Vp-p 2x Overdrive VIN = VCM to VCM 1.2V Step VIN = VCM 1.2V to VCM Step f = 5MHz, VO = 2Vp-p Specification: P, U Junction-to-Ambient
35
-- -- -- -- -- -- -- -- --
NOTES: (1) Junction Temperature = Ambient Temperature for low temperature limit and 25C guaranteed specifications. Junction Temperature = Ambient Temperature + 23C at high temperature limit guaranteed specifications. (2) TEST LEVELS: (A) 100% tested at 25C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value for information only. (3) Current is considered positive out of node. (4) CMIR tested as < 3dB degradation from minimum CMRR at specified limits. (5) I VH (VH bias current) is negative, and I VL (VL bias current) is positive, under these conditions. See Note 3, Figures 2, and Figure 8. (6) Limiter feedthrough is the ratio of the output magnitude to the sinewave added to V H (or VL) when VIN = 0. (7) VH slew rate conditions are: V IN = VCM +0.4V, G = +2, VL = VCM -1.2V, VH = step between VCM + 1.2V and V CM. VL slew rate conditions are similar. (8) Linearity Guardband is defined for an output sinusoid (f = 5MHz, V O = VCM 1Vp-p) centered between the limiter levels (V H and VL). It is the difference between the limiter level and the peak output voltage where SFDR decreases by 3dB (see Figure 8).
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OPA688
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. 6.5V Internal Power Dissipation .......................... See Thermal Characteristics Common-Mode Input Voltage ............................................................. VS Differential Input Voltage ..................................................................... VS Limiter Voltage Range ........................................................... (VS - 0.7V) Storage Temperature Range: P, U ................................ -40C to +125C Lead Temperature (DIP, soldering, 10s) ..................................... +300C (SO-8, soldering, 3s) ...................................... +260C Junction Temperature .................................................................... +175C
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.
PIN CONFIGURATION
Top View DIP, SO-8
NC Inverting Input Non-Inverting Input -VS
1 2 3 4
8 7 6 5
VH +VS Output VL
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER(1) 006 182 SPECIFIED TEMPERATURE RANGE -40C to +85C -40C to +85C PACKAGE MARKING OPA688P OPA688U ORDERING NUMBER(2) OPA688P OPA688U OPA688U/2K5 TRANSPORT MEDIA Rails Rails Rails
PRODUCT OPA688P OPA688U
PACKAGE 8-Pin Plastic DIP SO-8 Surface Mount
"
"
"
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of OPA688U/2K5" will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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OPA688
TYPICAL PERFORMANCE CURVES --VS = 5V
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted. NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 12 9
Normalized Gain (dB) INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 6 3 Normalized Gain (dB) 0 -3 -6 -9 -12 -15 -18
RG
VO = 0.2Vp-p
G = +1, RC = , RF = 25
VO = 0.2Vp-p
G = -1
6 3 0 -3 -6 -9 -12 -15 -18 1M
VIN RS 150
G = +1, RC = 175, RF = 25 G = +2, RC =
G = -2
VO RC RF
G = -5
G = +5, RC = 100M Frequency (Hz) 1G
-21 -24 1M 10M 100M Frequency (Hz) 1G
10M
SMALL-SIGNAL PULSE RESPONSE 0.25 0.20 0.15 VO = 0.2Vp-p
LARGE-SIGNAL PULSE RESPONSE 2.5 2.0 1.5
Output Voltage (V)
VO = 4Vp-p VH = -VL = 2.5V
Output Voltage (V)
0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -0.25 Time (5ns/div)
0.10 0.05 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (5ns/div)
VH--LIMITED PULSE RESPONSE 2.5 2.0
VL--LIMITED PULSE RESPONSE 2.5 2.0 G = +2 VL = -2V
Input and Output Voltages (V)
Input and Output Voltages (V)
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (20ns/div) G = +2 VH = +2V VIN VO
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 Time (20ns/div) VIN VO
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OPA688
6
TYPICAL PERFORMANCE CURVES --VS = 5V
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
(CONT)
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
2nd and 3rd Harmonic Distortion (dBc)
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 1M Frequency (Hz) 10M 20M HD3 HD2 VO = 2Vp-p RL = 500
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 HD3 HD2 VO = 0VDC 1Vp f1 = 5MHz RL = 500
Limit Voltage (V)
2ND HARMONIC DISTORTION vs OUTPUT SWING -40
2nd Harmonic Distortion (dBc)
-40
3RD HARMONIC DISTORTION vs OUTPUT SWING -45 RL = 500
-50 -55 -60 -65 -70 -75 -80 -85 -90 0.1 1.0 Output Swing (Vp-p) f1 = 10MHz
f1 = 20MHz
3rd Harmonic Distortion (dBc)
-45
RL = 500
-50 -55 -60 -65 -70 -75 -80 -85 -90 f1 = 2MHz f1 = 5MHz f1 = 10MHz f1 = 20MHz f1 = 1MHz
f1 = 5MHz f1 = 2MHz f1 = 1MHz
5.0
0.1
1.0 Output Swing (Vp-p)
5.0
HARMONIC DISTORTION vs LOAD RESISTANCE 2nd and 3rd Harmonic Distortion (dBc) -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 50 100 Load Resistance () 1000 HD3 HD2 VO = 2Vp-p f1 = 5MHz
LARGE-SIGNAL FREQUENCY RESPONSE 12 9 6 3 Gain (dB) 0 -3 -6 -9 -12 -15 -18 1M 10M 100M Frequency (Hz) 1G 2Vp-p G = +2 0.2Vp-p
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OPA688
TYPICAL PERFORMANCE CURVES --VS = 5V
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
(CONT)
RS vs CAPACITIVE LOAD 80
FREQUENCY RESPONSE vs CAPACITIVE LOAD 12 9
Gain to Capacitive Load (dB)
VO = 0.2Vp-p
70 60 50
CL = 0 CL = 10pF CL = 100pF
6 3 0 -3 -6 -9 -12
402 VIN 200 RS
RS ()
40 30 20 10 0 1 10 100 300 Capacitive Load (pF)
OPA688
402 1k
VO CL
-15 -18 1M
1k is optional
10M
100M Frequency (Hz)
1G
OPEN-LOOP FREQUENCY RESPONSE Input Voltage Noise Density (nV/Hz) Input Current Noise Density (pA/Hz) 60 50
Open-Loop Gain (dB)
INPUT NOISE DENSITY
0 Gain -30 -60 -90 VO = 0.2Vp-p -120 -150 -180 -210 -240 1G
Open-Loop Phase (deg)
100
40 30 20 10 0 -10 -20 10k
Phase
Voltage Noise 10 Current Noise 6.3nV/Hz
2.0pA/Hz 1 100 1k 10k 100k 1M 10M Frequency (Hz)
100k
1M
10M
100M
Frequency (Hz)
LIMITER SMALL-SIGNAL FREQUENCY RESPONSE 6 3 0
Feedthrough (dB)
LIMITER FEEDTHROUGH -30 -35 -40 -45 -50 -55 -60 -65 -70
402 402 200 8 VO VH = 0.02Vp-p + 2VDC
VO = 0.02Vp-p
Limiter Gain (dB)
-3 -6 -9 -12 -15 -18 -21 -24 1M 10M 100M Frequency (Hz) 1G
402 402 200 2VDC 8 VO VH = 0.02Vp-p + 2.0VDC
-75 -80 1M 10M Frequency (Hz)
50M
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OPA688
8
TYPICAL PERFORMANCE CURVES --VS = 5V
G = +2, RL = 500, RF = 402, VH = -VL = 2V (Figure 1 for AC performance only), unless otherwise noted.
(CONT)
CLOSED-LOOP OUTPUT IMPEDANCE 100
100
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE Maximum Over Temperature
Limter Input Bias Current (A)
Output Impedance ()
G = +1 RF = 25 VO = 0.2Vp-p 10
75 50 25 0 -25 -50 -75 Limiter Headroom = +VS - VH = VL - (-VS) Current = IVH or -IVL 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Minimum Over Temperature
1
0.1 1M 10M 100M 1G Frequency (Hz)
-100
Limiter Headroom (V)
SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 20 120 100
PSR AND CMR vs TEMPERATURE
PSR and CMR, Input Referred (dB)
95 90 85 80 75 70 65 60 55 50 -50 -25 0 25 50 75 100 Ambient Temperature (C) CMRR PSR+ PSRR PSR-
18
Output Current, Sourcing
110
Supply Current (mA)
16
Supply Current
100
14 | Output Current, Sinking | 12
90
80
10 -50 -25 0 25 50 75 Ambient Temperature (C)
70 100
VOLTAGE RANGES vs TEMPERATURE 5.0 VH = -VL = 4.3V 4.5 Output Voltage Range 4.0
Voltage Range (V)
3.5 Common-Mode Input Range 3.0 -50 -25 0 25 50 75 100 Ambient Temperature (C)
Output Current (mA)
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OPA688
TYPICAL PERFORMANCE CURVES --VS = +5V
G = +2, RF = 402, RL = 500 tied to VCM = 2.5V, VL = VCM -1.2V, VH = VCM +1.2V, (Figure 2 for AC performance only), unless otherwise noted.
NON-INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 12 9
Normalized Gain (dB)
6
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 VO = 0.2Vp-p G = -1 G = -2 G = -5
VO = 0.2Vp-p
G = +1, RC = , RF = 25 G = +1, RC = 175, RF = 25 G = +2, RC =
Normalized Gain (dB)
6 3 0 -3 -6 -9 -12 -15 -18 1M
VIN RS 150
0 -3 -6 -9 -12 -15 -18
VO RC RF RG
G = +5, RC = 10M 100M Frequency (Hz) 1G
-21 -24 1M 10M 100M Frequency (Hz) 1G
LARGE-SIGNAL FREQUENCY RESPONSE 12.0 9.0
Input and Output Voltages (V)
VH AND VL--LIMITED PULSE RESPONSE 5.0 4.5 VH = VCM +1.2V VL = VCM -1.2V
G = +2 0.2Vp-p
6.0 3.0
Gain (dB)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 VCM VIN VO
0 -3.0 -6.0 -9.0 -12.0 -15.0 -18.0 1M 10M 100M Frequency (Hz) 1G 2.0Vp-p
VIN
VO
Time (20ns/div)
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
2nd and 3rd Harmonic Distortion (dBc)
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 1M Frequency (Hz) 10M 20M HD3 HD2 VO = 2Vp-p RL = 500
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 HD3 HD2 VO = 2.5V 1Vp f1 = 5MHz RL = 500
| Limit Voltages - 2.5VDC |
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OPA688
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TYPICAL APPLICATIONS
DUAL SUPPLY, NON-INVERTING AMPLIFIER Figure 1 shows a non-inverting gain amplifier for dual supply operation. This circuit was used for AC characterization of the OPA688, with a 50 source, which it matches, and a 500 load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. SINGLE SUPPLY, NON-INVERTING AMPLIFIER Figure 2 shows an AC coupled, non-inverting gain amplifier for single supply operation. This circuit was used for AC characterization of the OPA688, with a 50 source, which
it matches, and a 500 load. The power supply bypass capacitors are shown explicitly in Figures 1 and 2, but will be assumed in the other figures. The limiter voltages (VH and VL) and their bias currents (IVH and IVL) have the polarities shown. Notice that the single supply circuit can use 3 resistors to set VH and VL, where the dual supply circuit usually uses 4 to reference the limit voltages to ground. LIMITED OUTPUT, ADC INPUT DRIVER Figure 3 shows a simple ADC driver that operates on single supply, and gives excellent distortion performance. The limit voltages track the input range of the converter, completely protecting against input overdrive.
3.01k +VS = +5V + 2.2F 0.1F 0.1F
1.91k
VS = +5V + 2.2F 0.1F 523 0.1F VH = 3.7V
VH = +2V 174 VIN 49.9 2 RG 402 RF 402 4 3 7 8
IVH 6 IVL 500 VO
VIN
806 0.1F 3 806 2 4 RF 402 7 8 57.6 IVH 6 IVL 976 0.1F VO 500
OPA688
5
OPA688
5
0.1F
0.1F VL = -2V
RG 402 0.1F VL = 1.3V 523
+ -VS = -5V
2.2F
3.01k
1.91k
0.1F
FIGURE 1. DC-Coupled, Dual Supply Amplifier.
FIGURE 2. AC-Coupled, Single Supply Amplifier.
VS = +5V
R6 VH = +3.35V +5V R1 C1 VIN 3 VS = +5V REFT 7 8 OPA688 2 R2 4 5 6 R5 IN C3 ADS902 10-Bit 30MSPS REFB R4 R8 R3 C2 VL = +2.15V R9 2k R7
C4
+3.25V 10-Bit Data CM 2k C5
+2.25V C6
FIGURE 3. Single Supply, Limiting ADC Input Driver.
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OPA688
The recommended component values are: R1 = R2 = 210 R5 = 24.9 R7 = R8 = 402 C3 = 100pF C1 = C2 = C4 = C5 = C6 = 0.1F PRECISION HALF WAVE RECTIFIER Figure 4 shows a half wave rectifier with outstanding precision and speed. VH (pin 8) will default to a voltage between 3.1 and 3.8V if left open, while the negative limit is set to ground.
+VS = +5V 200 VIN 2 7
R3 = R4 = 402 R6 = 536 R9 = 698
DC RESTORER Figure 7 shows a DC restorer using the OPA688 and OPA660. The OPA660's OTA amplifier is used as a current conveyor (CCII) in this circuit, with a current gain of 1.0. When VO tries to go below ground, CCII charges C1 through D1, which restores the output back to ground. D1 adds a propagation delay to the restoration process, which then has an exponential decay with time constant R1C1/G (G = +2 = the OPA688 gain). When the signal is above ground, it decays to ground with a time constant of R2C1. The OPA688 output recovers very quickly from overdrive.
3.01k +VS = +5V 0.1F 1.91k
200
NC 8 6 VO
402 VO 3 7 8 6
VIN
OPA688
3 4 402 402 5
133
OPA688
2 4 5
0.1F
-VS = -5V
FIGURE 4. Precision Half Wave Rectifier.
-VS = -5V
3.01k
1.91k
VERY HIGH SPEED SCHMITT TRIGGER Figure 5 shows a very high speed Schmitt trigger. The output levels are precisely defined, and the switching time is exceptional. The output voltage swings between 2V. UNITY-GAIN BUFFER Figure 6 shows a unity-gain voltage buffer using the OPA688. The feedback resistor (RF) isolates the output from any board inductance between pins 2 and 6. We recommend that RF 24.9 for unity-gain buffer applications. RC is an optional compensation resistor that may reduce the peaking typically seen at G = +1. Choosing RC = RS + RF gives a unity gain buffer with approximately the G = +2 frequency response.
C1 100pF 6 D1 RQ 1k D2
FIGURE 5. Very High Speed Schmitt Trigger.
RS
VS
RC
OPA688
VO
RF 24.9
FIGURE 6. Unity-Gain Buffer.
U1 200 VIN 5 +1 1 U1 = OPA660 RQ = 1k (sets U1's IQ) D1, D2 = 1N4148
20
VH = +3V 8
R2 100k
OPA688
5 VL = -1V 402
VO
20 3 B
C CCII
U1 402 2 R1 40.2
E
FIGURE 7. DC Restorer.
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DESIGN-IN TOOLS
APPLICATIONS SUPPORT The Burr-Brown Applications Department is available for design assistance at 1-800-548-6132 (US/Canada only). The Burr-Brown Internet web page (http://www.burr-brown.com) has the latest data sheets and other design aids. DEMONSTRATION BOARDS Two PC boards will be available to assist in the initial evaluation of circuit performance of the OPA688 in both package styles. These are available as an unpopulated PCB with descriptive documentation. See the demonstration board literature for more information. The summary information for these boards is shown below:
LITERATURE REQUEST NUMBER MKT-350 MKT-351
The limiters have a very sharp transition from the linear region of operation to output limiting. This allows the limiter voltages to be set very near (<100mV) the desired signal range. The distortion performance is also very good near the limiter voltages. CIRCUIT LAYOUT Achieving optimum performance with the high frequency OPA688 requires careful attention to layout design and component selection. Recommended PCB layout techniques and component selection criteria are: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken elsewhere. b) Provide a high quality power supply. Use linear regulators and power planes to provide power to the supply pins. Place high frequency 0.1F decoupling capacitors < 0.2" away from the power pins. Use wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2F to 6.8F) high frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further from the device, and be shared among several adjacent devices. c) Place external components close to the OPA688. This minimizes inductance, ground loops, transmission line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output resistors. d) Use high frequency components to minimize parasitic elements. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded resistors can also provide good performance when their leads are as short as possible. Never use wirewound resistors for high frequency applications. Remember that most potentiometers have large parasitic capacitances and inductances. Multilayer ceramic chip capacitors work best and take up little space. Monolithic ceramic capacitors also work very well. Use RF type capacitors with low ESR and ESL. The large power pin bypass capacitors (2.2F to 6.8F) should be tantalum for better high frequency and pulse performance. e) Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel capacitance. Good metal film or surface mount resistors have approximately 0.2pF parasitic parallel capacitance. For resistors > 1.5k, this adds a pole and/or zero below 500MHz. Make sure that the output loading is not too heavy. The recommended 402 feedback resistor is a good starting point in your design.
DEMONSTRATION BOARD DEM-OPA68xP DEM-OPA68xU
PACKAGE 8-Pin DIP SO-8
PRODUCT OPA68xP OPA68xU
Contact the Burr-Brown Application Department for availability of these boards. SPICE MODELS Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for high speed active devices, like the OPA688, where parasitic capacitance and inductance can have a major effect on frequency response. SPICE models will be available through the Burr-Brown web page, or on a disk (call our Application Department). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or differential gain and phase characteristics. These models do not distinguish between the AC performance of different package types.
OPERATING INFORMATION
THEORY OF OPERATION The OPA688 is a voltage feedback op amp that is unity-gain stable. The output voltage is limited to a range set by the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of the output buffer. This avoids saturating any part of the signal path, giving quick overdrive recovery and excellent limiter accuracy at any signal gain.
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OPA688
f) Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output, and use the series isolation resistor recommended in the RS vs Capacitive Load plot. Parasitic loads < 2pF may not need the isolation resistor. g) When long traces are necessary, use transmission line design techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50 transmission line is not required on board--a higher characteristic impedance will help reduce output loading. Use a matching series resistor at the output of the op amp to drive a transmission line, and a matched load resistor at the other end to make the line appear as a resistor. If the 6dB of attenuation that the matched load produces is not acceptable, and the line is not too long, use the series resistor at the source only. This will isolate the source from the reactive load presented by the line, but the frequency response will be degraded. Multiple destination devices are best handled as separate transmission lines, each with its own series source and shunt load terminations. Any parasitic impedances acting on the terminating resistors will alter the transmission line match, and can cause unwanted signal reflections and reactive loading. h) Do not use sockets for high speed parts like the OPA688. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are obtained by soldering the part onto the board. If socketing for DIP prototypes is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. POWER SUPPLIES The OPA688 is nominally specified for operation using either 5V supplies or a single +5V supply. The maximum specified total supply voltage of 12V allows reasonable tolerances on the supplies. Higher supply voltages can break down internal junctions, possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow design of non-standard or single supply operation circuits. Figure 2 shows one approach to single-supply operation. ESD PROTECTION ESD damage has been known to damage MOSFET devices, but any semiconductor device is vulnerable to ESD damage. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are required when handling the OPA688.
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OUTPUT LIMITERS The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL (pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with gain. The transition from the linear region of operation to output limiting is very sharp--the desired output signal can safely come to within 30mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within 0.7V of the supplies (VL -VS + 0.7V, VH +VS - 0.7V). They must also be at least 200mV apart (VH - VL 0.2V). When pins 5 and 8 are left open, VH and VL go to the Default Voltage Limit; the minimum values are in the spec table. Looking at Figure 8 for the zero bias current case will show the expected range of (Vs - default limit voltages) = headroom. When the limiter voltages are more than 2.1V from the supplies (VL -VS + 2.1V or VH +VS - 2.1V), you can use simple resistor dividers to set VH and VL (see Figure 1). Make sure you include the Limiter Input Bias Currents (Figure 8) in the calculations (i.e., IVL -50A out of pin 5, and IVH +50A out of pin 8). For good limiter voltage accuracy, run at least 1mA quiescent bias current through these resistors.
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE 100 Maximum Over Temperature
Limter Input Bias Current (A)
75 50 25 0 -25 -50 -75 -100 0.0 0.5 1.0 1.5 2.0 Limiter Headroom = +VS - VH = VL - (-VS) Current = IVH or -IVL 2.5 3.0 3.5 4.0 4.5 5.0 Minimum Over Temperature
Limiter Headroom (V)
FIGURE 8. Limiter Bias Current vs Bias Voltage. When the limiter voltages need to be within 2.1V of the supplies (VL -VS + 2.1V or VH +VS - 2.1V), consider using low impedance buffers to set VH and VL to minimize errors due to bias current uncertainty. This will typically be the case for single supply operation (VS = +5V). Figure 2 runs 2.5mA through the resistive divider that sets VH and VL. This keeps errors due to IVH and IVL < 1% of the target limit voltages.
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14
The limiters' DC accuracy depends on attention to detail. The two dominant error sources can be improved as follows: * Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (e.g., 5%). Using a more accurate source, and bypassing pins 5 and 8 with good capacitors, will improve limiter PSRR. * The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Other error sources also contribute, but should have little impact on the limiters' DC accuracy: * Reduce offsets caused by the Limiter Input Bias Currents. Select the resistors in the resistive divider(s) as described above. * Consider the signal path DC errors as contributing to uncertainty in the useable output swing. * The Limiter Offset Voltage only slightly degrades limiter accuracy. Figure 9 shows how the limiters affect distortion performance. Virtually no degradation in linearity is observed for output voltage swinging right up to the limiter voltages.
HARMONIC DISTORTION NEAR LIMIT VOLTAGES 2nd and 3rd Harmonic Distortion (dBc) -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 HD3 HD2 VO = 0VDC 1Vp f1 = 5MHz RL = 500
Remember that additional offset errors can be created by the amplifier's input bias currents. Whenever possible, match the impedance seen by both DC input bias currents using R3. This minimizes the output offset voltage caused by the input bias currents. OUTPUT DRIVE The OPA688 has been optimized to drive 500 loads, such as A/D converters. It still performs very well driving 100 loads; the specifications are shown for the 500 load. This makes the OPA688 an ideal choice for a wide range of high frequency applications. Many high speed applications, such as driving A/D converters, require op amps with low output impedance. As shown in the Output Impedance vs Frequency performance curve, the OPA688 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency. THERMAL CONSIDERATIONS The OPA688 will not require heat-sinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175C. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated in the output stage (PDL) while delivering load power. PDQ is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded resistive load, and equal bipolar supplies, it is at a maximum when the output is at 1/2 either supply voltage. In this condition, PDL = VS2/ (4RL) where RL includes the feedback network loading. Note that it is the power in the output stage, and not in the load, that determines internal power dissipation. The operating junction temperature is: TJ = TA + PD JA, where TA is the ambient temperature. For example, the maximum TJ for a OPA688U with G = +2, RFB = 402, RL = 100, and VS = 5V at the maximum TA = +85C is calculated as:
P DQ = (10V * 20mA ) = 200mW P DL = 4 * (100 ||804 )
Limit Voltage (V)
FIGURE 9. Harmonic Distortion Near Limit Voltages. OFFSET VOLTAGE ADJUSTMENT The circuit in Figure 10 allows offset adjustment without degrading offset drift with temperature. Use this circuit with caution since power supply noise can inadvertently couple into the op amp.
+VS RTRIM 47k OPA688 -VS 0.1F R1 R3 = R1 || R2 VO R2
( 5V )2
= 70mW
P D = 200mW + 70mW = 270mW T J = 85 C + 270mW *125 C / W = 119 C
VIN or Ground
NOTES: (1) R3 is optional and minimizes output offset due to input bias currents. (2) Set R1 << RTRIM.
CAPACITIVE LOADS Capacitive loads, such as the input to ADCs, will decrease the amplifier's phase margin, which may cause high frequency peaking or oscillations. Capacitive loads 2pF should be isolated by connecting a small resistor in series
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FIGURE 10. Offset Voltage Trim. 15
OPA688
with the output as shown in Figure 11. Increasing the gain from +2 will improve the capacitive drive capabilities due to increased phase margin.
bandwidth will be limited by the pole that the feedback resistor and this capacitor create. In other high gain applications, use a three resistor "Tee" network to reduce the RC time constants set by the parasitic capacitances. Be careful to not increase the noise generated by this feedback network too much. PULSE SETTLING TIME The OPA688 is capable of an extremely fast settling time in response to a pulse input. Frequency response flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an A/D converter, use the recommended RS in the RS vs Capacitive Load plot. Extremely fine scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors. The pulse settling characteristics when recovering from overdrive are very good. DISTORTION The OPA688's distortion performance is specified for a 500 load, such as an A/D converter. Driving loads with smaller resistance will increase the distortion as illustrated in Figure 12. Remember to include the feedback network in the load resistance calculations.
RS OPA688 VO
RL
CL
RL is optional
FIGURE 11. Driving Capacitive Loads. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if they are properly terminated. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable, or transmission line, is terminated in its characteristic impedance. FREQUENCY RESPONSE COMPENSATION The OPA688 is internally compensated to be unity-gain stable, and has a nominal phase margin of 60 at a gain of +2. Phase margin and peaking improve at higher gains. Recall that an inverting gain of -1 is equivalent to a gain of +2 for bandwidth purposes (i.e., noise gain = 2). Standard external compensation techniques work with this device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, which limits the bandwidth. To maintain a wide bandwidth at high gains, cascade several op amps, or use the high gain optimized OPA689. In applications where a large feedback resistor is required, such as photodiode transimpedance amplifier, the parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this effect, connect a small capacitor in parallel with the feedback resistor. The
HARMONIC DISTORTION vs LOAD RESISTANCE
2nd and 3rd Harmonic Distortion (dBc)
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 50 100 Load Resistance () 1000 HD3 HD2 VO = 2Vp-p f1 = 5MHz
FIGURE 12. 5MHz Harmonic Distortion vs Load Resistance.
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