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| SN54/74LS173A 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS The SN54 / 74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE1, OE2) brings the output to a high impedance state without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE1, OE2) or the Input Enable (IE1, IE2) lines. * Fully Edge-Triggered * 3-State Outputs * Gated Input and Output Enables * Input Clamp Diodes Limit High-Speed Termination Effects 16 1 4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 MR 15 D0 14 D1 13 D2 12 D3 11 IE2 10 IE1 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 OE1 2 OE2 3 Q0 4 Q1 5 Q2 6 Q3 7 CP 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. D0 - D3 IE1 - IE2 OE1 - OE2 CP MR Q0 - Q3 Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs Clock Pulse (Active HIGH Going Edge) Input Master Reset Input (Active HIGH) Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. LOGIC SYMBOL 9 10 12 IE CP 1 2 OE MR Q0 Q1 Q2 Q3 D0 D1 D2 D3 14 13 12 11 7 1 2 NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. 15 3456 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS173A LOGIC DIAGRAM D0 14 D1 13 D2 12 D3 11 IE1 IE2 9 10 CP 7 CP D Q MR 15 D D D Q OE1 OE2 1 2 3 4 5 6 Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS TRUTH TABLE MR H L L L L L CP x L IE1 x x H x L L IE2 x x x H L L Dn x x x x L H Qn L Qn Qn Qn L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial When either OE1, or OE2 are HIGH, the output is in the off state (High Impedance); however this does not affect the contents or sequential operation of the register. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 1.0 - 2.6 12 24 Unit V C mA mA FAST AND LS TTL DATA 5-2 SN54/74LS173A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 30 - 0.4 - 130 30 0.35 0.5 20 - 20 20 V A A A mA mA mA mA 2.4 3.1 0.25 0.4 V V 2.4 - 0.65 3.4 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VO = 2.7 V VCC = MAX, VO = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol S bl fMAX tPLH tPHL tPHL tPZH tPZL tPLZ tPHZ Parameter P Maximum Input Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Output Enable Time Output Disable Time Min 30 Typ 50 17 22 26 15 18 11 11 25 30 35 23 27 17 17 Max Unit Ui MHz ns ns ns ns CL = 5.0 pF, RL = 667 VCC = 5.0 V 50 CL = 45 pF, pF RL = 667 Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol S bl tW ts ts th trec Parameter P Clock or MR Pulse Width Data Enable Setup Time Data Setup Time Hold Time, Any Input Recovery Time Min 20 35 17 0 10 Typ Max Unit Ui ns ns ns ns ns 50 VCC = 5.0 V Test C di i T Conditions FAST AND LS TTL DATA 5-3 SN54/74LS173A AC WAVEFORMS 1 / fmax tW 1.3 V ts(H) D or E 1.3 V th(H) ts(L) 1.3 V th(L) 1.3 V Q Q tPLH 1.3 V tPHL 1.3 V MR tW CP tPHL 1.3 V trec 1.3 V CP Figure 1 Figure 2 VE 1.3 V tPLZ 1.3 V tPZL 1.3 V 0.5 V VOL VE 1.3 V tPZH tPHZ 1.3 V VOH 1.3 V 0.5 V VOUT VOUT 1.3 V Figure 3 Figure 4 AC LOAD CIRCUIT VCC RL SYMBOL SW1 TO OUTPUT UNDER TEST tPZH tPZL tPLZ tPHZ 5 k CL* SWITCH POSITIONS SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed SW2 * Includes Jig and Probe Capacitance. Figure 5 FAST AND LS TTL DATA 5-4 |
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