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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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155Mb/s / 622Mb/s Receiver (Demultiplexer) with Clock Recovery
The MC10SX1401 receiver (Rx) chip is an integrated de-serialization SONET OC-3 (155.52 Mb/s) and OC-12 (622.08 Mb/s) interface device. It performs the data and clock recovery and serial-to-parallel conversion functions in conformance with SONET/SDH transmission standards. High performance and low power is achieved with MOSAIC VTM, Motorola's most advanced high-performance silicon Bipolar process. A companion serialization (Tx) chip, the SX1405, is also available.
MC10SX1401
RECEIVER (DEMULTIPLEXER) WITH CLOCK RECOVERY
* Recovers a 155.52/622.08 MHz internal clock from an OC3/OC12 data
stream
* Samples, quantizes and demultiplexes the input signal into a parallel
TTL data stream * Generates an EVEN parity bit with the demultiplexed data
* Provides a 155.52 MHz differential PECL timing reference clock * No external input reference clock is required * Detects the peak amplitude of the Rx signal and generates a
proportional DC voltage
* Provides PLL Frequency Control Monitor and Out-of-Lock Indicator * Selectable eight or four bit parallel interface * Single supply operation (+5V)
APPLICATIONS
FJ SUFFIX 52-LEAD CLCC PACKAGE CASE 778B-01
* * * *
SONET/SDH-based transmission systems, modules, test equipment ATM using SONET Add drop multiplexers Other (non-SONET) data rate transmission systems
TX SX1405 Parallel Data and Control
Laser Driver SX1130
Laser
CONTROL LOGIC
RX SX1401
Post Amp SX1125
PIN
Figure 1. Typical OC3/OC12 Electro-Optical Interface
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 5/98
(c) Motorola, Inc. 1998
1
REV 0.4
Optical Interface
MC10SX1401
CONTROL LOGIC
DIFFERENTIAL RX INPUT RISP POST AMPLIFIER DATA DETECTION AND RETIMING SERIAL TO PARALLEL ELECTRO- OPTICAL MODULE
PARALLEL DATA OUTPUT
RISN
ROD1:8 OC3 (STM1) REP OC12 (STM4) Interface
ROC CLOCK RECOVERY
MC10SX1401
Figure 2. MC10SX1401 Simplified Block Diagram
MX10SX1401 Theory of Operation Operation of the SX1401 is straight forward. The device recovers clock and data from the serial input. Serial- to-parallel conversion is performed. Then the parallel data, parity, and recovered clock is output. The bit-serial 622 Mbit/s or 155 Mbit/s data stream is converted into a 78 MByte/s or 19 MByte/s parallel data format. The Data Clock is recovered from the incoming data stream. No external reference clock is required. For testing and applications which provide an external high-frequency bit clock, the internal clock recovery circuit may be bypassed. SX1401 Block Diagram Functional Description
Data Detection and Retiming
Receives the differential input signal and retimes the serial data with the Recovered Clock. The peak amplitude of the differential input signal is also detected and a proportional Peak Detector Output (PDO) DC voltage is output.
Serial to Parallel Conversion In OC3 mode, converts the retimed serial data into either a 4-bit (Nibble) or 8-bit (Byte) parallel format. This parallel data is output to the ROD1:8 Bus. In Nibble mode, the data appears on ROD2, 4, 6, 8. In OC12 mode, the retimed serial data is converted into an 8-bit (Byte) parallel format. This parallel data is output to the ROD1:8 Bus. A parity bit is also generated from the retimed serial data as it is shifted into the parallel register. the Receive Even Parity Output (REP) is toggled whenever the current nibble has EVEN parity. The internal Recovered Clock is buffered and output as a TTL Receive Output Data Clock (ROC) at 78MHz, 39MHz, or 19MHz, depending on the selected mode. Also output is a PECL Differential Receiver Clock (RCKP/RCKM) at 155MHz.
SX1401 Control Signals Reset (RSTN) - Used for testing and verification, the TTL outputs are set to Tri-State and all divider flip-flops are reset by applying RSTN LOW. An internal pull-up is provided on RSTN allowing the device to operate normally if RSTN is not used. Low Speed Select (LSS) - Selects data rate. LOW = OC-12 (622.08 Mb/s), HIGH = OC-3 (155.52 Mb/s). An internal pull-up is provided on LSS allowing the device to operate in OC-12 mode if LSS is not used. Byte / Nibble Select (BYTE) - In OC-3 mode, selects between 4-bit (Nibble) and 8-bit (Byte) parallel data output format. LOW = Nibble, HIGH = Byte. An internal pull-up is provided on BYTE allowing the device to operate in Byte mode if BYTE is not used.
Clock Recovery
Using a standard phase locked loop (PLL) configuration, the clock recovery circuit locks the output of an internal VCO to the phase and frequency of the detected differential input signal. The internal VCO operates nominally at 1.2GHz. The output of the VCO is then divided to provide an internal Recovered Clock at either 622MHz or 155MHz. An Out Of Lock indicator (OOL) is driven HIGH if the PLL is not locked.
MOTOROLA
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1401
External Clock Select (ECSN) - Allows external high-frequency bit clock to be applied and bypasses the internal clock recovery circuit. LOW = External bit clock. An internal pull-up is provided on ECSN allowing the device to operate normally if ECSN is not used. VCO Frequency Control Monitor (FCM) - Single ended reference voltage output generated from the VCO control voltage. Typically 1.25V and varying from 0.25V to 2.25V. Out of Lock Indicator (OOL) - Is set HIGH if the PLL is not frequency-locked to the incoming serial stream.
7 AVCC C3 13 PDC C1 R1 50 FILTN 51 FILTC C2 R2 52 FILTP
49 AVCC
18 VCC
26 VCC
19 VCCT
27 VCCT
36 VCCT
21 VCCO
48 VBR1 47 SX1401 VBR2 46 VBR4 45 VBR3 VEET VEET VEET AVEE AVEE AVEE AVEE VEE
0.1F 2k
0.1F
OC3 Mode C1, C2 = 0.1F R1, R2 = 143 C3 = 820pF OC12 Mode C1, C2 = TBD R1, R2 = TBD C1 = 220pF
2
VEE 14
3
4
43
44
15
24
38
Figure 3. SX1401 Typical Operating Circuit
ECLinPS and ECLinPS Lite DL140 -- Rev 3
3
MOTOROLA
MC10SX1401
ECSN ROD8 35 ROD7 34 33 32 31 30 29 28 27 26 25 24 23 22 21 8 N/C 9 N/C 10 N/C 11 N/C 12 PDO 13 PDC 14 VEE 15 VEET 16 N/C 17 OOL 18 VCC 19 VCCT 20 REP ROD6 ROD5 ROD4 ROD3 ROD2 ROD1 VCCT VCC ROC VEET RCKP RCKM VCCO RSTN 37 VCCT 36 VEET 38 VBR4 VBR3 BYTE 40 4 AVEE AVEE
ECK
46 VBR2 VBR1 AVCC FILTN FILTP FILTC FCM VEE AVEE AVEE RISN RISP AVCC 47 48 49 50 51 52 1 2 3 4 5 6 7
45
44
43
42
41
Figure 4. MC10SX1401 52-Lead Pinout (Top View)
MOTOROLA
LSS 39
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1401
Table 1. SX1401 Pin Descriptions
Name TTL Compatible I/O OOL REP ROC ROD1 ROD2 ROD3 ROD4 ROD5 ROD6 ROD7 ROD8 RSTN LSS BYTE ECSN PECL Compatible I/O RCKM RCKP ECK Analog I/O FCM RISN RISP PDO PDC VBR4-VBR1 FILTN FILTC FILTP Power and Ground Pins VEE AVEE AVCC VEET VCC VCCT VCCO Reserved N/C 8-11, 16 Reserved for Factory Test 2, 14 3, 4, 43, 44 7, 49 15, 24, 38 18, 26 19, 27, 36 21 PECL 0V Supply Analog 0V Supply Analog +5V Supply Output TTL 0V Supply PECL +5V Supply Output TTL +5V Supply Output PECL +5V Supply 1 5 6 12 13 45-48 50 51 52 VCO Frequency Control Monitor Output Serial Data Input Negative Serial Data Input Positive Peak Detector Output Peak Detector Capacitor VCO Filter Pins Loop Filter Negative Loop Filter Positive Loop Filter Common 22 23 41 Differential Receiver Clock Minus Output Differential Receiver Clock Plus Output External Clock Output 17 20 25 28 29 30 31 32 33 34 35 37 39 40 42 Out of Lock Indicator Output Receive Even Parity Output Receive Output Data Clock Parallel Output Data (Byte MSB) Parallel Output Data (Nibble MSB) Parallel Output Data Parallel Output Data (Nibble MSB-1) Parallel Output Data Parallel Output Data (Nibble MSB-2) Parallel Output Data Parallel Output Data (Byte and Nibble LSB) Reset Input Low Speed Select Input Byte / Nibble Select Input External Clock Select Input Pin No Description
ECLinPS and ECLinPS Lite DL140 -- Rev 3
5
MOTOROLA
MC10SX1401
MAXIMUM RATINGS*
Symbol VCC, VCCO, VCCT, AVCC VIN IOUT IOUT-TTL TSTG Parameter Power Supply (VEE, VEET, AVEE, GVEE = 0V) Input Voltage (VEE, VEET, AVEE, GVEE = 0V) PECL Output Current TTL Output Current Storage Temperature Continuous Surge Value -0.5 to +6.5 -0.5 to +6.5 50 100 5 -50 to +175 Unit V V mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC, VCCO, VCCT, AVCC ICC TA TJ Parameter Power Supply (VEE, VEET, AVEE, GVEE = 0V) Device Current Drain Operating Temperature Junction Temperature Value 5V 5% 225 -40 to +85 125 Unit V mA C C
TTL DC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IIH IIL VOH VOL VIH VIL IOZ Characteristic Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Tri-State Current 2.0 0.8 50 REP, ROD EDO, OOL 2.5 2.5 0.5 Min Typ Max 20 -0.6 Unit A mA V V V V A Condition VIN = VCC VIN = 0.5V IOH = -2mA IOH = -300A IOL = 5mA
100E PECL DC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IIH IIL VOH VOL VIH VIL Characteristic Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage 0.5 3.93 3.19 3.93 3.19 4.19 3.45 4.19 3.43 Min Typ Max 200 Unit mA mA V V V V NOTE 1. NOTE 1. NOTE 1. NOTE 1. Condition
1. PECL levels are referenced to VCC and will vary 1:1 with the Power Supply. The Outputs are loaded with an equivalent 50 termination to +3.0V. The values shown are for VCC = VCCT = VCCO = AVCC = 5.0V.
MOTOROLA
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1401
PLL COMPONENT CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol IFILT Characteristic Loop Filter Currents (FILTP-FILTN) Min 250 -450 -20 -40 -40 -40 45 100 -0.5 0.4 0.65 1.1 -100 0.45 5000 800 1000 120 -80 -30 -90 180 1244 1700 1450 260 80 250 0.5 2 1.85 1.4 100 0.55 Typ Max 450 -250 20 40 40 40 80 Unit A Condition PD Up, FD=Neutral PD Down, FD = Neutral PD, FD = Neutral FD Up, PD = Neutral FD Down, PD = Neutral IUP + IDOWN
IUP + IDN Kdt ADV E VFCM
Phase Detector UP + DOWN Current Combined Phase Detector TZA Gain Loop Filter Amplifier Large Signal Differential Voltage Amplification Phase Error FCM Amplitude Range FCM Locked PLL Range FCM Shorted
A A/rad V/V radians V V V mV gain MHz MHz MHz/V MHz/V dBc/Hz dBc/Hz
FILTP, FILTN Shorted
EFCM KFCM RO fVCO
FCM Error FCM Gain FCM Output Impedance VCO Frequency VCO Frequency Shorted
2000 (1%) - EXT. R FILTP, FILTN Shorted 2000 (1%) - EXT. R 0 < fVCC < 10MHz at f = 1kHz at f = 1kHz
KO KOVCC VCO
VCO Gain VCC Supply (AVCC) Sensitivity VCO Phase Noise
DATA INPUT CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V 5%)
Symbol VRIS VSO VSO VDT VDT VDTO VDTO RI RI CI Characteristic Input SIgnal Amplitude Input Offset (DST) Relative Input Offset (DST/EST) Input Offset Sensitivity Relative Input Offset Sensitivity Slicing Threshold Offset Relative Slicing Threshold Offset Input Resistance - DC Input Resistance - AC Input Capacitance Min 40 -10 -10 0.05 -0.05 -90 -90 2000 1360 1.0 3 3 Typ Max 2000 10 10 0.15 0.05 90 90 Unit mV mV mV V/V V/V mV mV pF Condition PP-DIFF AC Coupled VDST=VR=1.25V VDST=VEST=1.25V VRIS= 100mV VRIS= 100mV VRIS=0V VRIS=0V Across RISP, RISN Across RISP, RISN RISP, RISN
PEAK DETECTOR CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V +5%)
Symbol VPDO KPDO Characteristic Peak Detector Output Peak Detector Voltage Sensitivity Min 1.30 2.5 Typ Max 1.65 4.0 Unit V mV/mVpp Condition PDC cap = 1000pF (OC3) PDC cap = 1000pF (OC3)
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MOTOROLA
MC10SX1401
AC CHARACTERISTICS (VCC = VCCT = VCCO = AVCC = 5.0V +5%)
Symbol tr, tf tr, tf tpd tdc tdc Characteristic PECL Rise/Fall Time TTL Rise/Fall Time Skew: ROC ROD, ROP Duty Cycle: ROC, OC3 Duty Cycle: RCK, OC3 ROC ROD, REP -3.0 -15 -15 Min Typ Max 1.6 3.2 5.0 3.0 15 15 Unit nS nS nS % % th/(tl+th) th/(tl+th) Condition 20-80% 20-80%, 500, 20pF
bits 0-3 of nibble n-1 Input Data RISP/RISN ROD ROP ROC RCK 0 3 2 1 0 3
bits 0-3 of nibble n 2 1 0 3
bits 0-3 of nibble n+1 2 1 0 3
bits 0-3 of nibble n+2 2 1 0 3
bits 0-3 of nibble n-2 parity of nibble n-2
bits 0-3 of nibble n-1 parity of nibble n-1
bits 0-3 of nibble n parity of nibble n
Figure 5. SX1401 Timing Diagram -- OC-3, 4 Bits
bits 0-7 of byte n Input Data RISP/RISN ROD ROP ROC RCK 0 7 6 5 4 3 2 1 0 7 6 5
bits 0-7 of byte n+1 4 3 2 1 0 7
bits 0-7 of byte n-1 parity of byte n-1
bits 0-7 of byte n parity of byte n
Figure 6. SX1401 Timing Diagram -- OC-3, 8 Bits
MOTOROLA
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10SX1401
bits 0-7 of byte n Input Data RISP/RISN ROD ROP ROC RCK 0 7 6 5 4 3 2 1 0 7 6 5
bits 0-7 of byte n+1 4 3 2 1 0 7
bits 0-7 of byte n-1 parity of byte n-1
bits 0-7 of byte n parity of byte n
Figure 7. SX1401 Timing Diagram -- OC-12, 8 Bits (Note: The relative phase of RCK with ROD, ROP and ROC is not guaranteed. The depiction here is merely to show relative frequency)
ECLinPS and ECLinPS Lite DL140 -- Rev 3
9
MOTOROLA
MC10SX1401
OUTLINE DIMENSIONS
FJ SUFFIX CLCC PACKAGE CASE 778B-01 ISSUE O
-A- R 0.51 (0.020)
M
TA
S
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION R AND N DO NOT INCLUDE GLASS PROTRUSION. GLASS PROTRUSION TO BE 0.25 (0.010) MAXIMUM. 4. ALL DIMENSIONS AND TOLERANCES INCLUDE LEAD TRIM OFFSET AND LEAD FINISH. DIM A B C D F G H J K N R S INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.200 0.017 0.021 0.026 0.032 0.050 BSC 0.090 0.130 0.006 0.010 0.035 0.045 0.735 0.756 0.735 0.756 0.690 0.730 MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 5.08 0.44 0.53 0.67 0.81 1.27 BSC 2.29 3.30 0.16 0.25 0.89 1.14 18.67 19.20 18.67 19.20 17.53 18.54
N
-B-
0.51 (0.020) F
M
TA
S
B
S
K H
C J
0.15 (0.006) G D 52 PL S 0.18 (0.007)
M
-T-
SEATING PLANE
TA
S
B
S
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MOTOROLA 10
MC10SX1401/D ECLinPS and ECLinPS Lite DL140 -- Rev 3

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