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May 1999
CLC5958 14-bit, 52MSPS A/D Converter
N
CLC5958 14-bit, 52MSPS A/D Converter
General Description
The CLC5958 is a monolithic 14-bit, 52MSPS analog-to-digital converter. The ultra-wide dynamic range and high sample rate of the device make it an excellent choice for wideband receivers found in multi-channel basestations. The CLC5958 integrates a low distortion track-and-hold amplifier and a 14-bit multi-stage quantizer on a single die. Other features include differential analog inputs, low jitter differential clock inputs, an internal bandgap voltage reference, and CMOS/TTL compatible outputs. The CLC5958 is fabricated on the National ABIC-V 0.8 micron BiCMOS process. The CLC5958 features a 90dB spurious free dynamic range (SFDR) and a 70dB signal to noise ratio (SNR). The balanced differential analog inputs ensure low even-order distortion, while the differential clock inputs permit the use of balanced clock signals to minimize clock jitter. The 48-pin CSP package provides an extremely small footprint for applications where space is a critical consideration. The package also provides a very low thermal resistance to ambient. The CLC5958 may be operated with a single +5V power supply. Alternatively, an additional supply may be used to program the digital output levels over the range of +3.3V to +5V. Operation over the industrial temperature range of -40C to +85C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications.
Features
* 14-bit * 52MSPS * Ultra-wide dynamic range Noise floor: -72dBFS SFDR: 90dB * Excellent performance to Nyquist * IF sampling capability * Very small package: 48-pin CSP * Programmable output levels: 3.3V to 5V
Applications
* Multi-channel basestations * Multi-standard basestations: GSM, WCDMA, DAMPS, etc. * Smart antenna systems * Wireless local loop * Wideband digital communications
Actual Size (Bottom View)
Single-Tone Output Spectrum
0 -20 -20
Output Response with GSM 1800 Blocker Power at the Antenna (dBm)
Full Scale = -24dBM Res. BW = 200KHz
Sample Rate = 52MSPS Input Frequency = 5MHz
-40 -60 -80 -100 -120
-25dBm blocker
Power (dBFS)
-40 -60 -80 -100 -120 0 5 10 15 20 25
-101dBm reference
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
(c) 1999 National Semiconductor Corporation
Printed in the U.S.A.
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CLC5958 Electrical Characteristics (Vcc= +5V, DVcc= +3.3V, 52MSPS; unless specified, Tmin = -40C, Tmax = +85C)
PARAMETERS CONDITIONS TEMP MIN RESOLUTION DIFF. INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE SNR SFDR SFDR EXCLUDING 2nd & 3rd HARM. NO MISSING CODES Full Full Full +25C +25C +25C +25C RATINGS TYP 14 2.048 65 71 90 92 Guaranteed MAX Bits V MSPS dBFS dB dB 1 1 1 1 1 1 2 +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full +25C +25C +25C +25C Full Full Full Full Full 3.9 3.0 0.2 2 25 -71.0 -72.0 -90 -87 -78 -92 -90 -90 -95 -95 -82 -95 -100 69 -95 -100 100e-6 0.3 1.5 2.0 2 210 0.5 -0.2 3 6.6 6.6 500 3.6 4.5 3.8 dBFS dBFS dBFS dBFS dBFS 3 dBFS dBFS dBFS 4 dBFS dBFS dBFS dBFS dBFS dB dBFS dBFS UNITS NOTES
fin = 10MHZ, Ain = -0.6dBFS fin = 10MHZ, Ain = -0.6dBFS fin = 10MHZ, Ain = -0.6dBFS fin = 10MHZ, Ain = -0.6dBFS
52 69 80 85
NOISE AND DISTORTION noise floor fin = 5MHz Ain = -1dBFS fin = 5MHz Ain = -20dBFS 2nd & 3rd harmonic distortion (w/o dither) Ain = -1dBFS fin = 5MHz fin = 20MHz Ain = -1dBFS fin = 70MHz Ain = -3dBFS next worst harmonic distortion (w/o dither) Ain = -1dBFS fin = 5MHz fin = 20MHz Ain = -1dBFS fin = 70MHz Ain = -3dBFS worst harmonic distortion (with dither) Ain = -6dBFS fin = 5MHz fin = 20MHz Ain = -6dBFS Ain = -6dBFS fin = 70MHz fin = 70MHz (2nd & 3rd excluded) Ain = -6dBFS 2-Tone IM distortion (w/o dither) fin1 =12MHz, fin2 = 15MHz Ain1 = Ain2 = -7dBFS SINAD (w/o dither) Ain = -1dBFS fin = 5MHz CLOCK RELATED SPURIOUS TONES fs/8, fs/4 next worst clock spur calibration sideband coefficient DC ACCURACY AND PERFORMANCE differential non-linearity integral non-linearity offset error gain error DYNAMIC PERFORMANCE large-signal bandwidth aperture jitter TIMING effective aperture delay (tA) pipeline delay (tP) output buffer delay (to) data valid buffer delay (tDAV) ANALOG INPUT CHARACTERISTICS single-ended input resistance single-ended capacitance ENCODE INPUT CHARACTERISTICS VIH VIL differential input swing IIL IIH
5 6
LSB LSB mV % of FS MHz ps(rms) ns clk cycle ns ns pF V V V A A 7 7
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
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CLC5958 Electrical Characteristics (Vcc= +5V, DVcc= +3.3V, 52MSPS; unless specified, Tmin = -40C, Tmax = +85C)
PARAMETERS CONDITIONS TEMP MIN DIGITAL OUTPUT CHARACTERISTICS VOH IOH = 50A VOL IOL = 50A SUPPLY CHARACTERISTICS +5V supply current (VCC) +3.3V supply current (DVCC) power dissipation VCC power supply rejection ratio Full Full +25C +25C +25C +25C 3.2 0.1 260 32 1.4 0.75 300 40 RATINGS TYP MAX V V mA mA W mV/V 1 1 UNITS NOTES
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.
CLC5958 Timing Diagram Notes
1) 2) 3) 4) 5) These parameters are 100% tested at 25C. Harmonics and clock spurious are removed in noise measurements. 4th or higher harmonic. Low frequency dither injected in the DC to 500KHz band. Next worst clock spur is a subharmonic of fs, but not fs/8 or fs/4. See text on spurious.
N+1
6) 7)
See text on calibration sidebands in the application information section. Encode levels are referenced to VCC, i.e. the minimum VIH value is 1.1V below VCC, and the maximum VIH value is 0.5V below VCC.
Analog Input
tA
ENCODE Data DAV
tO
N N-3
N+1 N-2
N+2 N-1
N+3 N
tDAV
Delay from rising edge of ENCODE to output data transition - nominally 6.6ns tDAV: Delay from falling edge of ENCODE to rising edge of DAV - nominally 6.6ns Effective aperture delay tA: - nominally -0.2ns
tO:
CLC5958 Timing Diagram
Absolute Maximum Ratings
positive supply voltage differential voltage between any two grounds analog input voltage range digital input voltage range output short circuit duration (one-pin to ground) junction temperature storage temperature range lead solder duration (+240C) (VCC) -0.5V to +6V <200mV GND to VCC -0.5V to +VCC infinite 175C -65C to 150C 5sec
Recommended Operating Conditions
positive supply voltage (VCC) analog input voltage range input coupling operating temperature range digital output supply voltage (DVCC) analog input common mode voltage +5V 5% 2.048Vpp diff. AC -40C to +85C +3.3V 5% Vcm 0.025V
Package Thermal Resistance
Package JA 39C/W JC 5C/W 48-pin CSP
Note: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability.
Package Transistor Count
Transistor count 10,000
Ordering Information
Model CLC5958SLB CLC5958PCASM Temperature Range -40C to +85C Description 48-pin CSP (industrial temperature range) Fully loaded evaluation board with CLC5958 ... ready for test.
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CLC5958 Typical Performance Characteristics (Vcc= +5V, 52MSPS; unless specified)
Single-Tone Output Spectrum
0 -20
Fs = 52MSPS Fin = 5MHz Ain = -0.6dBFS
Single-Tone Output Spectrum
0 -20
Fs = 52MSPS Fin = 75MHz Ain = -3.2dBFS
Power (dBFS)
Power (dBFS)
-40 -60 -80 -100
-120 0 5 10 15 20 25
-40
Fundamental = 75MHz
-60 -80 -100
-120 0 5 10 15 20 25
2nd
3rd
Frequency (MHz)
Frequency (MHz) Single-Tone Output Spectrum w/200KHz Res. BW
-20
Single-Tone Output Spectrum (w/Dither)
0 -20
Power at the Antenna (dBm)
Fs = 52MSPS Fin = 10MHz Ain = -6dBFS Dither
-40 -60 -80
Full Scale = -24dBm Fin = 10MHz Ain = -25dBm
Power (dBFS)
-40 -60 -80 -100
-120 0
-101dBm reference
-100
-120
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
Two-Tone Output Spectrum
0 -20
f1 f2
Two-Tone Output Spec. w/200KHz Res. BW
-20
Power at the Antenna (dBm)
Fs = 52MSPS f1 = 10MHz f2 = 15MHz
-40 -60 -80 -100
-120
Power (dBFS)
-40 -60 -80 -100
-120 0 5 10 15 20 25
f2-f1 f1+f2 2f2-f1
Fin1 = 5MHz Fin2 = 10MHz Ain1 = -31dBm Ain2 = -31dBm
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
Differential Non-Linearity
1.0
Fs = 52MSPS Fin = 4.9791
Integral Non-Linearity
3.0 2.0 1.0
0.6 0.2 -0.2 -0.6 -1.0 0 4000 8000 12000 16000
LSBs
LSBs
0 -1.0 -2.0 -3.0 0 4000 8000 12000 16000
Fs = 52MSPS Fin = 4.9791MHz
Code
Code
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CLC5958 Typical Performance Characteristics (Vcc= +5V, 52MSPS; unless specified)
Noise and Spurious vs. Amplitude at Fin = 10MHz
120
Fs = 52MSPS
Spurious vs. Amplitude with Dither at Fin = 10MHz
120 110
2nd or 3rd Harmonic
110
Other Spurious
100
Fs/8 or Fs/4
100
-dBFS
90
2nd or 3rd Harmonic
-dBFS
90 80
Other Spurious
Fs/8 or Fs/4
80
Noise Floor
70 60 -70 -60 -50 -40 -30 -20 -10 0
70
Fs = 52MSPS
60 -70 -60 -50 -40 -30 -20 -10 0
Amplitude (dBFS) Noise and Spurious vs. Amplitude at Fin = 75MHz
120
Fs = 52MSPS
Amplitude (dBFS) Spurious vs. Amplitude with Dither at Fin = 75MHz
120 110
Fs/8 or Fs/4 2nd or 3rd Harmonic
110 100
100
-dBFS
90 80 70 60 -70 -60 -50 -40 -30 -20 -10 0
Other Spurious 2nd or 3rd Harmonic Noise Floor
-dBFS
90 80 70
Other Spurious
Fs/8 or Fs/4
Fs = 52MSPS
60 -70 -60 -50 -40 -30 -20 -10 0
Amplitude (dBFS)
Amplitude (dBFS)
Noise and Distortion vs. Sample Rate
120 110 100
2nd or 3rd Harmonic Fin = 10MHz Ain = -0.6dBFS
Clock Spurious vs. Sample Rate
120
Fin = 10MHz Ain = -0.6dBFS
110
fs/8 "next clock spurs"
90 80 70
Noise Floor Other Spurious
-dBFS
dBFS
100
fs/4
90 80 70
60 10 20 30 40 50 60 70
10
20
30
40
50
60
70
Sample Rate (MSPS)
Sample Rate (MSPS)
Noise and Spurious vs. Input Frequency
120 110 100
Fs = 52MSPS Ain = -0.6dBFS Fs/8 or Fs/4
Noise and Spurious vs. Input Frequency
120 110
Other Spurious Fs = 52MSPS Ain = -3.2dBFS
100
Fs/8 or Fs/4
-dBFS
-dBFS
90
2nd or 3rd Harmonic
90 80
2nd or 3rd Harmonic
80
Other Spurious
70 60 0
Noise Floor
70 60
Noise Floor
5
10
15
20
25
0
10
20
30
40
50
60
70
Input Frequency (MHz)
Input Frequency (MHz)
5
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CLC5958 Pin Definitions
1 GND 2 GND 3 GND 4 GND 5 VCC 6 VCC 7 VCC 8 GND 9 ENCODE 10 ENCODE 11 GND 12 GND 13 AIN 14 AIN 15 GND 16 VCC 17 VCC 18 VCC 19 GND 20 GND 21 VCM 22 VCC 23 GND 24 GND GND 48 GND 47 VCC 46
AIN, AIN
(Pins 13, 14) Differential inputs. Self biased at a common mode voltage of +3.25V. The ADC full scale input is 2.048Vpp differential. (Pins 9, 10) Differential clock inputs. ENCODE initiates a new data conversion cycle on each rising edge. Clock signals may be sinusoidal or square waves with PECL encode levels. The falling edge of ENCODE clocks internal pipeline stages. (Pins 28 - 34, 39 - 45) Digital data outputs. CMOS and TTL compatible. D0 is the LSB and D13 is the inverted MSB. Output coding is two's complement. (Pin 27) Data valid. The rising edge of this signal occurs when output data is valid and may be used to latch data into following circuitry. (Pin 21) Internal analog input common mode voltage reference. Nominally +3.25V. Can be used to establish the analog input common mode voltage for DC coupled applications (DC coupling not recommended, see applications section). (Pins 1 - 4, 8, 11, 12, 15, 19, 20, 23 - 26, 35, 36, 47, 48, and vias) circuit ground. (Pins 5 - 7, 16 - 18, 22, 46) +5V power supply. Bypass each group of supply pins to ground with a 0.01F capacitor. (Pins 37, 38) +3.3V to +5V power supply for the digital outputs. Establishes the high output level for the digital outputs. Bypass to ground with a 0.1F capacitor.
CLC5958
(MSB) D13 45 D12 44 D11 43 D10 42 D9 41 D8 40 D7 39 DVCC 38 DVCC 37 GND 36 GND 35 D6 34 D5 33
ENCODE, ENCODE
D0-D13
DAV
VCM
vias
D4 32 D3 31 D2 30 D1 29 (LSB) DO 28 DAV 27 GND 26 GND 25
GND VCC
DVCC
CLC5958 Block Diagram
AIN
T&H
Summing Network
Residue Amp
10-bit Fine ADC ENCODE 4-bit Flash 4-bit DAC
Over-range Correction Logic & Output Buffers
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CLC5958 Package Dimensions
7
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CLC5958 Application Information
Driving the Analog Inputs The differential analog inputs, AIN and AIN, are biased from an internal 3.25V reference (a 2.4V bandgap reference plus a diode) through an on-chip resistance of 500. This bias voltage is set for optimum performance, and varies with temperature. Since DC coupling the inputs overrides the internal common mode voltage, it is recommended that the inputs to the CLC5958 be AC coupled whenever possible. The time constant of the input coupling network must be greater than 1sec to minimize distortion due to nonlinear input bias currents. Additionally, the common mode source impedance should be less than 100 at the sample rate. If DC coupling is required, then the VCM output may be used to establish the input common mode voltage. The CLC5958 samples the common mode voltage at the internal track-and-hold output and servos the VCM output to establish the optimum common mode potential at the track-and-hold. It is possible to use the VCM output to construct an external servo loop. Figure 1 below illustrates one input coupling method. The transformer provides noiseless single-ended to differential conversion. The two 50 resistors in the secondary define the input impedance and provide a low common mode source impedance through the bypass capacitors.
0.1 AIN 0.1 VIN 1:1.4 50
25 ENCODE 0.1 D D Q Q VBB
100
0.1 AIN 39pf
VIN VIN 39pf
CLC5958
AIN 100 0.1
Figure 2: Differential Amplifier Driving the ENCODE Inputs The ENCODE and ENCODE inputs are differential clock inputs that are referenced to VCC. They may be driven with PECL input levels. Alternatively they may be driven with a differential input (e.g. a sine input) that is centered at 1.2 Volts below VCC and which meets the min and max ratings for VIL and VIH. Low noise differential clock signals provide the best SNR performance for the converter. The ENCODE inputs are not self biasing, so a DC bias current path must be provided to each of the inputs. Figure 3 shows one method of driving the encode inputs.
25 0.1 Clock 1:1 MC10EL16 ENCODE
CLC5958
CLC5958
332 332
0.01 50
0.1
Figure 3: ENCODE Inputs
AIN 0.1
Figure 1: Input Coupling Alternatively, the inputs can be driven using a differential amplifier as shown in Figure 2. The network of Figure 2 uses a simple RC low-pass filter to roll off the noise of the differential amplifier. The network has a cutoff frequency of 40MHz. Different noise filter designs are required for different applications. For example, an IF application would require a band-pass noise filter. The analog input lines should be routed close together so that any coupling from other sources is common mode.
The transformer converts the single-ended clock signal to a differential signal. The center-tap of the secondary is biased by the VBB potential of the ECL buffer. The diodes in the secondary limit the input swing to the buffer. Since the encode inputs are close to the analog inputs, it is recommended that the analog inputs be routed on the top of the board directly over a ground plane and that the encode lines be routed on the back of the board and then connected through via to the encode inputs. Latching the Output Data The rising edge of DAV is approximately centered in the data transition window, and may be used to latch the output data. The DAV output has twice the load driving capability of the data outputs so that two latch clock inputs may be driven by this output.
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Routing Output Data Lines It is recommended that the ground plane be removed under the data output lines to minimize the capacitive loading of these lines. In some systems this may not be permissible because of EMI considerations. Harmonics and Clock Spurious Harmonics are created by non-linearity in the track-andhold and the quantizer. Harmonics that arise from repetitive non-linearities in the quantizer may be reduced by the application of a dither signal. Transformers and baluns can contribute harmonic distortion, particularly at low frequencies where transformer operation relies on magnetic flux in the core. If a transformer is used to perform single-ended to differential conversion at the input, care should be taken in the selection of the transformer. The clock is internally divided by the CLC5958 in order to generate internal control signals. These divided clocks can contribute spurious energy, principally at fs/4 and fs/8. The clock spurious is typically less than -90dBFS. Calibration Sidebands The CLC5958 incorporates on-board calibration. The calibration process creates low level sideband spurious close to the carrier and near DC for some input frequencies. In most applications these sidebands will not be an issue. The sidebands add negligible power to the carrier and therefore do not reduce sensitivity in receiver applications. Also, the sidebands never fall in adjacent channels with any appreciable power. They may be visible in some very narrow-band applications, and so are documented here for completeness. The offset of the sidebands relative to the carrier and relative to DC is derived using the equations: 32 fin n = round fs f = fin - nfs 32
32 4.8671e 6 n = round =3 52e 6 f = 4.8671e
6
-
3 52e 32
6
= 7.9KHz
If the input is a full scale input, then the magnitude of the sidebands is derived as: x = 1024 7.9e 3 / 52e 6 = 0.489 a = 100e -6 sin ( .489 ) .489 = 96e -6 = - 80dBc
The sidebands roll off rapidly with increasing sideband offset. For example, if the sideband is offset 200KHz from the carrier (in an adjacent GSM channel) as opposed to the 7.9KHz offset from the previous example, the sideband magnitude is reduced to -116dBc. Figure 4 shows how the sideband offset frequency varies with input frequency at a sample rate of 52MSPS.
800 700 600
f (KHz)
500 400 300 200 100 0 0 5 10 15 20 25
Input Frequency (MHz)
Figure 4: Sideband Offset vs. Input Frequency The sideband magnitude is a function of the sideband offset, as illustrated in Figure 5.
-80
where f is the sideband offset, fin is the input
Sideband Magnitude (dBc)
frequency, fs is the sample rate, and round(*) denotes integer rounding. The magnitude of the sideband relative to the carrier for a full scale input tone is approximated by the equations: x = 1024 f / f s a = sin ( x ) x
-85 -90 -95 -100 -105 -110 -115 -120 0 100 200 300 400 500 600 700 800
where a is the sideband magnitude relative to the input, and is the calibration sideband coefficient. The value of rolls off 2dB per dB as the input amplitude is reduced. For example, assume the input frequency is 4.8671MHz and the sample rate is 52MSPS. Then the sideband offset is derived as follows:
f (KHz)
Figure 5: Sideband Magnitude vs. Sideband Offset
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Power Supplies The VCC pins supply power to all of the CLC5958 circuitry with the exception of the digital output buffers. The DVCC pins provide power to the digital output buffers. Each supply pin should be connected to a supply (i.e. do not leave any supply pins floating). Local groups of supply pins should be bypassed with.01uF capacitors. These capacitors should be placed as close to the part as possible. Avoid using via to the ground plane. If vias to the ground plane cannot be avoided, then use multiple vias in close proximity to the bypass capacitor. The supplies should be bypassed in a manner to prevent supply return currents from flowing near the analog inputs. The evaluation board layout is an example of how to accomplish this. The digital output buffer supplies (DVCC) provide a means for programming the output buffer high level. Supply values ranging from 3.3V to 5.0V may be applied to these pins. In general, best performance is achieved with DVCC set to 3.3V.
Layout Recommendations for the CSP The 48 lead chip scale package not only provides a small footprint, but also provides an excellent connection to ground. The thermal vias on the bottom of the package also serve as additional ground pads. The solder pad dimensions on the pc board should match the package pads 1:1. Soldering Recommendations for the CSP A 4 mil thick stencil for the solder screen printing is recommended. The suggested IR reflow profile is: Ramp Up: Dwell Time > 183C: Solder Temperature: (max solder temperature): Dwell Time @ Max Temp: Ramp Down: 2C/sec 75 sec 215C 235C 5 sec 2C/sec
CLC5958 Evaluation Board
Description The CLC5958 evaluation printed circuit board provides a convenient test bed for rapid evaluation of the CLC5958. It illustrates the proper approach to layout in order to achieve best performance, and provides a performance benchmark. Analog Input The CLC5958 evaluation board is configured to be driven by a single-ended signal at the AIN SMA connector (the AIN connector is disconnected). The AIN SMA connector should be driven from a 50 source impedance. A full scale input is approximately 1.4Vpp (7dBm). The single-ended input is converted to a differential input by an on-board transformer. When performing sine wave testing, it is critical that the input sine wave be filtered to remove harmonics and source noise. Encode Input The CLK SMA connector is the encode input and should also be driven from a 50 source. A low jitter 16dBm sine wave should be applied at this input. In some cases it may be necessary to band-pass filter the sine wave in order to achieve low jitter. The single-ended clock input is converted to a differential signal by an on-board transformer and buffered by an ECL buffer. Digital Outputs The digital outputs are available at the Eurocard connector (J1). Data bits D0 through D13 are available at J1 pins 18B through 5B. The data ready signal (labeled DR in the schematic) is available at J1 pin 20B. These outputs are also available at the HP 01650-63203 termination adapter for direct connection to an HP logic analyzer (see evaluation board schematic). The outputs are buffered by 3.3V digital latches. The falling edge of the data ready signal may be used to latch the output data. Supply Voltages Power is sourced to the board through the Eurocard connector. A 5V supply should be connected at J1 pins 32A and 32B. A 3.3V supply should be connected at J1 pins 31A and 31 B. The ground return for these supplies is at J1 pins 27A, 27B, 28A, and 28B. It is recommended that low noise linear supplies be used.
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CLC5958 Evaluation Board Layout
CLC5958PCASM Layer 1
CLC5958PCASM Layer 2
CLC5958PCASM Layer 3
CLC5958PCASM Layer 4
11
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CLC5958 Evaluation Board Schematic
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CLC5958 14-bit, 52MSPS A/D Converter
Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy National's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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