View NJU6674_993292.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJU6674
38-common x 132-segment+1-icon common Bitmap LCD Driver
GENERAL DESCRIPTION
The NJU6674 is a Bitmap LCD Driver to display graphics or characters. It contains 5,148 bits display data RAM, Microprocessor interface circuits, instruction decoder, 38-common and 132-segment +1-icon common drivers. The bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface. 39 x 132 dots graphics or 10-character 3-line by 12 x 13 dot character with icon are displayed by NJU6674 itself. The wide operating voltage from 2.4V to 3.3V and low operating current are suitable for small sized battery operated items.
PACKAGE
NJU6674CJ
FEATURES
Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM : 5,148-bit LCD Drivers : 132-seg, 38-com+1-icon com Bias select 1/5 bias or 1/6 bias Direct interface with 68 and 80 type MPU Serial interface (SI, SCL, A0, CS1B, CS2) Useful Instruction Set Display ON/OFF ,Display Start Line Set, Page Address Set, Column Address Set, Status Read, Display Data Write, Display Data Read, ADC Select, Inverse Display, Entire display ON/OFF, Bias Select, Read Modify Write, End, Reset, Power control set, Internal resistor ratio set, EVR Register Set, EVR Mode Set, Power saving Power Supply Circuits for LCD incorporated Step up circuit (x2, x3, x4), Regulator, Voltage Follower x4, V5 level is adjusted by internal bleeder resistancePrecision Electrical Variable Resistance (64-steps)
Bias Stabilization Capacitor less
Low power consumption Operating Voltage (All the voltages are based on VDD=0V.) * Logic Operating -2.4 to -3.3V * Voltage Booster Operating Voltage -2.4 to -3.3 V * LCD Driving voltage -5.0 to -10.0V Rectangle outlook for COG Package outline: Bump-chip C-MOS Technology (Substrate: N)
Ver.2003-04-08
-1-
NJU6674
PAD LOCATION
C37 COMS DUMMY38 C19 DUMMY32
ALI_A1 DUMMY1
ALI_B2
DUMMY15 CL VSS1 CS1B CS2 VDD RESB A0 VSS1 WRB(R/WB) RD(E) VDD D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) VDD VDD VDD VDD VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VOUT VOUT C3C3C1+ C1+ C1C1C2C2C2+ C2+ VSS1 VSS1 VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST VDD CLS VSS1 SEL68 P/S VDD DUMMY16 VSS1 IRS VDD DUMMY17 DUMMY25
S131 S130
Chip Center :X=0m,Y=0m Chip Size :X=10.38mm, Y= 2.51mm Chip Thickness :400m30m Bump Size :78.16m x 48.10m PAD Pitch :72m(Min) Bump Height :17.5m(Typ) Bump Material :Au Voltage Boosting Polarity :Negative Voltage(VDD common) Substrate :N
*
Alignment marks
110.34m
Y
X
70.38m ALI_B1, ALI_B2
70.38m
70.38m ALI_A1, ALI_A2 Note) Alignment Marks are not contains window.
S1 S0
ALI_A2
ALI_B1
DUMMY26 COMS C0
DUMMY31
C18
-2-
Ver.2003-04-08
NJU6674
PAD COORDINATES
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Terminal DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 CL VSS1 CS1B CS2 VDD RESB A0 VSS1 WRB RDB VDD D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) VDD VDD VDD VDD VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VOUT VOUT C3C3C1+ X= m -4949 -4877 -4805 -4733 -4661 -4589 -4517 -4445 -4373 -4301 -4229 -4157 -4085 -4013 -3941 -3869 -3797 -3725 -3653 -3581 -3509 -3437 -3365 -3293 -3221 -3149 -2879 -2599 -2319 -2039 -1759 -1479 -1199 -919 -710 -638 -566 -494 -422 -350 -278 -206 -134 -62 10 82 154 226 298 370 Chip Size 10.38x2.51mm(Chip Center X=0m, Y=0m) PAD No. Terminal Y= m X= m Y= m -1098 51 C1+ 442 -1098 -1098 52 C1514 -1098 -1098 53 C1586 -1098 -1098 54 C2658 -1098 -1098 55 C2730 -1098 -1098 56 C2+ 802 -1098 -1098 57 C2+ 874 -1098 -1098 58 VSS1 946 -1098 -1098 59 VSS1 1018 -1098 -1098 60 VRS 1090 -1098 -1098 61 VRS 1162 -1098 -1098 62 VDD 1234 -1098 -1098 63 VDD 1306 -1098 -1098 64 V1 1378 -1098 -1098 65 V1 1450 -1098 -1098 66 V2 1522 -1098 -1098 67 V2 1594 -1098 -1098 68 V3 1666 -1098 -1098 69 V3 1738 -1098 -1098 70 V4 1810 -1098 -1098 71 V4 1882 -1098 -1098 72 V5 1954 -1098 -1098 73 V5 2026 -1098 -1098 74 VR 2098 -1098 -1098 75 VR 2170 -1098 -1098 76 VDD 2242 -1098 -1098 77 VDD 2314 -1098 -1098 78 TEST 2386 -1098 -1098 79 VDD 2458 -1098 -1098 80 CLS 2530 -1098 -1098 81 VSS1 2602 -1098 -1098 82 SEL68 2674 -1098 -1098 83 P/S 2746 -1098 -1098 84 VDD 2818 -1098 -1098 85 DUMMY16 2890 -1098 -1098 86 VSS1 2962 -1098 -1098 87 IRS 3034 -1098 -1098 88 VDD 3106 -1098 -1098 89 DUMMY17 3178 -1098 -1098 90 DUMMY18 3250 -1098 -1098 91 DUMMY19 3322 -1098 -1098 92 DUMMY20 3394 -1098 -1098 93 DUMMY21 3466 -1098 -1098 94 DUMMY22 3538 -1098 -1098 95 DUMMY23 3610 -1098 -1098 96 DUMMY24 3682 -1098 -1098 97 DUMMY25 3754 -1098 -1098 98 ALI_A2 5036 -1098 -1098 99 C18 5036 -943 -1098 100 C17 5036 -871
Ver.2003-04-08
-3-
NJU6674
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Terminal C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 COMS DUMMY26 DUMMY27 DUMMY28 DUMMY29 DUMMY30 DUMMY31 ALI_B1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 X= m 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 5036 4716 4644 4572 4500 4428 4356 4284 4212 4140 4068 3996 3924 3852 3780 3708 3636 3564 3492 3420 3348 3276 3204 3132 3060 2988 Y= m -799 -727 -655 -583 -511 -439 -367 -295 -223 -151 -79 -7 65 137 209 281 353 425 569 641 713 785 857 929 1089 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Terminal S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 X= m 2916 2844 2772 2700 2628 2556 2484 2412 2340 2268 2196 2124 2052 1980 1908 1836 1764 1692 1620 1548 1476 1404 1332 1260 1188 1116 1044 972 900 828 756 684 612 540 468 396 324 252 180 108 36 -36 -108 -180 -252 -324 -396 -468 -540 -612 Y= m 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098
-4-
Ver.2003-04-08
NJU6674
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Terminal S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 X= m -684 -756 -828 -900 -972 -1044 -1116 -1188 -1260 -1332 -1404 -1476 -1548 -1620 -1692 -1764 -1836 -1908 -1980 -2052 -2124 -2196 -2268 -2340 -2412 -2484 -2556 -2628 -2700 -2772 -2844 -2916 -2988 -3060 -3132 -3204 -3276 -3348 -3420 -3492 -3564 -3636 -3708 -3780 -3852 -3924 -3996 -4068 -4140 -4212 Y= m 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 1098 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 Terminal S125 S126 S127 S128 S129 S130 S131 ALI_B2 DUMMY32 DUMMY33 DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY38 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 COMS ALI_A1 X= m -4284 -4356 -4428 -4500 -4572 -4644 -4716 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 -5036 Y= m 1098 1098 1098 1098 1098 1098 1098 1089 929 857 785 713 641 569 497 425 353 281 209 137 65 -7 -79 -151 -223 -295 -367 -439 -511 -583 -655 -727 -799 -871 -943 -1098
Ver.2003-04-08
-5-
NJU6674
BLOCK DIAGRAM
C0 VSS1 VDD V1 to V5 5 C1+ C1C2+ C2C3VOUT VSS2 VR VRS IRS Shift Register Shift Register Common Drivers Segment Drivers Common Drivers C O M S Common Timing Generator C18 S0 S131 C37 C19 COMS
Internal Power Circuits
Common Direction
Display Data Latch 132 bits Row Address Decoder Line Address Decoder
Display Data RAM 132 x 39 bits
Page Address Register
Column Address Decoder Display Timing Generator Column Address Counter 8bit Column Address Register 8bit Multiplexer Oscillator CLS CL
I/O Buffer
Status
Instruction Decoder Internal Bus
BF
Bus Holder
Initial Display Line
Line Counter
MPU Interface
Reset
CS1B CS2
A0 RDB WRB P/S (E) (R/WB)
SEL68
D0 to D5 D6(SCL) D7(SI)
RESB
-6-
Ver.2003-04-08
NJU6674
TERMINAL DESCRIPTION
No. 1 to 15 85 89 to 97 119 to 124 259 to 265 20,26, 35 to 38, 62 to 63, 76 to 77, 79,84,88 17,23, 39 to 41, 58 to 59, 81,86 42 to 45 60 to 61 64,65 66,67 68,69 70,71 72,73 Symbol DUMMY1 to DUMMY38 I/O Description Dummy Terminals. These are open terminals electrically.
VDD
Power
Power supply terminals.
VSS1
GND Ground terminal.
VSS2 VRS V1 V2 V3 V4 V5
Power
Reference voltage for voltage booster External reference voltage input terminal. Power LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not used, supply each level of LCD driving voltage from outside with following relation. VDDV1V2V3V4V5VOUT When the internal power supply is on, the internal circuits generate and supply following LCD bias voltage from V1 to V4 terminal. Bias V1 V2 V3 V4 I
1/5 Bias 1/6 Bias
V5+4/5 VLCD V5+5/6 VLCD
V5+3/5 VLCD V5+4/6 VLCD
V5+2/5 VLCD V5+2/6 VLCD
V5+1/5 VLCD V5+1/6 VLCD
50,51 52,53 56,57 54,55 48,49 46,47 74,75
C1+ C1C2+ C2C3VOUT VR
O
VLCD=VDD-V5 Boosted capacitor connecting terminals used for voltage booster.
O I
27 28 29 30 31 32 33 34 87
D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) IRS
I/O
Voltage booster output terminal. Connect the boosted capacitor between this terminal and VSS1. Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting between VDD and V5 terminal.(IRS="L") IRS terminal connect with "H" at the time of built-in resistance used. "H" , this terminal must connect to "H" or "L". P/S="H": Tri-state bi-directional Data I/O terminal in 8-bit parallel operation. P/S="L" : Serial data input terminal. (D7 ) Serial data clock signal input terminal. (D6 ) Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL. Internal resistor select terminal "H": Internal "L": External This terminal must connect to "H" or "L".
I
Ver.2003-04-08
-7-
NJU6674
No. 22 Symbol A0 I/O I Description Connect to the Address bus of MPU. The data on the D0 to D7 is distinguished between Display data and Instruction by status of A0. A0 H L Discrimination. Display Data Instruction Reset terminal. When the RESB terminal goes to "L", the initialization is performed. Reset operation is executing during "L" state of RESB. Chip select terminal. Data Input/Output are available during CS1B="L" and CS2="H". RDB signal of 80 type MPU input terminal. Active "L" During this signal is "L" , D0 to D7 terminals are output. Enable signal of 68 type MPU input terminal. Active "H" Connect to the 80 type MPU WRB signal. Active "L". The data on the data bus input synchronizing the rise edge of this signal. The read/write control signal of 68 type MPU input terminal. R/WB H L State Read Write MPU interface type selection terminal. This terminal must connect to VDD or VSS. SEL68 H State 68 Type
Chip Select
21
RESB
I
18 19 25
CS1B CS2 RDB(E)
I I
24
WRB(R/WB)
I
82
SEL68
I
L 80 Type
Read /Write
83
P/S
I
Serial or parallel interface selection terminal. P/S "H"
Data/Command
Data
Serial Clock
80
CLS
I
16
CL
I/O
A0 D0 to D7 RDB, CS1B, WRB CS2 A0 SI(D7) "L" SCL(D6) CS1B, CS2 RAM data and status read operation do not work in mode of the serial interface. In case of the serial interface (P/S="L"),RDB and WRB must be fixed "VDD" or " VSS", and D0 to D5 are high impedance. Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS="H" : Internal oscillator circuit is enable CLS="L" : Internal oscillator circuit is disabled (requires external input) When CLS="L", input the display clock through the CL terminal. Display clock input/output terminal. The following is true depending on the CLS status. CLS "H" "L" CL Output Input
-8-
Ver.2003-04-08
NJU6674
No. 117~99 266 to 284 Symbol C0 to C18 C19 to C37 I/O O O Description LCD driving signal output terminals. Common output terminals :C0 to C37 Segment output terminals :S0 to S131 * Common output terminal The following output voltages are selected by the combination of FR and status of common. Scan Data FR Output Voltage H H V5 L VDD H V1 L L V4 Power Save VDD * Segment output terminal The following output voltages are selected by the combination of FR and data in the RAM. Output Voltage RAM FR Data Normal Reverse H VDD V2 H L V5 V3 H V2 VDD L L V3 V5 Power Save VDD COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. Maker testing terminal. Used for maker test (No connections )
126 to 257
S0 to S131
O
118 285 78
COMS
O
TEST
I
Ver.2003-04-08
-9-
NJU6674
Functional description
(1) Block circuits description (1-1) Busy Flag (BF) During internal operation, the LSI is being busy and can't accept any instructions except "status read". The BF data is output through D7 terminal by the "status read" instruction. When the cycle time (tcyc) mentioned in the "AC characteristics" is satisfied, the BF check isn't required after each instruction, so that MPU processing performance can be improved. (1-2) Initial display line register The initial display line register assigns a DDRAM line address, which corresponds, to COM0 by "initial display line set" instruction. It is used for not only normal display but also vertical display scrolling and page switching without changing the contents of the DDRAM. th However, the 39 address for icon display can't be assigned for initial display line address. (1-3) Line counter The line counter provides a DDRAM line address. It initializes its contents at the switching of frame timing signal (FR), and also counts-up in synchronization with common timing signal. (1-4) Column address counter The column address counter is an 8-bit preset counter, which provides a DDRAM column address, and it is independent of below-mentioned page address register. It will increment (+1) the column address whenever "display data read" or "display data write" instructions are issued. However, the counter will be locked when no-existing address above (84)H are addressed. The count-lock will be able to be released by the "column address set" instruction again. The counter can invert the correspondence between the column address and segment driver direction by means of "ADC set" instruction. (1-5) Page address register The page address register provides a DDRAM page address. The page address "1 to 3" should be used the D0, D1, D2, D3, D4, D5 , D6, D7 are valid. The page address "4" should be used the only D0, D1, D2, D3, D4, D5 are valid. The last page address "5" should be used for icon display because the only D0 is valid. (1-6) Display data RAM (DDRAM) The DDRAM contains 5,148-bit, and stores display data, which are 1-to-1 correspondents to LCD panel pixels. When normal display mode, the display data "1" turns on and "0" turns off LCD pixels. When inverse display mode, "1" turns off and "0" turns on.
- 10 -
Ver.2003-04-08
NJU6674
Page Address
(D2,D1,D0)
Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0
D0=0 D0=1
Display Pattern
Line Address
Common Driver
0, 0, 0
Page 0
0, 0, 1
Page 1
0, 1, 0
Page 2
0, 1, 1
Page 3
1, 0, 0
Page 4
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 82 01 83 00
1, 0, 1
Column Address(ADC)
Page 5 00 01 02 03 04 05 83 82 81 80 7F 7E S1 S2 S3 S4 S5
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 COMM*
Segment Drivers S0
S130 S131
*: COMM is independent of the "Initial display line set" instruction and always corresponds to the 39th line. Fig.1 Display data RAM (DDRAM) Map
Ver.2003-04-08
- 11 -
NJU6674
(1-7) Common direction register The common direction register specifies common driver's scanning direction. Table 1. PAD No. Pin name Common direction "L" select(D3) "H" 117 C0 COM0 COM37 Common Drivers 99 284 C18 C37 COM18 COM37 COM19 COM0 266 C19 COM19 COM18
The duty ratio setting and output assignment register are so controlled to operate independently that duty ratio setting required to corresponding duty ratio for output assignment.
(1-8) Reset Circuit The reset circuit initializes the LSI to the following status by using of the reset signal into the RESB terminal. * Reset status using the RES terminal: 1. Display off 2. Normal Display (Non-inverse display) 3. ADC select : Normal mode (D0=0) 4. Power control register clear : D2, D1, D0="0, 0, 0" 5. Serial interface register clear 6. LCD bias select : D0="0"(1/6 bias) 7. Entire display off : D0="0" (Normal mode) 8. Read modify write off 9. Initial display line address : 00H 10. Column address : 00H 11. Page address : 0 page 12. Common direction register : Normal mode (D3=0) 13. V5 level is adjusted by external bleeder resistance : D2, D1, D0="1, 0, 0" 14. EVR mode off and EVR register : D5, D4, D3, D2, D1, D0="1, 0, 0, 0, 0, 0" The RESB terminal should be connected to MPU's reset terminal, and the reset operation should be executed at the same timing of the MPU reset. As described in the "DC characteristics", it is necessary to input 10us(min.) or over "L" level signal into the RESB terminal in order to carry out the reset operation. The LSI will return to normal operation after about 1.0us(max.) from the rising edge of the rest signal. In case of using external power supply for LCD driving voltage, the RESB terminal is required to be being "L" level when the external power supply is turned-on. The "Reset" instruction in Table.4 can't be substituted for the reset operation by using of the RESB terminal. It executes above-mentioned only 8 to 14 items.
- 12 -
Ver.2003-04-08
NJU6674
LCD driving circuits (a) Common and segment drivers LCD drivers consist of 38-common drivers, 132-segment divers and 1-icon-common driver. As shown in "LCD driving waveform", LCD driving waveforms are generated by the combination of display data, common timing signal and internal FR timing signal. (b) Display data latch circuit The display data latch circuit temporally stores 132-bit display data transferred from the DDRAM in the synchronization with the common timing signal, and then it transfers these stored data to the segment drivers. "Display on/off", "inverse display on/off" and "entire display on/off" instructions control only the contents of this latch circuit, they can't change the contents of the DDRAM. In addition, the LCD display isn't affected by the DDRAM accesses during its displaying because the data read-out timing from this latch circuit to the segment drivers is independent of accessing timing to the DDRAM. (c) Line counter and latch signal or latch Circuits The clock line counter and latch signal to the latch circuits are generated from the internal display clock (CL). The line address of display data RAM is renewed synchronizing with display clock (CL). 132bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the MPU. (d) Display timing generator The display timing generates the timing signal for the display system bay combination of the master clock CL and driving signal FR ( refer to Fig.2 ) The frame signal FR and LCD alternative signal generate LCD driving waveform on the two frame alternative driving method. (e) Common timing generation The common timing is generated by display clock CL (refer to Fig.2) 37 38 1 CL
(LSI internal signal)
2
3
4
56
78
36 37 38 1
2
3
4
56
7
FR VDD V1 V4 V5 VDD V1 V4 V5
C0
C1 RAM DATA Sn Fig.2 Waveform of Display Timing
VDD V2 V3 V5
Ver.2003-04-08
- 13 -
NJU6674
(f) Oscillator This is the low power consumption CR oscillator which provides the display clock and voltage converter timing clock. Either external or internal Oscillator can be selected by setting the CLS terminal to "L" or "H" as shown in below. CLS="L" : External Oscillator CLS="H" : Internal Oscillator When the internal oscillator is used, the CL terminal fixed to "H" or "L". When the external oscillator is used, the CL terminal into display clock. (g) Internal power circuits The internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step EVR and voltage followers. The optimum values of the external passive components for the internal power circuits, such as capacitors for V1 to V5 terminals and feed back resistors for VR terminal, depend on LCD panel size. Therefore, it is necessary to evaluate the actual LCD module with these external components in order to determine the optimum values. Each portion of the internal power circuits is controlled by "power control set" instruction as shown in Table.2. In addition, the combination of power supply circuits is described in Table.3. Table.2
Bits D2 D1 D0
Power control set
Portions Voltage converter Voltage regulator Voltage followers 1 :On 1 :On 1 :On Status 0: Off 0: Off 0: Off
Table.3
Power supply combinations
Status D2 1 0 0 0 D1 1 1 0 0 D0 1 1 1 0 Voltage converter On Off Off Off Voltage regulator On On Off Off Voltage followers On On On Off External voltage VSS2 VOUT, VSS2 VOUT, V5, VSS2 VOUT, V1 to V5 Capacitor terminals Use Open Open Open
Using all internal power circuits Using voltage regulator and Voltage followers Using voltage followers Using only external power supply
Note1) Capacitor input terminals: C1+, C1-, C2+, C2-, C3Note2) Do not use other combinations except examples in Table.3. Note3) Connect decoupling capacitors on V1 to V5 terminals whenever using the voltage followers.
- 14 -
Ver.2003-04-08
NJU6674
- Power Supply applications Power Control Instruction D2 : Boost Circuit D1 : Voltage Regulator D0 : Voltage Follower (1) Internal power supply Example. V5 level is adjusted by internal bleeder resistance (IRS="H") All of the Internal Booster, Voltage Regulator, Voltage Follower using. (D2,D1,D0) = (1,1,1) (2) Internal power supply Example. V5 level is adjusted by internal bleeder resistance (IRS="L") All of the Internal Booster, Voltage Regulator, Voltage Follower using. (D2,D1,D0) = (1,1,1)
VDD + V1 + V2 + V3 + V4 + V5 + VOUT VSS2 VDD
IRS + C1C1+ C3C2+ C2+ + + + +
VDD V1 V2 V3 V4 + V5 + VOUT VSS2 VDD
IRS C1C1+ C3C2+ C2+ +
VR
V5
VR
V5
*
:Bias capacitors are selected depending on the LCD panel. The evaluation in various display patterns should be experimented in the application.
Ver.2003-04-08
- 15 -
NJU6674
(3) Only VOUT Supply from outside Example. V5 level is adjusted by internal bleeder resistance (IRS="H") Internal Voltage Regulator, Voltage Follower using. (D2,D1,D0) = (0,1,1) (4) Only VOUT Supply from outside Example. V5 level is adjusted by internal bleeder resistance (IRS="L") Internal Voltage Regulator, Voltage Follower using. (D2,D1,D0) = (0,1,1)
VDD + + V2 + V3 + + V5 VOUT VSS2 VDD V4 V1
IRS + +
VDD V1 V2 + V3 + + V5 VOUT VSS2 VDD V4
IRS
VR
V5
VR
V5
(5) VOUT and V5 Supply from outside Example. Internal Voltage Follower using. (D2,D1,D0) = (0,0,1)
(6) External Power Supply Example. All of V1 to V5 and VOUT supply from outside (D2,D1,D0) = (0,0,0)
VDD + V1 + V2 + V3 + V4 V5 VOUT VSS2
VDD V1 V2 V3 V4 V5 VOUT VSS2
: These switches should be open during the power save mode. : *Bias capacitors are selected depending on the LCD panel. The evaluation in various display patterns should be experimented in the application.
- 16 -
Ver.2003-04-08
NJU6674
INSTRUCTION SET
The NJU6674 distinguishes the data on the data bus D7 to D0 as an instruction by combination of A0, RDB(E), WRB(R/W) signals. The decoding of the instruction and execution performs with only high speed internal timing without relation to the external clock. Therefore, no busy flag check required normally. In case of the serial interface, the data input as MSB(D7) first serially. Table.4 shows the instruction codes of the NJU6674.
Table.4
Instruction (a) Display ON/OFF (b) Initial display Line set A0 RDB WRB D7 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0(1) 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0
Instruction table
D4 0 D3 1 D2 1 D1 1 D0 0/1 Description LCD Display ON/OFF D0=0:OFF D0=1:ON Determine the Display Line of RAM to COM 0 Set the page of DD RAM to the Page Address Register Set the Higher order 4 bits Column Address to the Reg. Set the Lower order 4 bits Column Address to the Reg. Read out the internal Status Write the data into the Display Data RAM Read the data from the Display Data RAM Set the DD RAM vs Segment D0=0:Normal D0=1:Inverse Inverse the ON and OFF Display D0=0:Normal D0=1:Inverse Whole Display Turns ON D0=0:Normal D0=1: Whole Disp. ON Set the LCD bias ratio D0=0:1/6 D0=1:1/5 Increment the Column Address Register when writing but no-change when reading Release from the Read Modify write Mode Initialize the Internal Circuits Select common direction D3=0:Normal D3=1:Inverse Set the status of internal power Circuits Set the status of internal resistor ratio (Ra/Rb) Set EVR mode Set EVR register 1 0 1 0 * 1 0 1 1 0 * 0/1 Set the Power Save Mode (LCD Display OFF)
Instruction Code D6 D5 0 1 0 0 0 1 0 0 1 1 0 1
Start address * Page Address
(c) Page address set Column address set (Upper 4-bit) (d) Column address set (Lower 4-bit) (e) Status read (f) Display data write (g) Display data read (h) ADC select Inverse display On/Off Entire display On/Off (j) (i) LCD bias select Read modify write (l)
Higher Order Culomn Address Lower Order Culomn Address 0 0 0 0
Status
Write Data Read Data 1 1 0 0 0 0 0 1 0 1 0/1 0/1
0
1
0
1
0
1
0
0
1
0
0/1
(k)
0
1
0
1
0
1
0
0
0
1
0/1
0
1
0
1
1
1
0
0
0
0
0
(m) End (n) Reset Common direction (o) select (p) (q) (r) (s) (t) Power control set Internal resistor ratio set EVR mode set EVR register set Pawer save mode On/Off
0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 1 * 1 1 1 1 * 1
1 1 1 0 0 0 * 0 0 1 0 * 0
1 1 0 1 1 0
0 0 0 0 0 0
1 0 0/1 1 0 0
1 0 * D2 D2 0
1 1 * D1 D1 0
0 0 * D0 D0 1
Setting Data 1 1 1 1 * 1 0 0 0 0 * 0 1 0 0 1 * 1 1 1 0 1 * 1
(u) NOP Reserve (v) (Inhibited) (w) Test
Inhibited command Inhibited command (*Don't Care)
Ver.2003-04-08
- 17 -
NJU6674
(2) Instruction description (a) Display On/Off The "Display ON/OFF" instruction is used to control the display ON or OFF without changing the display data in the DDRAM. All of the COM terminals at the time of "Display OFF" and SEG terminals are set to VDD level. A0 0 D RDB 1 WRB 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D
0: Display Off 1: Display On
(b) Initial display line set This instruction specifies the DDRAM line address which corresponds to the COM0 position. By means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth display scrolling will be enabled. A0 0 A5 0 0 : : 1 RDB 1 A4 0 0 : : 0 WRB 0 A3 0 0 : : 0 D7 0 A2 0 0 : : 1 D6 1 A1 0 0 : : 0 D5 A5 A0 0 1 : : 1 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
Line address (HEX) 00 01 : : 25
(c) Page address set In order to access to the DDRAM for writing or reading display data, both "page address set" and "column address set" instructions are required before accessing. The last page address "5" should be used for icon display because the only D0 is valid. A0 0 A2 0 0 0 0 1 1 RDB 1 WRB 0 A1 0 0 1 1 0 0 D7 1 A0 0 1 0 1 0 1 D6 0 D5 1 D4 1 Page 0 1 2 3 4 5 D3 * D2 A2 D1 A1 D0 A0
(*: Don't Care)
- 18 -
Ver.2003-04-08
NJU6674
(d) Column address set As above-mentioned, in order to access to the DDRAM for writing or reading display data, it is necessary to execute both "page address set" and "column address set" before accessing. The 8-bit column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column address register. Once the column address is set, it will automatically increment (+1) whenever the DDRAM will be accessed, so that the DDRAM will be able to be continuously accessed without "column address set" instruction. The column address will stop increment and the page address will not be changed when the last address (83)H is addressed. A0 0 0 A7 0 0 : : 1 (e) Status read This instruction reads out the internal status regarding "busy flag", "ADC select", "display on/off" and "reset". A0 0 RDB 0 WRB D7 BUSY 1 D6 D5 D4 ADC ON/OFF RESET D3 0 D2 0 D1 0 D0 0 RDB 1 1 A6 0 0 : : 0 A5 0 0 : : 0 WRB 0 0 A4 0 0 : : 0 D7 0 0 A3 0 0 : : 0 D6 0 0 A2 0 0 : : 0 D5 0 0 A1 0 0 : : 1 D4 1 0 A0 0 1 : : 1 D3 A7 A3 D2 A6 A2 D1 A5 A1 D0 A4 A0
Upper 4-bit Lower 4-bit
Column address (HEX) 00 01 : : 83
BUSY: When D7 is "1", the LSI is being busy and can't accept any instructions. ADC: It shows the correspondence between the column address and segment drivers. When D6 is "0", the column address (131-n) corresponds to segment driver n. When D6 is "1", the column address (n) corresponds to segment driver n. Please be careful that read out data is opposite of "ADC select" instruction data. ON/OFF: It shows display on or off status. When D5 is "0", the LSI is in display-on status. When D5 is "1", the LSI is in display-off status. Please be careful that read out data is opposite of "Display On/Off" instruction data. RESET: It shows reset status. When D4 is "0", the LSI is in normal operation. When D4 is "1", the LSI is during reset operation. (f) Display data write This instruction writes display data into the selected column address on the DDRAM. The column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without "column address set" instruction. A0 1 RDB 1 WRB 0 D7 D6 D5 D4 D3 Write Data D2 D1 D0
Ver.2003-04-08
- 19 -
NJU6674
(g) Display data read This instruction reads out the display data stored in the selected column address on the DDRAM. The column address automatically increments (+1) whenever the display data is read out by this instruction, so that this instruction can be continuously issued without "column address set" instruction. After the "column address set" instruction, a dummy read will be required, please refer to the (4-5). In case of using serial interface mode, this instruction can't be used. A0 1 (h) ADC select This instruction selects segment driver direction. The correspondence between the column address and segment driver direction is shown in Fig.1. Segment Driver Output order is inverse, when this instruction executes, therefore, the placement NJU6674 against the LCD panel becomes easy. A0 0 D RDB 1 WRB 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D RDB 0 WRB 1 D7 D6 D5 D4 D3 Read Data D2 D1 D0
0: Clokwise Output(Normal) 1: Counterclockwise Output(Inverse)
(i) Inverse display On/Off This instruction inverses the status of turn-on or turn-off of entire LCD pixels. It doesn't change the contents of the DDRAM. A0 0 D RDB 1 WRB 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D
0: Normal 1: Inverse
RAM data "1" correspond to "On" RAM data "0" correspond to "On"
(j) Entire display On/Off This instruction turns on entire LCD pixels regardless the contents of the DDRAM. It doesn't change the contents of DDRAM. This instruction executed prior to the "Normal or Inverse display On/Off Set" Instruction. A0 0 D RDB 1 WRB 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D
0: Normal Display 1: Whole Display turns On
When the "Entire display On" instruction is executed at Display Off states, the NJU6674 operates in Power Save Mode. (Refer "Power Save Mode") (k) LCD bias set This instruction selects LCD bias value. A0 0 D RDB 1 WRB 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 D
0: 1/6 bias 1: 1/5 bias
- 20 -
Ver.2003-04-08
NJU6674
(l) Read modify write This instruction sets the Read Modify Write controlling the Column Address increment. In this mode, Column Address only increments when execute the display data "Write" instruction; but no change when the display data "Read" Instruction. This states is continued until the End instruction(m) execution. When the End instruction is executed, the Column Address goes back to the start address before the execution of this "Read Modify Write" instruction. This function reduces the load of MPU for repeating display data change of the fixed area. A0 0 *) RDB 1 WRB 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
In this "Read Modify Write" mode, out of display data "Read"/"Write", any instructions except "Column Address Set" can be executed.
The sequence of cursor blink display
Page Address Set Column Address Set Read Modify Write Dummy Read Data Read Data inverse by MPU Data Write Dummy Read Data Read Data Write Dummy Read Data Read Data Write Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase Start the Read Modify Write Set to the Start Address of Cursor Display(*)
The data is ignored Column Counter doesn't increase
End
End the Read Modify Write
No
Finish? Yes Column Address goes back to the start address.(*)
Ver.2003-04-08
- 21 -
NJU6674
(m) End The "end" instruction cancels the read modify write mode and makes the column address return to the initial value just before "read modify write" is started. A0 RDB WRB D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Return Column Address (n) Reset N N+1 N+2 N+3 N+m N End
Read modify write
This instruction reset the LSI to the following status, however it doesn't change the contents of the DDRAM. Please be careful that it can't be substituted for the reset operation by using of the RESB terminal. Reset status by "reset" instruction: 1: Read modify write off 2: Initial display line address : (00)H 3: Column address : (00)H 4: Page address : (0) page 5: Common direction register : Normal mode (D3="0") 6: V5 level is adjusted by external bleeder resistance (D2, D1, D0="1, 0, 0") 7: EVR register : (D5, D4, D3, D2, D1, D0="1, 0, 0, 0, 0, 0") A0 0 RDB 1 WRB 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
(o) Common driver direction select This instruction selects common driver direction. Please refer to (1-7) common driver direction for more detail. D6 D5 D4 D3 A0 RDB WRB D7 0 1 0 1 1 0 0 D3 D3 0: Normal (C0 C37) 1: Inverse (C37 C0)
D2 *
D1 *
D0 *
(*: Don't Care)
- 22 -
Ver.2003-04-08
NJU6674
(p) Power control set This instruction controls the status of internal power circuits. Please refer to the (1-9) LCD Driving Circuits (g) internal power circuits for more detail. A0 RDB WRB D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 D2 D1 D0 D2 0: Voltage converter off 1: Voltage converter on D1 0: Voltage regulator off 1: Voltage regulator on D0 0: Voltage followers off 1: Voltage followers on Note) The internal power supply must be Off when external power supply using. * The wait time depends on the C4 to C8, COUT capacitors, and VDD and V5 Voltage. Therefore it requires the actual evaluation using the LCD module to get the correct time. LCD Driving power supply ON/OFF sequences. The sequences below are required when the power supply turns ON/OFF. For the power supply turning on operation after the power-save mode(p), refer the "power save release" mentioned after. Turn ON seaquence Turn OFF seaquence
E.V.R Register set
Display OFF Entire Display ON
Internal resister ratio set
Power control OFF or Power control ON or Ext. Power Supply ON (wait time *1) (wait time *1) Display OFF Display ON NJU6674 Power OFF Ext. Power Supply OFF
(1)
The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly, test by using the actual LCD module. refer to (3-5) "LCD Driving Voltage Generation Circuits".
Ver.2003-04-08
- 23 -
NJU6674
(q) Internal resistor ratio set The "Internal resistor ratio set" instruction is used to determine the internal resistor ratio for the voltage regulator. A0 0 D2 0 0 0 0 1 1 1 1 RDB 1 D1 0 0 1 1 0 0 1 1 WRB 0 D0 0 1 0 1 0 1 0 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 A2 D1 A1 D0 A0
Internal resistor ratio(1+Rb/Ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4
Internal resistor ratio(1+Rb/Ra) Minimum : : : : : : Maximum
(r),(s) EVR set (r) EVR mode set This instruction sets the LSI into the EVR mode, and it is always used by the combination with "EVR register set". The LSI can't accept any instructions except the "EVR register set" during the EVR set mode. This mode will be released after the "EVR register set" instruction. A0 0 RDB 1 WRB 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
(s) EVR register set This instruction sets 6-bit data into the EVR register to determine the output voltage "V5" of the internal voltage regulator. A0 0 RDB 1 WRB 0 D7 * D6 * D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 (*: Don't Care)
D5 D4 D3 D2 D1 D0 V5 Minimum 0 0 0 0 0 0 : 1 0 0 0 0 0 : : : : : : : : : : : : : : Maximum 1 1 1 1 1 1 When EVR doesn't use, set the EVR register to D5, D4, D3, D2, D1, D0 = "1, 0, 0, 0, 0, 0".
- 24 -
Ver.2003-04-08
NJU6674
(t) Power Save(complex command) When Entire Display ON at the Display OFF states(inverse order also same), the internal cirsuits goes to the Power Save Mode and the operating curent is dramatically reduced, almost same as the standby current. The internal states in the Power Save Mode is shown as follows; 1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation. 2: LCD driving is stopped. Segment and Common drives output VDD level Voltage. 3: The display data and the internal operating condition are remained and kept as just before enter the Power Save Mode. 4: All the LCD driving bias voltage(V1 to V5) is fixed to the VDD level. The power save and its release perform according to the following sequences. Power Save Sequence *1 Power Save Releace Sequence *2
Display OFF Entire Display ON
Entire Display OFF (Wait Time) *3 Display ON *4
*1: In the Power save sequence, the Power Save Mode starts after the Entire Display ON command is executed. *2: In the Power save Release sequence, Power Save Mode releases just after the Entire Display OFF instruction. The Display ON instruction is allowed to execute at any time after the Entire Display OFF instruction is completed. *3: The Internal Power Supply rise time depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capactor of Booster, and External Capacitor connected to V1 to V5. To Know the rise time correctly, test by using the actual LCDmodule. *4: LCD Driving waveform is output after the exection of the Display ON instruction execution. *5: In case of the external power supply operation, the external power supply should be turned off before the Power Save Mode and connected to the VDD for fixing the voltage. In this time, VOUT terminal also shold be made condition like as connection to VSS. (u) NOP This instruction is Non Operation Instruction.
(v) Reserve, (w) Test This instruction is used only for manufacturer's tests. (Don't Inhibited command)
Ver.2003-04-08
- 25 -
NJU6674
(3) Internal Power Supply (3-1) Voltage converter The voltage converter generates maximum 4x boosted negative-voltage from the voltage between VDD and VSS2. The boosted voltage is output from the VOUT terminal. The internal oscillator is required to be operating when using this converter, because the divided signal provided from the oscillator is used for the internal timing of this circuit. The boosted voltage between VDD and VOUT must not exceed 10.0V. The voltage converter requires external capacitors for boosting as shown in below. The boosted voltage and VDD, VSS2 VDD=+3V VSS2=0V VOUT=-3V VOUT=-6V VOUT=-7.5V 2x boost 3x boost 4x boost VDD=+2.5V
Example for connecting the capacitors 4x boost 3x boost VSS2 C1C1+ C3C2+ C2VOUT VSS2 C1C1+ + + C3C2+ + C2VOUT + + +
2x boost VSS2 C1C1
+
+ +
C3C2+ C2-
VOUT
- 26 -
Ver.2003-04-08
NJU6674
(3-2) Contrast Adjustment by the EVR function The EVR selects the VREG voltage out of following 64 conditions by setting 6-bit data into the EVR register. When the EVR function, VEV (refer:Fig-3-a Voltage Adjust Circuit) is controlled, and the LCD display contrast is adjusted. The EVR controls the voltage of VEV bay instruction and change the voltage of V5. A step with EVR is set like table shown below. n 63 62 61 : : : 2 1 0 EVR register (0,0,0,0,0,0) (0,0,0,0,0,1) (0,0,0,0,1,0) : : : (1,1,1,1,0,1) (1,1,1,1,1,0) (1,1,1,1,1,1) VEV [V] (99/162)VREG (100/162)VREG (101/162)VREG : : : (160/162)VREG (161/162)VREG (162/162)VREG VLCD Minimum : : : : : : : Maximum
00H 01H 02H : : : 3DH 3EH 3FH
*1: VLCD=VDD-V5 *2 : In use of the EVR function, the voltage adjustment circuit must turn on by the power control instruction. (3-3) Setting for internal resistor ratio Either external or internal feedback resistors can be selected by setting the IRS terminal to "0" or"1". The Internal resistor ratio selects 8 conditions of the feedback resistor ratio(1+Rb/Ra).The feed back resistor ratio(1+Rb/Ra) changing 3-bit data into the Internal resistor ratio register. IRS 0 1 Ra, Rb External resistors Internal resistors (Reference) (1+Rb/Ra) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4
Internal resistor ratio register: D2 D1 D0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Ver.2003-04-08
- 27 -
NJU6674
(3-4) Voltage Adjust Circuit The boosted voltage of VOUT outputs V5 for VLCD driving through the voltage adjust circuit. This circuit is composed of high the VRS, 64-level EVR and internal feedback resistor. (a) Using Internal Resistor Ratio function (IRS="1") The LCD driving volatge V5 is determined in accordance with the setting for the EVR and the internal resistor ratio Instruction. The output voltage of V5 adjusted by changing with in the V5>VOUT. The output voltage is caluculated by the following formula. V5=(1+Rb/Ra)VEV=(1+(Rb/Ra))(n/162)VREG VREG : External Constant voltage (VRS) n : EVR value (EVR) VDD VREG VRS VDD VEV V5 Ra Rb Fig-3-a Voltage Adjust Circuit (a-1)
- 28 -
Ver.2003-04-08
NJU6674
(b) Using external Ra and Rb resistors In case that the external feedback resistors (Ra, Rb) are used by setting the IRS terminal to "0", these external resistors are required to be placed between the VDD and VR and between the VR and V5 terminals. The LCD driving voltage V5 is determined in accordance with the setting for the EVR and the external resistor ratio. The output voltage of V5 adjusted by changing the Ra and Rb within the V5>VOUT. The output voltage is caluculated by the following formula. V5=(1+(Rb'/Ra'))VEV=(1+(Rb'/Ra'))(1-(n/162))VREG VDD VREG VRS V5 VDD Ra' VR Rb' Fig-3-b Voltage Adjust Circuit < Designe example for R1 and R2 / Reference > Condition : Ta=25C, n=31, VREG=-2.1V, EVR=1FH , V5=(1+(Rb/Ra))(n/162)VREG -7=(1+(Rb'/Ra'))(1-(31/162) (-2.1) (b-2) (EVR) VEV (b-1)
Determined by the current flown between VDD-V5 / 5uA. Ra'+Rb'=1.4M (b-3) Ra and Rb caluculated by above conditions and the formula of (b-2, b-3) to mentioned below; Rb'/Ra'=3.12 Ra=340k Rb=1060k The adjustable V5 range and step voltage table shown below. V5
Adjustable Range
Min. -8.6 (63 Step)
Step Voltage
Typ. -7.0 (32 Step) 52
Max. -5.3(0 Step)
UNIT [V] [mV]
Ver.2003-04-08
- 29 -
NJU6674
(3-5) LCD Driving Voltage Generation Circuits The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the V5 voltage with the internal bleeder resistance and is supplied to the LCD driving circuits after the impedence conversion by the voltage follower. The external capacitors to V1 to V5 for Bias voltage stabilization may be removed in use of small size LCD panel. The equivalent load of LCD panel may be changed depending on display patterns. Therefore, it require display quality check on various display patterns actually without external capacitors. If the display quality is not so good, external capacitors should connects as show in Fig. 4. (If no need external capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.)
Using the internal Power Supply
Using the external Power Supply
VSS2 VSS1 COUT C1 + C3 VOUT C3C1+ C1+ C2 C2+ C2R3 R2 VDD R1 + + + + + VDD C4 C5 C6 C7 C8 V1 V2 V3 V4 V5 VRS VSS1 V5 VR
IRS
VSS1 VSS2 VOUT C3C1+ C1C2+ C2VDD or VSS1 VDD VDD V5 VR
IRS
External Voltage Generator
V1 V2 V3 V4 V5 VRS
Fig.4 . Reference set up value VLCD=VDD-V5=5.0 to 9.0V . 1 Short wiring or sealed wiring to the VR terminal is required due to COUT 1.0F the high impedance of VR terminal. C1, C2, C3 1.0F 2 Following connection of VOUT is required when external power supply using. C4 to C7 0.1 to 0.47 F When VSS>V5, VOUT=V5 R1 264k When VSSV5, VOUT=VSS R2 211k 3 Bias capacitors are selected depending on the LCD panel. R3 925k The evaluation in various display patterns should be experimented in the application
- 30 -
Ver.2003-04-08
NJU6674
(4) MPU Interface (4-1) Interface type selection NJU6674 interfaces with MPU by 8-bit bi-directional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 5. In case of the serial interface, status and RAM data read out operation is impossible. P/S H L I/F type Parallel Serial CS1B CS1B CS1B CS2 CS2 CS2 A0 A0 A0 Table 5 RDB WRB SEL68 RDB WRB SEL68 "Hi-Z" mark: Hi-impedance D7 D6 D5 - D0 D7 D6 D5 - D0 SI SCL Hi-Z "-" mark: Fix to "H"or "L"
(4-2) Parallel Interface The NJU6674 interfaces the 68- or 80-type MPU directly if the parallel interface (P/S="H" is selected. The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to "H" or "L" as shown in table 6. Table 6 SEL68 H L Type 68-type MPU 80-type MPU CS1B CS1B CS1B CS2 CS2 CS2 A0 A0 A0 RDB E RDB WRB R/WB WRB D7 - D0 D7 - D0 D7 - D0
(4-3) Discrimination of Data Bus Signal The NJU6674 discriminates the mean of signal on the data bus by the combination of A0, E, R/WB, and (RDB, WRB) signals as shown in Table 7. Table 7 80 type Function RDB WRB L H Read Display Data H L Write Display Data L H Status Read H L Write into the Register(Instruction)
common A0 H H L L
68 type R/WB H L H L
Ver.2003-04-08
- 31 -
NJU6674
(4-4) Serial Interface.(P/S="L") The serial interface of the NJU6674 consists of the 8-bit shift register and 3-bit counter. In case the chip is selected (CS1B="L", CS2="H"), the input to D7(SI) and D6(SCL) becomes available, and in case that the chip isn't selected, the shift register and the counter are reset to the initial condition. The data input from the terminal(SI) is MSB first like as the order of D7, D6,------ D0, by a serial interface, it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 8-bit with the rise edge of 8th serial clock and processed. It discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (8 X n)th of serial clock (SCL), it is recognized display data by A0="H" and instruction by A0="L" A0 input is read in the rise edge of (8 X n)th of serial clock (SCL) after chip select and distinguished. However,in case of RESB="H" to "L" or CS1B="L" to "H" and CS2="H" to "L" with trasfered data does not fill 8 bit, attention is necessary because it will processed as there was command input. Always, input the data of (8 X n) style. The SCL signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it.
CS1B, CS2 SI SCL 1 A0 2 3 4 7 8 9 10 D7 D6 D5 D4 D1 D0 D7 D6
Fig.5
- 32 -
Ver.2003-04-08
NJU6674
(4-5) Access to the Display Data RAM and Internal Register. The NJU6674 transfers data to the MPU through the bus holder with the internal data bus. In case of reading out the display data contents in the DD RAM, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data write cycle. Therefore, the limitation of the access to NJU6674 from MPU side is not access time (tACC, tDS) of Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the MPU becomes possible. In case of cycle time isn't met, the MPU inserts NOP operation only and becomes an equivalent to an execution of wait operation on the satisfy condition in MPU. When setting an address, the data of the specified address isn't output immediately by the read operation after setting an address, and the data of the specified address is output at the 2nd data read operation. Therefore, the dummy read is always necessary once after the address set and the write cycle. (See Fig. 6) The example of Read Modify Write operation is mentioned in (3)Instruction -l)The sequence of Inverse Display. Write Operation MPU WRB DATA Internal timing Read Operation Bus holder WRB N
N
N+1 N+1
N+2 N+2
N+3 N+3
MPU
WRB RDB DATA WRB RDB Column address Bus holder
N N N+1 N+2
N
Address set N
N
Dummy read
n
Data read n
n+1
Data read n+1
Internal timing
n
n+1
n+2
Fig.6 (4-6) Chip Select CS1B, CS2 is Chip Select terminal. In case of CS1B="L" and CS2="H". the interface with MPU is available. In case of CS1B="H" or CS2="L", the D0 to D7 are high impedance and A0, RDB, WRB, SI and SCL inputs are ignored. If the serial interface is selected when CS1B="H" or CS2="L" the shift register and counter are reset. However, the reset is always operated in any conditions of CS1B, CS2.
Ver.2003-04-08
- 33 -
NJU6674
ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage(1) Supply Voltage(2) Supply Voltage(3) Supply Voltage(4) Supply Voltage(5) Input Voltage Operating Temperature Strage temperature SYMBOL VDD VSS2 V5, VOUT V1,V2,V3,V4 VRS VIN Topr Tstg RATINGS -0.3 to +7.0 -0.3 to +3.6(Used Tripler) -7.0 to +0.3 -3.6 to +0.3(Used Tripler) VDD-11.0 to VDD+0.3 V5 to VDD+0.3 -7.0 to +0.3 -0.3 to VDD+0.3 -40 to +85 -55 to +125 UNIT V V V V V V C C
VDD VSS
VDD
V5 Note 1) All voltage values are specified as VSS1=0V. Note 2) The relation of VDD>V1>V2>V3>V4>V5>VOUT; VDD>VSS1>VOUT must be maintained. In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to NJU6674 at the mean time of turning on VDD power supply or after turned on VDD. In use of the voltage boost circuit, the condition that the supply voltage: 11.0V> VDD -VOUT is necessary. Note 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the erectric characteristics conditions will cause malfunction and poor reliability. Note 4) Decoupling capacitor should be connected between VDD and VSS1 due to the stabilized operation for the voltage converter.
- 34 -
Ver.2003-04-08
NJU6674
DC Electrical Characteristics
PARAMETER Operating voltage (1) Operating voltage (2)
Recommend SYMBOL
VDD VSS V5 V1,V2 V3,V4 VIHC VILC VOHC VOLC ILI ILO RON IDDQ CIN fOSC tR tRW
Operating Available voltage(3) Available Available
"H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage
Input Leagage Current Driver On-resistance Stand-by Current Input Terminal Capacitance Oscillation Frequency Reset Time Reset "L" level pulse Width
(VDD=2.4V to 3.3V, VSS=0V, Ta=-20 to 75C) UNIT NOTE MIN TYP MAX 2.4 3.3 V 1 VDD-3.3 VDD-2.4 V VDD-10.0 VDD-5.0 VDD-10.0 V VDD-0.4xV5 VDD VLCD=VDD-V5 V5 VDD-0.6xV5 A0, D0 to D7, RDB, WRB, RESB, 0.8 x VDD VDD V CS1B, CS2, P/S, SEL68 Terminal 0.2 x VDD VSS D0 to D7 IOH=-0.5mA 0.8 x VDD VDD V Terminal IOL= 0.5mA VSS 0.2 x VDD All input terminals -1.0 1.0 A D0 to D7 terminals, Hi-Z state -3.0 3.0 Ta=25C, VLCD=8.0V 3.0 4.5 2 k CONDITIONS During Power Save Mode Ta=25C VDD= 3.0V Ta =25C RESB terminal 10.2 1.0 10.0 2.4 2.4 VDD-5.0 -10.0 1600 VDD-10.0V VDD-10.0V 0.01 10.0 12.5 14.8 5.0 A pF kHz s s V V V V V % A A A 10 9 8 3 4 5 6 7
driving voltage Voltage Follower Int. resistor ratio
VDD1 3-times boost VDD2 4-times boost VRS Output voltage VOUT1 4-times boost, VDD=2.5V 3-times boost, On-resistance RTRI VDD=3.0V, COUT=1.0F Adjustment range LCD Voltage boost operation off V
Input voltage
OUT2
3.3 2.5 VDD-2.4 -9.5 2600 VDD-5.0V VDD-5.0V 3.0 0.01 51 12 5 85 20
Operating Current
Ver.2003-04-08
Voltage booster
Voltage adjustment circuit "OFF" VDD=3.0V, VRS=VDD-2.4V, INTR EVR=00H,VOUT=VDD-10.0V V5=No load ;Ta =25C V5 IDDQ1 IOUT1 IOUT2 Power save mode VDD=3.0V, VLCD=5V, No access Com/Seg terminals non connect Display Checkerd pattern
Note 1) Although the NJU6674 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with MPU. Note 2) RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals (V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of Operating Voltage(2). Note 3) Apply no access from MPU. Note 4) Apply A0, D0 to D7, RDB, WRB, CS1B, CS2, RESB, P/S, CL terminals. Note 5) tR ( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RESB signal. Note 6) Apply minimum pulse width of the RESB signal. To reset, the "L" pulse over tRW shall be input. Note 7) Apply to the VDD when using 4-times boost. Note 8) The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage. 1 Note 9) INTR : The calculation of (VLCD(Ideal)* -(VLCD(Real))/VLCD(Ideal)) x100% 1 * VLCD(Ideal)=Nx(1-63/162)x2.4 (N:Selected by the "Internal resistor ratio" )
- 35 -
NJU6674
Note10) Each operating current shall be defined as being measured in the following condition. Power Control Operating Condition External Voltage Symbol Supply D2 D1 D0 Voltage Voltage Voltage (Input terminal) converter regulator Follower IDD1 1 1 1 Validity Validity Validity Use(VSS2) IDD2 0 0 0 Invalidity Invalidity Invalidity Use(VOUT, V1 to V5)
:IDD1 1M 500k 1.6M
VDD
VDD or VSS VDD-3V
VDD A 3V VSS1
VR NJU6674 VSS2 C1+
+
V5 C1- C3- C2+
+
IR
CLS
CL VR VOUT
C21.0F
1.0F
+
1.0F
:IDD2 VDD 10k VDD VR V1 C1+ V2 V3 V4 C2V5 C310k 10k 10k 10k VDD
VDD A 3V
CLS VOUT
CL
VSS1 VSS2
NJU6674 C1- C2+
-5V
Fig.7 MEASURMENT BLOCK DIAGRAM
- 36 -
Ver.2003-04-08
NJU6674
BUS TIMING CHARACTERISTICS
*
Read and Write characteristics (80 type MPU)
tCYC8
A0, CS1B, CS2 tr tAW8 WRB, RDB tCCL tDH8 tDS8 D0 to D7
(WRITE)
tf tAH8 tCCH
tACC8 D0 to D7
(READ)
tOH8
Parameter Address hold time Address set up time System cycle time Control "L" pulse width (Write) Control "L" pulse width (Read) Control "H" pulse width Data set up time Data set up time RD access time Output disable time Input signal rising, falling edge
Terminal
Symbol
Condition
tAH8 tAW8 tCYC8 tCCL(W) tCCL(R) tCCH tDS8 tDH8 tACC8 tOH8 tr, tf
A0, CS1B, CS2 WRB, RDB
D0 to D7 CL=100pF CS1B, CS2, WRB, RDB A0, D0 to D7
(VDD=2.7V to 3.3V, Ta=-20 to 75C) Min. Max. Unit TYP 0 0 300 60 120 60 40 ns 25 140 10 100 15
*
*:All timing based on 20% and 80% of VDD voltage level.
Ver.2003-04-08
- 37 -
NJU6674
Read and Write characteristics (68 type MPU)
tCYC6 E tr tEWH R/WB tAW6 A0, CS1B, CS2 tDH6 tAH6 tf tEWL
tDS6 D0~D7 (WRITE) tACC6 D0~D7 (READ) tOH6
Parameter Address hold time Address set up time System cycle time Enable "H" pulse WRITE width (Read) READ Enable "L" pulse WRITE width (Read) READ Data set up time Data hold time RD access time Output disable time Input signal rising, falling edge
Symbol
Terminal
Condition
(VDD=2.7V to 3.3V, Ta=-20 to 75C) Unit MIN TYP MAX 0 0 300 120 60 60 60 40 25
tAH6 tAW6 tCYC6 tEWH tEWL tDS6 tDH6 tACC6 tOH6 tr, tf
A0, CS1B CS2, R/WB E E E
ns
D0 to D7
CL=100pF
10
140 100 15
E, R/WB, A0, D0 to D7
*:All timing based on 20% and 80% of VDD voltage level. *:tCYC6 shows the cycle of theE signal in active CS1B and CS2.
- 38 -
Ver.2003-04-08
NJU6674
Write characteristics (Serial interface)
tCSS CS1B, CS2 tSAS A0 tSCYC SCL tf tSLW tr tSDS tSDH tSHW tSAH tCSH
SI
Parameter Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address set up time Address hold time Data set up time Data hold time CS-SCL time Input signal rising, falling edge
Symbol
Terminal
Condition
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tf, tr
SCL A0 SI CS1B, CS2 CS1B, CS2 SCL, SI, A0
(VDD=2.7V to 3.3V, Ta=-20 to 75C) Unit MIN TYP MAX 250 100 100 150 150 ns 100 100 150 150 15
*:All timing based on 20% and 80% of VDD voltage level.
Ver.2003-04-08
- 39 -
NJU6674
LCD DRIVING WAVEFORM
37 38
0
1
2
3
4
37 38 0
1
2
34
5
FR
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15
C0
VDD VSS VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5
C1
C2
S0
S4 S3 S2 S1 S0 S1 C0~S0 C0~S1
- 40 -
Ver.2003-04-08
NJU6674
APPLICATION CIRCUIT
*
(1) Microprocessor Interface Example The NJU6674 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU. * : C86 terminal must be fixed VDD or VSS. 80 Type MPU VCC CPU VDD SEL68 NJU6674 VDD RD WR RES
RESET
A0 A1~A7 IORQ D0~D7 Decoder
A0 CS1B CS2 D0~D7 RDB WRB RESB
GND
VSS
P/S
68 Type MPU VDD VCC A0 A1~A15 VMA D0~D7 E R/W RES
RESET
A0 Decoder CS1B CS2 D0~D7 E R/WB RESB
VDD SEL68 NJU6674 VDD P/S
CPU
GND
VSS
Serial Interface
VCC
A0 A1~A7 Decoder
A0 CS1B CS2 D7(SI) D6(SCL) RESB
RESET
VDD SEL68 NJU6674
CPU Port 1
Port 2
GND
RES
VSS
P/S
Ver.2003-04-08
- 41 -
NJU6674
MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
- 42 -
Ver.2003-04-08

▲Up To Search▲

Price & Availability of NJU6674

	To Download NJU6674 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .