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| in im el Pr Semiconductor MSM54V24616 Semiconductor 131,072-Word 16-Bit 2-bank SYNCHRONOUS DYNAMIC RAM MSM54V24616 y ar DESCRIPTION The MSM54V24616 is a 131,072-word 16-bit 2-bank synchronous dynamic RAM, fabricated in OKI's CMOS silicon gate process technology. The device operates at 3.3 V. The inputs and outputs are LVTTL compatible. This device can operate up to 125MHz by using synchronous interface. FEATURES * * * * * * * * * * * * * * * * * 131,072-words 16-bit 2 banks configuration Single 3.3 V10% power supply LVTTL compatible inputs and outputs All input signals are latched at rising edge of system clock Auto precharge and controlled precharge Internal pipelined operation: column address can be changed every clock cycle Dual internal banks controlled by A9 (Bank Address: BA) Independent byte operation via DQML and DQMU Programmable burst sequence (Sequential / Interleave) Programmable burst length (1, 2, 4, 8 and full page) Programmable CAS latency (1, 2 and 3) Programmable Write burst (Burst write / Single write) Burst stop function (full-page burst) Power Down operation and Active Power Down (Clock Suspend) operation Auto refresh and Self refresh capability Refresh period: 1,024 cycles / 16 ms Package options: 50-pin plastic TSOP (type II) (TSOPII50-P-400-0.80-K) (Product : MSM54V24616-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM54V24616-8 MSM54V24616-10 MSM54V24616-12 Max. Frequency 125 MHz 100 MHz 83MHz Access Time (Max.) tAC1 22 ns 27 ns 32 ns tAC2 10 ns 12 ns 15 ns tAC3 7 ns 9 ns 10 ns Power Dissipation Operating (Max.) Standby (Max.) 648 mW 540 mW 468 mW 7.2 mW 1 MSM54V24616 Semiconductor PIN CONFIGURATION (TOP VIEW) VCC DQ0 DQ1 VSS(Q) DQ2 DQ3 VCC(Q) DQ4 DQ5 VSS(Q) DQ6 DQ7 VCC(Q) DQML WE CAS RAS CS A9 A8 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 VSS 49 DQ15 48 DQ14 47 VSS(Q) 46 DQ13 45 DQ12 44 VCC(Q) 43 DQ11 42 DQ10 41 VSS(Q) 40 DQ9 39 DQ8 38 VCC(Q) 37 NC 36 DQMU 35 CLK 34 CKE 33 NC 32 NC 31 NC 30 A7 29 A6 28 A5 27 A4 26 VSS 50-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0 - A8 A9 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name DQML / DQMU DQ0 - DQ15 VCC VSS VCC(Q) VSS(Q) NC Function Data Input/Output Mask Data Input/Output Power Supply (3.3 V) Ground (0 V) Data Output Power Supply (3.3 V) Data Output Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCC(Q)pin. The same GND voltage level must be provided to every VSS pin and VSS(Q) pin. 3 Semiconductor MSM54V24616 PIN DESCRIPTION CLK CS CKE Fetches all inputs at the "H" edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, DQMU and DQML. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Address Row & column multiplexed. Row address: RA0 - RA8 Column address: CA0 - CA7 A9 RAS CAS WE DQML DQMU DQ0 - DQ15 Masks the read data of two clocks later when DQMU / DQML is set "H" at the "H" edge of the clock signal. Masks the write data of the same clock when DQMU / DQML is set "H" at the "H" edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. Functionality depends on the combination. For details, see the function truth table. Selects bank to be activated during row address latch time and selects bank for precharge and read/ write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B 3 MSM54V24616 Semiconductor BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQML DQMU Timing Register Programing Register Latency & Burst Controller I/O Controller Bank Controller A9 A0-A9 Internal Col. Address Counter Input Data Register 8 Input Buffers 16 16 8 Column Address Buffers Column Decoders Sense Amplifier Internal Row Address Counter 16 Read Data Register 16 16 Output Buffers DQ0-DQ15 Row Decoders Word Drivers 2Mb Memory Cells 2Mb Memory Cells 9 Row Address Buffers 9 Row Decoders Word Drivers Sense Amplifier Column Decoders 5 Semiconductor MSM54V24616 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr Rating -0.5 to 4.6 -0.5 to 4.6 -55 to 150 1 50 0 to 70 Unit V V C W mA C *: Ta = 25C Recommended Operating Conditions (Voltages referenced to VSS = 0 V) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 2.97 2.0 -0.3 Typ. 3.3 -- -- Max. 3.63 VCC + 0.3 0.8 Unit V V V Capacitance (VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (CLK, CKE, CS, RAS, CAS, WE, DQML, DQMU) Input/Output Capacitance (DQ0 - DQ15) Symbol CIN1 CIN2 COUT Typ. -- -- -- Max. 5 5 7 Unit pF pF pF 5 MSM54V24616 Semiconductor DC Characteristics Condition Parameter Symbol Bank -- -- -- -- One Bank Active CKE -- -- -- -- Others IOH = -2 mA IOL = 2 mA -- -- Version -8 -10 -12 Unit Note Min. Max. Min. Max. Min. Max. 2.4 -- 2.4 -- 2.4 -- V -- 0.4 -- 0.4 -- 0.4 V mA mA -10 10 -10 10 -10 10 -10 10 -10 10 -10 10 -- 130 -- 110 -- Output High Voltage VOH Output Low Voltage Input Leakage Current Output Leakage Current VOL ILI ILO ICC1 Average Power Supply Current (Operating) CKE VIH tCC = min tRC = min No Burst CKE VIH tCC = min tRC = min tRRD = min No Burst CKE VIH tCC = min CKE VIL tCC = min 90 mA 1, 2 ICC1D Both Banks Active -- 180 -- 150 -- 130 mA 1, 2 Power Supply Current (Stand by) ICC2 Both Banks Precharge -- 55 -- 45 -- 40 mA 3 Average Power ICC3P One Bank Active Supply Current (Active Stand by Power Down Mode) Average Power ICC3N One Bank Active Supply Current (Active Stand by Non Power Down Mode) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) ICC4 ICC5 Both Banks Active One Bank Active Both Banks Precharge Both Banks Precharge -- 5 -- 5 -- 5 mA 3 CKE VIH tCC = min -- 75 -- 65 -- 55 mA 3 CKE VIH tCC = min CKE VIH tCC = min tRC = min CKE VIL tCC = min -- 150 -- 130 -- 110 mA 1, 2 -- 120 -- 100 -- 80 mA 2 ICC6 -- CKE VIL tCC = min -- 2 -- 2 -- 2 mA ICC7 2 -- 2 -- 2 mA Notes: 1. Measured with outputs open. 2. Address and data can be changed once or not be changed during one cycle. 3. Address and data can be changed once or not be changed during two cycles. 7 Semiconductor MSM54V24616 Mode Set Address Keys Operation Code A9 0 0 1 1 A8 0 1 0 1 TM Burst Read and Burst Write CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 1 Burst Type A3 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 BT = 1 1 2 4 8 Reserved Burst Read and Single Write Reserved Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved Note: A7 should stay "L" during mode set cycle. MSM54V24616 series has two types of power on sequence. POWER ON SEQUENCE 1 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply an Auto-refresh eight or more times. 5. Enter the mode register setting command. POWER ON SEQUENCE 2 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 100 ms or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Enter the mode register setting command. 5. Apply an Auto-refresh two or more times. 7 MSM54V24616 Semiconductor AC Characteristics 1 Note 1, 2 Parameter CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from CL = 2 Clock CL = 1 Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time form Clock Output High Impedance Time form Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tCC Symbol MSM54V24616-8 MSM54V24616-10 MSM54V24616-12 Min. 8 12 24 -- -- -- 2.5 2.5 2.5 1 3 -- 3 72 24 48 24 16 16 16 -- 8 1 Max. -- -- -- 7 10 22 -- -- -- -- -- 6 -- -- -- 105 -- -- -- -- 16 -- 5 Min. 10 15 30 -- -- -- 3 3 3 1 3 -- 3 90 30 60 30 20 20 20 -- 10 1 Max. -- -- -- 9 12 27 -- -- -- -- -- 8 -- -- -- 105 -- -- -- -- 16 -- 5 Min. 12 18 36 -- -- -- 4 4 3 1.5 3 -- 3 108 36 72 36 24 24 24 -- 12 1 Max. -- -- -- 10 15 32 -- -- -- -- -- 10 -- -- -- 105 -- -- -- -- 16 -- 5 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 3 3, 4 3, 4 3, 4 Write Command Input Time tOWD form Output RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time tRRD tREF tPDE tT 9 Semiconductor MSM54V24616 AC Characteristics 2 Note 1, 2 Parameter CL tCK CAS to CAS Delay Time (Min.) Clock Disable Time from CKE Data Output High Impedance Time from DQM lCCD lCKE lDOZ Symbol MSM54V24616-8 MSM54V24616-10 MSM54V24616-12 Unit Note 3 8 1 1 2 0 0 3 2 1 3 2 12 1 1 2 0 0 2 1 1 3 1 24 1 1 2 0 0 1 0 1 3 3 10 1 1 2 0 0 3 2 1 3 2 15 1 1 2 0 0 2 1 1 3 1 30 1 1 2 0 0 1 0 1 3 3 12 1 1 2 0 0 3 2 1 3 2 18 1 1 2 0 0 2 1 1 3 1 36 1 1 2 0 0 1 0 1 3 ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Data Input Mask Time from DQM lDOD Data Input Time from Write Command lDWD Data Output High Impedance Time from lROH Precharge Command Burst stop to output valid data hold lBSR Burst stop to write data ignore lBSW Active Command Input Time from Mode lMRD Register Set Command Input (Min.) 9 MSM54V24616 Semiconductor Notes : 1. AC measurements assume tT = 1 ns. 2. The reference level for timing of input signals is 1.4 V. 3. Output load. 1.4 V Z = 50 W Output 30 pF 50 W 4. An access time is measured at 1.4 V. 5. If tT is longer than 1ns, the reference level for timing of input signals is VIH and VIL. 11 Semiconductor TIMING WAVEFORM Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU , ,,, , MSM54V24616 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRC tRP tRCD Ra Ca0 Rb Cb0 Ra Rb tOH Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Row Active Write Command Precharge Command Precharge Command 11 MSM54V24616 Semiconductor Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 2, Burst Length = 4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK ,,, ,, tCC tCL CKE CS High tHI tHI tSI RAS tSI tHI lCCD CAS tSI tSI tSI ADDR Ra Ca Cb Cc tHI tHI A9 BS BS BS BS BS A8 Ra tAC tHI DQ Qa Db Qc tOLZ tSI tOH tOHZ tOWD tHI WE tSI DQML DQMU Row Active Write Command Precharge Command Read Command Read Command 13 Semiconductor *Notes: MSM54V24616 1. When CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE and DQML, DQMU are invalid. 2. When issuing an active, read or write command, the bank is selected by A9. A9 0 1 Active, read or write Bank A Bank B 3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is issued. A8 0 1 0 1 A9 0 0 1 1 Operation After the end of burst, bank A holds the active status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the active status. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs. A8 0 0 1 A9 0 1 X Operation Bank A is precharged. Bank B is precharged. Both bank A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1 CLK + tOHZ) after DQML or DQMU entry. 13 MSM54V24616 Semiconductor Page Read & Write Cycle (Same Bank) @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU *Notes: , , ,,,, , , , , , , , 17 18 19 High Bank A Active lCCD Ca0 Cb0 Cc0 Cd0 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 tWR *Note2 *Note1 Read Command Read Command Write Command Write Command Precharge Command 1. To write data before a burst read ends, DQMi should be asserted three cycles prior to the write command, to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 15 ,,,, , , , , , , Read & Write Cycle with Auto Precharge @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Semiconductor MSM54V24616 CLK CKE CS High RAS tRRD CAS ADDR Ra Rb Ca Cb A9 A8 Ra Rb WE CAS Latency = 1 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 DQML DQMU A-Bank Precharge Start CAS Latency = 2 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 DQML DQMU A-Bank Precharge Start CAS Latency = 3 DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 A-Bank Precharge Start tWR DQML DQMU Row Active (A-Bank) A Bank Read with Auto Precharge Row Active (B-Bank) B Bank Write with Auto Precharge B Bank Precharge Start Point 15 MSM54V24616 Bank Interleave Random Row Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU , , , ,, , , 18 19 Semiconductor High tRC tRRD RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 Row Active (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) Row Active (A-Bank) 17 Semiconductor MSM54V24616 ,,,, , , , ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank Interleave Random Row Write Cycle @ CAS Latency = 2, Burst Length = 4 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CA A9 A8 RAa RBb RAc DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 WE DQML DQMU Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Row Active (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 17 MSM54V24616 Bank Interleave Page Read Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU *Note: , ,,, , , 16 17 18 19 Semiconductor High *Note1 RAa CAa RBb CBb CAc CBd CAe RAa RAa QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 lROH Row Active (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 19 ,,, ,, , , , , , Semiconductor MSM54V24616 Bank Interleave Page Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb CAc CBd A9 A8 RAa RAb DQ DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 WE DQML DQMU Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Write Command (A-Bank) Precharge Command (Both Bank) 19 MSM54V24616 Semiconductor ,,, , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Bank Interleave Random Row Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CBb RAc CAc A9 A8 RAa RBb RAc DQ QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 WE DQML DQMU Row Active (A-Bank) Row Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Row Active (A-Bank) 21 Semiconductor MSM54V24616 Bank Interleave Page Read/Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU , , ,,,, , High CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 QAc3 Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 21 MSM54V24616 Semiconductor Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note1 *Note1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A9 A8 DQ0 - 7 Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Dc2 *Note4 DQ8 - 15 tOHZ tOHZ *Note3 Dc1 Qa0 Qa2 Qa3 Qb0 Qb1 Dc0 *Note2 WE DQML *Note4 DQMU Row Active Read Command Read DQM CLOCK Suspension Read Command CLK *Notes: , , ,, , ,, Read DQM Read DQM Write Command Write DQM CLOCK Suspension Write DQM 1. 2. 3. 4. When CKE is deactivated, the next clock cycle will be ignored. When DQMs are asserted, the read data after two clock cycles will be masked. When DQMs are asserted, the write data in the same clock cycle will be masked. When DQML is set High, the input/output data of DQ0 - DQ7 will be masked. When DQMU is set High, the input/output data of DQ8 - DQ15 will be masked. 23 Semiconductor Read Interruption by Precharge Command @ Burst Length = 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSM54V24616 CLK CKE CS RAS CAS ADDR A9 A8 WE CAS Latency = 1 DQ DQML DQMU CAS Latency = 2 DQ DQML DQMU CAS Latency = 3 DQ DQML DQMU *Note: When CAS latency = n, and if row precharge is asserted before a burst read ends, then the read data will not output after the n clock cycle of precharge command. ,, ,,, ,, , ,, ,, , 16 17 18 19 High Ra Ca Ra *Note Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 *Note Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Row Active Read Command Precharge Command 23 ,,, , , ,, MSM54V24616 Semiconductor Full Page Burst Read Cycle @ CAS Latency = 2, Burst Length = Full page 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 CLK CKE CS High High RAS CAS ADDR Ra Ca A9 A8 Ra DQ Qa0 Qa1 Qa2 Qa3 Qa4 Qa254 Qa255 Qa0 Qa1 Qa2 Qa3 Qa4 IBSR WE DQM Row Active Burst stop Command Read Command Precharge Command 25 ,,, , , ,, Semiconductor MSM54V24616 Full Page Burst Write Cycle @ CAS Latency = 2, Burst Length = Full page 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 CLK CKE CS High High RAS CAS ADDR Ra Ca A9 A8 Ra DQ Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da1 Da2 Da3 Da4 Da5 Da6 IBSW WE DQM Row Active Burst stop Command Write Command Precharge Command 25 MSM54V24616 Burst Read Single Write Cycle @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Semiconductor , , ,, , , 15 16 17 18 19 CLK CKE CS High RAS CAS ADDR RAa CAa RBb CAb CBa A9 A8 RAa RBb DQ QAa0 QAa1 QAa2 QAa3 DAb0 QBa0 QBa1 QBa2 QBa3 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Read Command (A-Bank) Read Command (B-Bank) Precharge Command (B-Bank) 27 , ,, , , , Semiconductor MSM54V24616 Power Down Mode @ CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI *Note1 CKE CS *Note2 tPDE tSI tSI RAS CAS ADDR Ra Ca A9 A8 Ra DQ Qa0 Qa1 Qa2 WE DQML DQMU Row Active Power-down Entry Power-down Exit Clock Suspention Entry Clock Suspention Exit Read Command Precharge Command *Notes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM54V24616 enters powerdown mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, set CKE high for longer than tPDE, and the inputs will be set within the same cycle. 27 MSM54V24616 Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A9 A8 DQ WE DQML DQMU , , ,,, , Semiconductor tRCmin. tSI tPDE Ra BS Ra Hi - Z Hi - Z Self Refresh Entry Self Refresh Exit Row Active 29 Semiconductor Mode Register Set Cycle 0 1 2 3 4 5 6 MSM54V24616 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK CKE CS RAS CAS ADDR DQ WE DQML DQMU ,, , ,, , High High lMRD tRC key Ra Hi - Z Hi - Z MRS New Command Auto Refresh Auto Refresh 29 MSM54V24616 Semiconductor FUNCTION TRUTH TABLE (Table 1) (1/2) Current State1 Idle CS RAS CAS WE BA H L L L L L L L Row Active H L L L L L L Read H L L L L L L L Write H L L L L L L L Read with Auto Precharge H L L L L L L Write with Auto Precharge H L L L L L L X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X X X BA BA BA BA X ADDR X X X CA RA A8 X OP Code X X CA, A8 CA, A8 RA A8 X X X X CA, A8 CA, A8 RA A8 X X X X CA, A8 CA, A8 RA A8 X X X X CA, A8 X RA, A8 X X X X CA, A8 X RA, A8 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Auto-Refresh or Self-Refresh 5 Mode Register write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst stop (Full page), NOP (BL=1, 2, 4 and 8) Term Burst, start new Burst Read Term Burst, start new Burst Write ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Burst stop (Full page), NOP (BL=1, 2, 4 and 8) Term Burst, Start new Burst Read Term Burst, start new Burst write ILLEGAL 2 Term Burst, executo Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Action 31 Semiconductor MSM54V24616 FUNCTION TRUTH TABLE (Table 1) (2/2) Current State1 CS RAS CAS WE BA Precharge H L L L L L L Write Recovery H L L L L L L Row Active H L L L L L L Refresh H L L L L Mode Register Access H L L L L X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A8 X X X X CA RA A8 X X X X CA RA A8 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Action ABBREVIATIONS RA = Row Address CA = Column Address Notes: BA = Bank Address AP = Auto Precharge NOP = No OPeration command 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A8. 5. Illegal if any bank is not idle. 31 MSM54V24616 Semiconductor FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) CKEn-1 Self Refresh 6 CKEn x H H H H H L X H H H H H L H L L L L L L L L H L H L CS RAS CAS WE X H L L L L X X H L L L L X X H L L L L L L X X X X X X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Action Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 7 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enaole Clock of Next Cycle Continue Clock Suspension H L L L L L L Power Down 6 H L L L L L L All Banks Idle 7 (ABI) H H H H H H H H L Any State Other than Listed Above H H L L Notes: 6. If a minimam set-up time tPDE is satisfied when CKE transitions from "L" to "H", CKE operates asynchronously so that a command can be input in the same internal clock cycle. 7. Power-down and self refresh can be entered only when all the banks are in an idle state. 32 |
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