View MS140132KT_992026.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Order Number: MS140132KT/D Rev. 1, 5/2001
Semiconductor Products Sector
MS140132KT
Advance Information
6KRUW +DXO /RRS 'XDO 3&0 &RGHF)LOWHU6/,& &KLSVHW ZLWK 63, ,QWHUIDFH
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 2001. All rights reserved.
&217(176
Section 1 Overview
1.1 1.2 Introduction: MC1420233 CODSP and MC1430132 SHLIC. . . . . . . . . . . . . . . . . . . . . . . . . . Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1
Section 2 Applications
2.1 2.2 Recommended External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-3
Section 3 Pin Descriptions
3.1 3.2 3.3 3.4 Device Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1420233 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1430132 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 SHLIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note on Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 CODSP Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 SHLIC Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-4 3-5 3-5 3-5 3-6 3-6 3-6
3.5
Section 4 Functional Characteristics of the SH-POTS System
4.1 4.2 On-Hook Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Balanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Semi-Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Battery Voltage and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-3 4-3 4-4 4-4 4-5
4.3
MS140132KT
iii
Contents
4.4
4.5
4.6 4.7
AC Transmission Characteristics (MS140132KT System). . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.1 Transmit and Receive Filter Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.2 Transmit and Receive Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.3 Source Impedance (ZCO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.4.4 Balance Impedance (Echo Canceller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Metering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5.1 Metering Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.5.2 Metering Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 CODSP Clock Recovery PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Section 5 Electrical Characteristics
5.1 5.2 5.3 5.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Shutdown SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Transient Energy Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . 5.4.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 VDD3 Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 DCO DC Levels, Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 VAG Analog Ground Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 DC Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 DCC Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.7 Characteristics for the Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.8 Test Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.9 Battery Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics (SHLIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Overpower and Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Hook Characteristics (MS140132KT System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Hook Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the PCM Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-1 5-2 5-2 5-2 5-3 5-4 5-6 5-6 5-7 5-7 5-8 5-9 5-9 5-10 5-11 5-11 5-11 5-13 5-14 5-14
5.5
5.6 5.7 5.8
Section 6 Detailed Programming Description
6.1 6.2 6.3 6.4 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description of the Programming Interface: SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmability of the SH-POTS Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Software Reset of the Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6-3 6-4 6-5 6-5
MS140132KT
iv
Contents
6.5 6.6 6.7 6.8
6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20
6.4.2 Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Access to the CODSP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Other Features via the SPI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Write SPI Interface Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 Read SPI Interface Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers in the SPI Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the PCM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map of the CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data RAM -- MemID = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBO Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alarm Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Coefficient RAM -- MemID = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Memory -- MemID = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Meaning and Default Values of the Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-5 6-6 6-6 6-7 6-8 6-8 6-8 6-9 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-15 6-18 6-19 6-21 6-22
Section 7 Mechanical Specifications
7.1 7.2 7.3 MC1420233 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1430132 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Pad Layout for 44-Lead TQFP MC1420233 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 7-3
v
MS140132KT
),*85(6
1-1. 2-1. 2-2. 2-3. 3-1. 3-2. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 5-1. 5-2. 5-3. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 7-1. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical SH-POTS Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Schematic for Two Analog Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Overvoltage Protection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1420233 CODSP Recommended Power-Supply Decoupling Arrangements . . . . . . . . . . . . SH-POTS Line Voltages -- Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nominal Hookswitch Detection Thresholds (Default Values) . . . . . . . . . . . . . . . . . . . . . . . . . . Application Suggestion for Semi-Unbalanced Ringing Injection . . . . . . . . . . . . . . . . . . . . . . . . DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit and Receive Frequency Response (Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relative Group Delay, Transmit and Receive Paths (Digital-to-Digital) Referred to 1 kHz . . . Three-Element ZCO Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering Pulse Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram Showing Gains in Various Signal Paths in SHLIC . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Signalling Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Bus Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Bus Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Write Request Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Example of PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Pad Layout for 44-Lead TQFP MC1420233 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2-1 2-4 2-6 3-1 3-7 4-1 4-2 4-4 4-5 4-6 4-7 4-8 4-9 5-10 5-12 5-14 6-2 6-3 6-5 6-6 6-7 6-7 6-8 6-9 6-9 6-12 7-3
MS140132KT
vi
7$%/(6
2-1. 3-1. 3-2. 3-3. 3-4. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 4-7. 4-8. 5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 5-10. 5-11. 5-12. 5-13. 5-14. 5-15. 5-16. 5-17. 5-18. 5-19. 5-20. Recommended External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions for MC1420233 CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions for MC1430132 SHLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1420233 CODSP Unused Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC1430132 SHLIC Unused Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Hook Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Feed Characteristics [Rfeed = 60 Total (50 +10 Protection) x 2] . . . . . . . . . . . . . . Examples of ZCO Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metering Characteristics (Determined by MC1420233 CODSP) . . . . . . . . . . . . . . . . . . . . . . . . Tone Signal Levels (Common Values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Generator Division Values for Common Frequencies from ETS-300-001 and DTMF Tones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Required Frequency Setting Values (N) for a Melody Generator (Western Equal-Tempered Scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHLIC Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD3 Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Characteristics A Wire (AW), B Wire (BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impedance Characteristics A Wire (AW), B Wire (BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rx, Tx Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VAG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Loop Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCC Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sense Bridge Inputs Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Switch Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Battery Switch Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Hook Characteristics (MS140132KT System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-2 3-4 3-5 3-6 4-2 4-3 4-5 4-8 4-10 4-11 4-12 4-13 5-1 5-2 5-3 5-3 5-4 5-4 5-5 5-5 5-6 5-6 5-6 5-7 5-7 5-8 5-8 5-9 5-9 5-10 5-12 5-13
MS140132KT
vii
Tables
6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 6-9. 6-10. 6-11.
SPI Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map: SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map for CODSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LBO Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Coefficient RAM: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Coefficient RAM: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . Shared Memory: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Memory: Description and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2 6-3 6-10 6-13 6-13 6-14 6-15 6-18 6-19 6-21 6-22
MS140132KT
viii
6(&7,21
29(59,(:
,1752'8&7,21 0& &2'63 $1' 0& 6+/,&
The MS140132KT chipset provides all the functions necessary to connect analog telephone sets or other analog terminals (telefax, answering machines, modems, etc.) into digital communication systems. It provides an economical solution for the traditional "BORS(C)HT" [Battery, Overvoltage, Ringing, Supervision, (Codec), Hybrid, Test] functions found in central-office exchanges, but is optimized for short-range communication [e.g., up to 500 m with 5 RENs (Ringer Equivalence Number) attached]. Virtually all system-dependent parameters can be set under software control, giving an unprecedented flexibility to the system integrator, as well as optimizing the system cost. The digital interface to the SH-POTS (Short Haul, Plain Old Telephone System) chipset uses the PCM/SPI interface. The system architecture has been designed to offer the most cost-effective solution for short haul systems, yet offers the full flexibility required to meet worldwide analog telephony standards. The MS140132KT chipset is also suitable for Q.552 applications. The MS140132KT chipset comprises three devices (see Figure 1-1): a pair of high-voltage devices, the Short Haul Line Interface Circuit (SHLIC) which provides the signal and power interface to the analog lines (one per line), and a low-voltage CMOS, DSP-based dual codec/control device (CODSP) which provides all signal processing and control functions for up to two lines.
* * * * * * * * * *
.(< )($785(6
Digitally Programmable Transmission and Signalling Characteristics Meet Worldwide Specification Requirements Integrated Ringing: Sine or Trapezoid with Auto Cadence Metering Injection (12 or 16 kHz) Support On-Hook Transmission: ADSI, CLIP Battery Reversal Codec and AC Parameters (ZCO and Hybrid) are Fully Programmable (A-Law or -Law) Tone Generators for Signalling and Testing Loop Current Control and Monitoring are Programmable Minimal External Components Codec and SLIC Functions for Two Lines
MS140132KT
1-1
Overview: Key Features
* * * * * * * *
Low-Cost POTS Interface for Short Range Flexible IDL Interface with Timeslot Assigner Test Support (Test Load Switch, Loopback, Tone Generators) Supports up to -72 V on VBAT Ring and -35 V on VBAT Speech CODSP (Dual Codec) is 3.3 V with 5 V Tolerant Input for Low Power Consumption PCM Interface with Clock Frequency from 512 kHz to 8192 kHz in Steps of 512 kHz, Programmable up to128 Channels for Speech SPI Interface with Clock Frequency up to 8192 kHz to Control the PCM and SH-POTS Functions One Programmable Output Per Line for Signaling (Default: Off-Hook Detection)
DET0 DET1
BUSY CH0 CH1 SPIin SPiout SPICLK SPI REGISTERS PCM INTERFACE CURRENT CODSP (WITH CHANGE OF PINS) SPI INTERFACE
PCMout PCMin PCMA PCMCLK FRAME
Figure 1-1. Block Diagram
MS140132KT
1-2
6(&7,21
$33/,&$7,216
Figure 2-1 shows a typical SH-POTS application using Motorola semiconductor chip solutions. The short haul dual PCM chipset provides all necessary functions to connect analog telephone sets or fax terminals to digital communications systems. * * * * Advanced ISDN NT (NTplus), Smart NT1 Personal Router Analog/Digital PABX Cable Telephone Systems (Set-Top Box) Remote Telephone Access Systems -- Fiber to the Curb -- Radio in the Loop Internet Telephones
*
ETHERNET 10BASE-T ETHERNET TRANSCEIVER
68030 CPU CORE ETHERNET MAC
SCP SCP
TRANSCEIVER MC145572 "U" DC METALLIC TERMINATOR
"U" OR "S/T" INTERFACE
SCC1 SCC2 SCC3
PCM
MC145574 "S/T"
TIMER BUS INTERFACE GPIO DRAM ANALOG POTS/FAX FLASH
POTS CIRCUITRY MS140132KT
Figure 2-1. Typical SH-POTS Application
MS140132KT
2-1
Applications:
BUSY CH0 CH1
TST[0] BR[0] RNG[0] PU[0] Rx[0] Tx[0] DCC[0] DCO[0] CDCI
TST BR RNG PU SHLIC Rx Tx DCC DCO DCI
SSB SB BW Ztest CB2 RB2 BAT BATS DP BATR VDD5A VSSB DCLF1 RF1 CS CP
PCM PORT
PCMCLK FRAME PCMout PCMin
RPROT VBATS DP VBATR
1 -- JTAG TEST ACCESS 1 1 0
JTDI JTDO JTCK JTMS JTRS
VAG CVAG
VAG VSSA DCLF2
CD
VDD5A
DEVICE TEST
0 0
DET0 DET1 VDD3A CV3A VDD3 VAG
RF2 SA AW SSB SB BW SHLIC Rx[1] Tx[1] DCC[1] DCO[1] CDCI CODSP Rx Tx DCC DCO DCI BAT BATS
CF1 CF2 a PROTECTION CB1 RB1 Ztest CB2 RB2 LINE b RPROT VBATS DP CP CS VBATR VDD5A CD
VDD3D D1 RPWRS PWRS CPWRS
TST[1] BR[1] RNG[1] PU[1]
TST BR RNG PU
BATR VDD5A VSSB
VSSA
VSSD
CPLL CPLL
VSSA
DCLF2
DCLF1 RF1 RF2 CF2
CF1
Figure 2-2. Application Schematic for Two Analog Lines
MS140132KT
2-2
LINE b
SPI PORT
PROTECTION
SPICLK SPIin SPIout
VDD3D CV3D
VDD3
SA AW CB1 RB1
a
Applications: Recommended External Components
5(&200(1'(' (;7(51$/ &20321(176
Table 2-1. Recommended External Components
Component RB1, RB2 RPROT Ztest RF1, RF2 CB1, CB2 CDCI CF1, CF2 CVAG CV3A CV3D CS CPLL CPWRS RPWS D1 DP CD Feed resistor
Function
x 50 2 x 10 510 10 k 1 nF 330 nF 470 nF 100 nF 10 F + 100 nF 10 F + 100 nF 100 nF 4.7 nF 100 nF 100 k -- -- 100 nF 100 V
Comment 1/4 W 1% (see Note 1)
Protection resistance Test resistor DC bias filter No-load stabilization DC feed separation DC bias filter Analog ground decoupling Analog 3.3 V regulator decoupling Digital 3.3 V decoupling Battery supply decoupling PLL loop filter Power-on reset delay Power-on reset delay Power loss reset Battery input protection 5 V power supply decoupling
1/4 W, optional
100 V (see Note 2) 5% 100 V, 10%
Any small signal diode BAT46 required depending on the power supplies
NOTES: 1. A 1% results in a maximum longitudinal balance of 40 dB. For higher values, more precise matching is required (e.g., 0.1% for 46 dB). 2. Capacitors are generally not required. They are foreseen to stabilize the line driver outputs when active but driving no load (test condition only).
29(592/7$*( 3527(&7,21
There are several recommended overvoltage protection options. The application will determine the most appropriate one to chose (e.g., in-house only systems with minimal protection requirements, or systems with loops outside a protected environment requiring more extended protection). The first external protection network to protect the line circuit against foreign voltages consist of resistors RPR1 and RPR2 and an overvoltage protection component (see Figure 2-3). Series resistors RPR1 and RPR2 can be PTC, poly-switch, or fusible components. For further protection, the simplest and cheapest solution is a diode bridge between SA, SB and V SSB, BATR, respectively. The diodes must be able to allow current peaks more than 20 A. In case the battery BATR can not accept these high current peaks, add a voltage clamping component to VSS, or a transient suppressor between each line and VSS. The clamp voltage or protection voltage minimum must always be larger than the maximum used ringing battery BATR.
2-3
MS140132KT
Applications: Overvoltage Protection
The protection components must be dimensioned in such a way that the transient energy on the chip pins AW, BW does not exceed 1 mJoule (or, the energy on-chip because of one lightning pulse).
RPR1
RB1
SA AW
RPR1
RB1
SA AW
BATR VSSB RPR2 RB2
MC1430132 SHLIC BW SB
VSSB RPR2 RB2
MC1430132 SHLIC BW SB
RPR1
RB1
SA AW
RPR1
RB1
SA AW
VSSB RPR2 RB2
MC1430132 SHLIC BW SB
VSSB RPR2
TRANSIENT SUPPRESSOR RB2
MC1430132 SHLIC BW SB
Figure 2-3. Recommended Overvoltage Protection Options
MS140132KT
2-4
6(&7,21
3,1 '(6&5,37,216
'(9,&( 3,12876
MC1430132 28-LEAD SOIC
PIN 1 INDICATOR
MC1420233 44-LEAD TQFP
RNG[0]
SPIout
VSSB BW BAT BATS BATR PU NC NC RNG BR TST VAG VDD5A VSSA
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AW SA SB SSB DCO DCI NC NC DCC Tx Rx DCLF1 DCLF2 VDD3
TST[0]
PWRS
BUSY
DET0
DET1
TEST
PU[0]
BR[0]
44 43 JTDO JTCK JTMS JTDI JTRS VDD3D PCMout PCMin PCMCLK FRAME VSSD 1 2 3 4 5 6 7 8 9 10 11
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Rx[0] Tx[0] DCC[0] DCO[0] DCC[1] DCO[1] VSSA VAG VDD3A Tx[1] Rx[1]
12 13 14 15
16 17 18 19 20 21 22
SPICLK
PLLCK
RNG[1]
Figure 3-1. Pin Assignments
MS140132KT
TST[1]
SCLK
CPLL
SPIin CH0
CH1
BR[1]
PU[1]
Zout
3-1
Pin Descriptions: MC1420233 Pin Descriptions
0& 3,1 '(6&5,37,216
Table 3-1. Pin Descriptions for MC1420233 CODSP
Pin Name JTDO JTCK JTMS JTDI JTRS VDD3D PCMout PCMin PCMCLK FRAME VSSD SPICLK SPIin CH0 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 JTAG test port data out JTAG test port clock JTAG test port mode select JTAG test port data in JTAG test port reset Digital section supply voltage Three-state PCM transmit data output that is enabled based on FRAME PCM receive data input, which is shifted into the CODSP following a programmed delay on the FRAME leading edge 2.048 MHz clock input Transmits and receives frame sync pulse for line 0 Digital ground (0 V) 2.048 MHz control clock input Bit serial data input Line 0 select, when CH0 = 0, the SPIout returns the data and the 8-bit control and programming data can input to the CODSP to control line 0 via SPIin, when CH0 goes from low to high, the data is latched Line 1 select, same functionality as CH0 SHLIC 1 test select SHLIC 1 bat reverse control SHLIC 1 ring control SHLIC 1 power-up control System clock (test only) PLL clock (test only) PLL loop filter capacitor SHLIC 1 Rx analog signal SHLIC 1 Tx analog signal Analog supply voltage Analog ground reference voltage output Analog ground (0 V) SHLIC 1 DC loop output SHLIC 1 DC loop control Pin Description Type (See Note) DO DIu DIu DIu DIu P DO5 DI5 DI5 DI5 P DI5 DI5 DI5
CH1 TST[1] BR[1] RNG[1] PU[1] SCLK PLLCK CPLL Rx[1] Tx[1] VDD3A VAG VSSA DCO[1] DCC[1]
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
DI5 DO DO DO DB DI DIs AO AO AI P AO P AI AO
MS140132KT
3-2
Pin Descriptions: MC1420233 Pin Descriptions
Table 3-1. Pin Descriptions for MC1420233 CODSP (continued)
Pin Name DCO[0] DCC[0] Tx[0] Rx[0] Zout TEST TST[0] BR[0] RNG[0] PU[0] SPIout DET1 DET0 BUSY PWRS Pin No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SHLIC 0 DC loop output SHLIC 0 DC loop control SHLIC 0 Tx analog signal SHLIC 0 Rx analog signal Digital I/O drive control (test only) Test mode select (test only) SHLIC 0 test select SHLIC 0 bat reverse control SHLIC 0 ring control SHLIC 0 power-up control Bit serial data output On/off hook and ring trip detection output (line 1) On/off hook and ring trip detection output (line 0) Indicates when a command is being executed Reset input Pin Description Type (See Note) AI AO AI AO DB DId DO DO DO DB DO5 DO5 DO5 DO5 DIs
NOTE: The first letter differentiates between: D: Digital A: Analog P: Power The second letter differentiates between: I: Input O: Output B: Bidirectional The third letter differentiates between: d: Pin with internal pull-down u: Pin with internal pull-up s: Pin with Schmitt-trigger input 5: 5 V compatible input NC: No connect
3-3
MS140132KT
Pin Descriptions: MC1430132 Pin Descriptions
0& 3,1 '(6&5,37,216
Table 3-2. Pin Descriptions for MC1430132 SHLIC
Pin Name VSSB BW BAT BATS BATR PU NC NC RNG BR TST VAG VDD5A VSSA VDD3 DCLF2 DCLF1 Rx Tx DCC NC NC DCI DCO SSB SB SA AW
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Battery ground (0 V) B wire output
Pin Description
Type P AB P P P DI NC NC DI DI DI P P P P AO AO AO AI DI NC NC AI AO AI AI AI AB
Battery voltage (output, do not connect) Battery voltage input, SPEECH mode Battery voltage input, RING mode Power-up control Do not connect; thermal conduction pin Do not connect; thermal conduction pin Ring mode control Battery reverse control Test mode control Analog ground reference input Analog supply voltage Analog ground, 0 V 3 V regulator output DC bias filter capacitor 2 DC bias filter capacitor 1 Analog receive signal Analog transmit signal DC loop control input Do not connect; thermal conduction pin Do not connect; thermal conduction pin DC loop control separation filter input DC loop control output Loop test resistor switch B wire sense input A wire sense input A wire output
NOTES: 1. A 1% results in a maximum longitudinal balance of 40 dB. For higher values, more precise matching is required (e.g., 0.1% for 46 dB). 2. Capacitors are generally not required. They are foreseen to stabilize the line driver outputs when active but driving no load (test condition only).
MS140132KT
3-4
Pin Descriptions: Unused Pins
8186(' 3,16
&2'63
Table 3-3 lists the pins on the CODSP that are not connected. Pins that are not used in the application should be connected as described here. Failure to do so could result in excessive sensitivity to RFI or other erratic behavior. A 0 or 1 indicates that the pin should be connected to ground or to the device's digital supply. A "--" indicates that the pin is an output and must be left unconnected.
Table 3-3. MC1420233 CODSP Unused Pin Connections
Pin Name JTDI JTDO JTCK JTMS JTRS SCLK PLLCK Zout TEST Pin No. 4 1 2 3 5 20 21 34 35 Connect To 1 (VDD3D) -- 1 (VDD3D) 1 (VDD3D) 0 (VSS) VSS VSS VSS VSS
6+/,&
Table 3-4 lists the pins on the SHLIC that are not connected. The NC pins (7, 8, 21, and 22) are connected to the device substrate, which is at a voltage equal to the VBATR supply pin, and may optionally be electrically connected to this pin.
Table 3-4. MC1430132 SHLIC Unused Pin Connections
Pin Name BAT NC NC NC NC Pin No. 3 7 8 21 22 Connect To No connect or see text above No connect or see text above No connect or see text above No connect or see text above No connect or see text above
3-5
MS140132KT
Pin Descriptions: Note on Decoupling
The BAT pin is the internal supply to the line drivers, and adopts the voltage of VBATR or VBATS, plus the voltage drop across the internal switch, depending on the operating mode. In low-voltage only systems (very short connections), the BAT pins, V BATR and VBATS, may all be connected together and a single supply (e.g., -27 V) may be used for both ringing and speech modes. (In this mode, the voltage drop of the internal switches is avoided.)
127( 21 '(&283/,1*
As in any system, the PCB layout and supply decoupling can influence the system performance, particularly with respect to noise.
&2'63 'HFRXSOLQJ
* It is recommended to connect VDD3D and VDD3A (digital and analog supply pins) in a star configuration from the supply (either from the SHLIC or from an external supply), and each pin be independently decoupled using 10 F in parallel with 100 nF. In two-line systems, using the SHLIC regulator to supply only the CODSP (i.e., no other use is made of the regulator), one SHLIC may be used to provide VDD3D power and the other VDD3A, thus giving improved decoupling between analog and digital supplies. See Figure 3-2. * The VAG line (analog signal reference) must always be properly decoupled using 100 nF, placed as close as possible to the CODSP device.
6+/,& 'HFRXSOLQJ
* The SHLIC should use separate 100 nF decoupling capacitors between VDD5A and VSSB, and VDD5A and VSSA. When the on-board regulator of the SHLIC is not used, no capacitor is required at the VDD3 pin.
MS140132KT
3-6
Pin Descriptions: Note on Decoupling
MC1430132 VDD3 SHLIC VSSB VSSA GROUND STAR-POINT VSSA V MC1430132 SSB SHLIC VDD3
VDD3A 10 F TA 100 nF CERAMIC 100 nF CERAMIC VSSA VAG VSSD 10 F TA 100 nF CERAMIC VDD3D MC1420132 CODSP
(a) Arrangement A
+3.3 V STAR POINT MC1430132 SHLIC VSSB VSSA GROUND STAR-POINT VSSA VSSB MC1430132 SHLIC 10 F TA 100 nF CERAMIC 100 nF CERAMIC VSSA VAG VSSD 10 F TA 100 nF CERAMIC VDD3D VDD3A MC1420132 CODSP
(b) Arrangement B
Figure 3-2. MC1420233 CODSP Recommended Power-Supply Decoupling Arrangements
3-7
MS140132KT
6(&7,21
)81&7,21$/ &+$5$&7(5,67,&6 2) 7+( 6+3276 6<67(0
For reference, Figure 4-1 shows the typical voltages on tip and ring during various stages of operation. For detailed electrical parameters, refer to Section 5.
(SATURATION, <0.5 V) 0V (BIAS, 3 V) (BIAS, 3 V)
VBATS (e.g., -24 V) (AVG. DC = VBATR/2) (BIAS, 3 V + DROP OF BAT SWITCH)
(BIAS, 3 V + DROP OF BAT SWITCH) VBATR (e.g., -64 V)
ON-HOOK
ON-HOOK ADSI
RING BURST
OFF-HOOK
Figure 4-1. SH-POTS Line Voltages -- Example
21+22. &21',7,216
When a line is not in use (on-hook), the designer may select either the speech battery or the ringing battery as the supply to the line drivers. In the on-hook mode, most of the internal circuits are put into a low-power operating mode to minimize supply currents. The A and B wire outputs are effectively connected to the supply voltage, thus applying this voltage (minus a small saturation voltage) to the line. The output is current-limited in this mode, thus protecting against short circuits and limiting any inrush current when a set goes off-hook. If the SHLIC detects a current in excess of a (programmable) limit, the off-hook
MS140132KT
4-1
Functional Characteristics of the SH-POTS System: On-Hook Conditions
condition will be detected (an on-chip debouncer with selectable delay avoids accidental hookswitch detection), and the circuit will be put into active speech mode. The nominal off-hook detection currents and hysteresis are shown in Figure 4-2. When a line is in the on-hook condition, the system designer may select, under program control via the PCM/SPI bus, an "on-hook active mode," whereby, on-hook signalling (ADSI, CLIP, etc.) can be performed in either direction (though battery reversal is not available in this mode). The hookswitch detector has a programmable debounce timer. Times of 8, 16, 24, or 64 ms can be selected. (The timer is common for both channels.)
OFF-HOOK
ON-HOOK
LINE CURRENT 6.3 10.0 (mA)
Figure 4-2. Nominal Hookswitch Detection Thresholds (Default Values) Table 4-1. On-Hook Characteristics
Parameter VfeedO Ion Ioff IOHYST IOC VbiasH VbiasL Open-line feed voltage Line current guaranteeing on-hook state Line current guaranteeing off-hook state Hookswitch detect hysteresis Peak over-current limit, on-hook mode Bias voltage during ADSI mode on A (H) and B (L) wires, ref. BAT pin Condition Min VBATS-1 4.67 7.86 2 -- 2 Max VBATR-1 7.93 12.14 -- 145 4 Unit V mA mA mA mA V Note 1 2 2 2 3
NOTES: 1. Iline = 0 mA, independent of battery reversal mode. This voltage is selected by the user. The output impedance when in the on-hook condition is set by the sense resistors Rfeed. The hook-switch detector has a programmable debounce timer. Times of 8, 16, 24, or 64 ms can be selected (common for both channels). 2. These are the default values after reset. The on-hook and off-hook thresholds can be individually programmed in the range 0 to 63 mA nominal. 3. This is the intrinsic current limit of the output driver. This current can only be seen during on-hook to off-hook transients, or during ringing into a short-circuit load during the ring-trip delay period. The actual value measured will depend on the load resistance used.
4-2
MS140132KT
Functional Characteristics of the SH-POTS System: Ringing Injection
5,1*,1* ,1-(&7,21
%DODQFHG 5LQJLQJ
The SH-POTS chipset is capable of directly injecting a ringing signal of up to 50 Vrms (sine wave) without the need for additional external components. The technique of "balanced ringing" is used, which allows this large voltage swing to remain within the technology limits of the SHLIC device. (Balanced ringing requires a specific algorithm for ring-trip detection, which is also implemented by the chipset.) The SH-POTS chipset allows the user to program a dc offset during ringing as well as a reduced amplitude ringing signal, should the application require this. Ringing waveform, frequency, amplitude, and cadence, as well as ring-trip thresholds, are controlled by the CODSP device, and are all programmable. Ringing cadence can be automatic, with independently programmable ring and pause times, or ringing can be controlled directly via the PCM/SPI bus. In the automatic cadence mode, ringing bursts on both channels can be optionally interleaved, if simultaneously active, to avoid peaks in current from the ringing battery supply.
Table 4-2. Ringing Characteristics
Parameter FR Ringing frequency 16.66, 20, 25 Hz 50 Hz Single-frequency noise, 10 Hz to 4 kHz Ringing voltage (max), VBATR = -72 V Ringing distortion, sine mode 30 Hz to 132 kHz Ring-trip delay, load = 500 + 4 F Ring-trip debounce time Ring-cadence times (active and silent) Ring-trip current, high threshold Ring-trip current, low threshold Ring-trip hysteresis Condition Min -1 -2 -- 50 -- -- 0 1 6.0 3.5 2 Max 1 2 -63 -- 5 150 30 255 12.0 9.5 -- dBm Vrms % ms ms n/n mA mA mA 2 4 3 3 3 1 Unit Hz Note
SFNR VR DR tRTD tRTDEB tC IRTH IRTL HRT
NOTES: 1. Ringing voltage is user-programmable from 0 to 70 Vp(diff) between the A and B wires (NB, the ringing battery voltage must be large enough to encompass this voltage) in 256 steps. The default is the maximum value. Condition: Load = 0 mA. 2. User-selectable 0 or 30 ms. Default is 30 ms. 3. These are the default values after reset. The max and min ring-trip thresholds can be individually programmed in the range 0 to 63 mA nominal. The ring-trip detect mask time is used to bridge the zero-crossings of the ringing signal, and is programmable between 0 and 32 ms in 125 s steps. 4. Units are periods of the selected ringing frequency. The default values are 1 s on, 3 s off, with a ringing frequency of 50 Hz.
MS140132KT
4-3
Functional Characteristics of the SH-POTS System: DC Feed Characteristics
6HPL8QEDODQFHG 5LQJLQJ
In order to support "semi-unbalanced ringing" (dc bias equal to VBATR superimposed on the differential ringing signal), two of these outputs will be active high during the active ringing period on each channel (SPICK for channel 0 and SPICS for channel 1). This can be used to drive a relay via an external NPN transistor, as shown in Figure 4-3.
PROTECTION AW Rfeed
LINE NC BW Rfeed RLY 47 F +5 V VBATR RLY SPICK (LINE 0) OR SPICS (LINE 1) RLY NC
Figure 4-3. Application Suggestion for Semi-Unbalanced Ringing Injection
'& )((' &+$5$&7(5,67,&6
As shown in Figure 4-4, the SH-POTS chipset implements a constant-current feed. The limit current and the residual resistance (slope of the characteristic) are both programmable by the user. The dc characteristic falls into three regions. When the combination of line and subset result in a current less than the programmed limit current, the system behaves like a battery with a fixed feed resistance of 120 , and a voltage equivalent to the speech supply voltage (V BATS) minus the bias voltage on both lines (6 V nominal in total). Should line conditions permit a current that exceeds the programmed limit current, the system enters the constant-current feed mode described above. In order to protect the output stage in the transition region at higher line currents (in excess of 50 mA), a third region is defined, where the system synthesizes a fixed feed resistance of 200 . The slope of the voltage/current characteristic in the constant-current mode can be user-programmed to select the effective feed-resistance.
127(
The SHLIC device includes over-temperature protection, that activates at 165C in case of overheating of the device.
4-4
MS140132KT
Functional Characteristics of the SH-POTS System: DC Feed Characteristics
Iline (mA) 80
(PROGRAMMABLE) Rfeed
Rfeed = 200 Rfeed = 120
60
40
20
Vline (V) VFN VBATS
Figure 4-4. DC Feed Characteristics
Table 4-3. DC Feed Characteristics
[Rfeed = 60 Total (50 +10 Protection) x 2]
Parameter VbiasH VbiasL TOLICL TRfeedCL ICL Condition Bias voltage, A wire (Iline = 0) Bias voltage, B wire (Iline = 0) Current limit tolerance Tolerance on programmed Rfeed when in current-limit Current-limit, useful programmed range Min 2.5 2.5 -15 -15 20 Max 3.5 3.5 15 15 70 Unit V V % % mA
%DWWHU\ 9ROWDJH DQG 5HYHUVDO
The open-line voltage (i.e., the voltage seen on the line when on-hook) is user-selectable for each channel via an internal register. It can be either the ringing battery supply (most common use) or the speech battery supply. The speech battery supply is automatically selected when an off-hook condition is detected, independently of these control bits. The selected supply voltage is maintained when the on-hook signalling function (ADSI) is enabled. The polarity of the line feed can be dynamically controlled by the user. In the "normal" condition, the A wire is the most positive. Thus, reversal makes the B wire the most positive. Battery reversal is fast (audible), is controlled by programming an internal register, and is independent for both channels. The selected polarity is used in all states (on-hook, off-hook, ringing, etc.) except for on-hook signalling, which is in normal battery mode.
MS140132KT
4-5
Functional Characteristics of the SH-POTS System: AC Transmission Characteristics (MS140132KT System)
$& 75$160,66,21 &+$5$&7(5,67,&6 06.7 6<67(0
7UDQVPLW DQG 5HFHLYH )LOWHU &KDUDFWHULVWLFV
The SH-POTS chipset implements transmit and receive filters according to ITU-T (G.712). These filters can be reprogrammed by the user for specific requirements. Please contact a Motorola sales office for more information. The implemented default filter characteristics are shown in Figures 4-5 and 4-6.
(dB) -0.3 RECEIVE 0.0 0.35 0.55 0.75 1.0 25.0 1.5 FREQUENCY 200 300 400 600 2,400 3,000 3,600 3,400 4,000 4,600 16,000 (Hz) 12.5 TRANSMIT RECEIVE / TRANSMIT 12.5 [1 - SIN (4000-) 1200
] dB
Figure 4-5. Transmit and Receive Frequency Response (Default)
4-6
MS140132KT
Functional Characteristics of the SH-POTS System: AC Transmission Characteristics (MS140132KT System)
DELAY (s) 1800
1500
1200
900
600
300 FREQUENCY (Hz) 2600 2800
0 500 600 1000 2000
Figure 4-6. Relative Group Delay, Transmit and Receive Paths (Digital-to-Digital) Referred to 1 kHz
7UDQVPLW DQG 5HFHLYH *DLQ
Transmit (from analog subset towards the switching system) and receive gains are user-programmable, independently for both lines. The default values are 0 dBr in the transmit direction, and -7 dBr in the receive direction.
6RXUFH ,PSHGDQFH =&2
The central-office impedance, ZCO, is synthesized using digital signal processing techniques. This renders it very stable, and moreover, programmable by the user by means of coefficients which are loaded via the PCM/SPI. Real or complex ZCO impedances can be synthesized using the common three-element model (Rs, Rp, Cp; see Figure 4-7). The ZCO setting is common for both lines. Both real and complex ZCO impedances can be programmed to address the local requirements of specifications worldwide, and cover the following range. Using the default coefficient values, the return loss when measured against 600 (using 0 dBm input signal level) is better than 20 dB in the 300 to 3400 Hz band, and better than 10 dB at 10 kHz. Real impedances: 600 to 900 . Complex impedances: Rs from 160 to 500 Rp from 300 to 1000 Rp//Cp pole from 725 Hz to 5 kHz.
MS140132KT
4-7
Functional Characteristics of the SH-POTS System: Metering
CP RS RP
Figure 4-7. Three-Element ZCO Model
%DODQFH ,PSHGDQFH (FKR &DQFHOOHU
The balance impedance (model of the line plus set impedance used to separate the receive and transmit signals in the "hybrid") is independently programmable (though is the same for both channels). Default values offer echo return loss of better than 20 dB, though optimization to specific line and set characteristics may yield further improvement.
Table 4-4. Examples of ZCO Coefficients
Rs Belgium Germany Europe ZCO850 ZCO900 600 220 270 850 900 h0 Belgium Germany Europe ZCO850 ZCO900 4 -31 3 4 4 Rp 0 820 750 0 0 h1 -22 48 -23 -22 -22 Cp 0 115 nF 150 nF 0 0 h2 105 1 118 105 105 ZCOZCOSh Alfa3 ZCOA2 RZCO Gamma 0 0 0 0 0 h3 95 156 88 95 95 0 40 19 0 0 a0 0 0 0 0 0 3 9 7 0 0 c5 0 0 0 0 0 0 9 15 0 0 b0 0 0 0 0 0 ZCOAlfa3 0 5 4 0 0 Dzd0 1 0 0 1 1 Ftx 237 52 122 282 290 Dzd1 1 0 0 1 1 Ap 0 346 388 0 0 Nan 0 512 -179 0 0 ACG 103 125 125 123 126
0(7(5,1*
0HWHULQJ ,QMHFWLRQ
Metering pulses of selectable frequency (12 kHz or 16 kHz) and programmable amplitude can be injected into either analog channel independently. The width of the injected pulse is determined by the user (on/off mode), or by an internal timer (burst mode) which can be set by the user from 2 ms to 510 ms in steps of 2 ms. The metering signal is always a multiple of half metering periods. See Figure 4-8. Metering is initiated on a channel by an active low state on the corresponding MPI bit in the PCM/SPI C/I byte.
4-8
MS140132KT
Functional Characteristics of the SH-POTS System: Metering
ON/OFF MODE MPI
METERING
MPI
BURST MODE
tMburst METERING
Figure 4-8. Metering Pulse Timing Diagrams
The metering level on the line is set by: VLM = (VGEN ZM)/(ZM + ZCOM) where: VLM = metering pulse level on the line VGEN = set level of the metering generator ZM = impedance of the metering load ZCOM = CO impedance at the metering frequency. The metering level VGEN is selectable from 0 to a maximum level of 230 mVrms (500 m line with ZCO = 900 ) in 15 linear steps. The internal tolerance on the metering signal level is 10%.
MS140132KT
4-9
Functional Characteristics of the SH-POTS System: Tone Generation
0HWHULQJ &KDUDFWHULVWLFV
Table 4-5. Metering Characteristics (Determined by MC1420233 CODSP)
(Conditions: Refer to Section 5.2)
Parameter FML FMH SFN1 Condition Metering frequency, 12 kHz Metering frequency, 16 kHz Single-frequency noise, subharmonics for 12 kHz, 30 Hz to 12 kHz for 16 kHz, 30 Hz to 12 kHz Single-frequency noise, mixed products 12 kHz, 12 kHz to 20 kHz 12 kHz, 20 kHz to 132 kHz 16 kHz In-band noise due to metering signal Transient noise due to metering pulse Metering total harmonic distortion, 30 Hz to 132 kHz, out of CODSP Metering signal distortion at load Metering pulse amplitude, maximum level with ZCO = 900 , Rline = 130 Metering symmetry, A and B wires Single frequency noise, mixed products, 10 Hz to 4 kHz, Tx path Tolerance = 0.5%. Measured in accordance to ITU-T Specification 071 (Blue Book). On 200 . Tolerance = 10%. Tolerance = max 6%. Min 11,940 25,920 -- -- -- -- -- -- -- -- -- 207 24 -- Max 12,060 16,080 -69 -69 dBm0 -51 -69 -69 -60 -35 0.5 5 253 -- -63 dBmp dBm0 % % mVrms dB dBm 3 4 5 2 2 Unit Hz Hz dBm0 Note 1 1
SFN2
NMC NMT THDM DM VLM SYMM SFNTX NOTES: 1. 2. 3. 4. 5.
721( *(1(5$7,21
The SH-POTS system allows the injection of user programmable tones, independently per channel, for signalling or user test purposes. Per channel, a tone comprising two programmable (sine wave) frequencies and programmable amplitudes can be generated (in this way, the most common call-progress and information tones, melody notes, or DTMF tones can be synthesized). The tone signal is added to the speech signal (the user must be aware of possible clipping which may occur if high signal levels are programmed), or the speech signal can also be muted during a tone burst. The tone burst duration is under user control only (the control bits for mute and tone insertion occupy the same register, which simplifies the generation of tone bursts). The amplitude of each frequency within the tone can be independently set from 0 to the maximum level in 256 linear amplitude steps (8-bit value), with n = 63 corresponding to 0 dBm on the line. From this, the line signal level, VTL, for a given gain factor n is given by: VTL = 20 log(n/63) in dBm
4-10
MS140132KT
Functional Characteristics of the SH-POTS System: Tone Generation
or n = int(63 x 10^(Vtl/20) + 0.5) Table 4-6 lists values for n, for a range of tone signal levels. The tone frequency is given by: Fout = 250 x N / 256 Hz, where N is a 16-bit value (thus, N = 1024 yields a tone of 1 kHz) or N = int(Fout x 256/250 + 0.5) The tone generated has continuous phase if the programmed frequency is changed during the course of a tone (this is not so if the generator is stopped and restarted). Tables 4-7 and 4-8 list the values of N required to generate commonly occurring frequencies, and the resulting error.
Table 4-6. Tone Signal Levels (Common Values) (See Note)
dBm 3 1.5 0 -1.5 -3 -6 -8 -10 -15 -20 -30 -36 n 89 75 63 53 45 32 25 20 11 6 2 1 Actual 3.00 1.51 0.00 -1.50 -2.92 -5.88 -8.03 -9.97 -15.16 -20.42 -29.97 -35.99 Error (dB) 0.00 0.01 0.00 0.00 0.08 0.12 -0.03 0.03 -0.16 -0.42 0.03 0.01
NOTE: It is possible to generate tones of very high amplitude. The user must ensure that the amplitude parameter is programmed before the tone is enabled.
MS140132KT
4-11
Functional Characteristics of the SH-POTS System: Tone Generation
Table 4-7. Tone Generator Division Values for Common Frequencies from ETS-300-001 and DTMF Tones
Common Signalling Frequencies Frequency (Hz) 300.00 320.00 325.00 340.00 350.00 375.00 380.00 382.50 400.00 410.00 420.00 440.00 450.00 455.00 475.00 490.00 500.00 525.00 550.00 Frequency (Hz) 697.00 770.00 852.00 941.00 1209.00 1336.00 1477.00 1633.00 N 307 328 333 348 358 384 389 392 410 420 430 451 461 466 486 502 512 538 563 DTMF Tones N 714 788 872 964 1238 1368 1512 1672 Actual Frequency 697.266 769.531 851.563 941.406 1208.984 1335.938 1476.563 1632.813 Error (%) 0.04 -0.06 -0.05 0.04 0.00 0.00 -0.03 -0.01 Actual Frequency 299.805 320.313 325.195 339.844 349.609 375.000 379.883 382.813 400.391 410.156 419.922 440.430 450.195 455.078 474.609 490.234 500.000 525.391 549.805 Error (%) -0.07 0.10 0.06 -0.05 -0.11 0.00 -0.03 0.08 0.10 0.04 -0.02 0.10 0.04 0.02 -0.08 0.05 0.00 0.07 -0.04
4-12
MS140132KT
Functional Characteristics of the SH-POTS System: Tone Generation
Table 4-8. Required Frequency Setting Values (N) for a Melody Generator (Western Equal-Tempered Scale)
Octave 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 Note C C# D Eb E F F# G Ab A Bb B C C# D Eb E F F# G Ab A Bb B C C# D Eb E F F# G Ab A Bb B C C# D Eb Frequency (Hz) 261.626 277.183 293.665 311.127 329.628 349.228 369.994 391.995 415.305 440.000 466.164 493.883 523.251 554.365 587.330 622.254 659.255 698.456 739.989 783.991 830.609 880.000 932.328 987.767 1046.502 1108.731 1174.659 1244.508 1318.510 1396.913 1479.978 1567.982 1661.219 1760.000 1864.655 1975.533 2093.005 2217.461 2349.318 2489.016 N 268 284 301 319 338 358 379 401 425 451 477 506 536 568 601 637 675 715 758 803 851 901 955 1011 1072 1135 1203 1274 1350 1430 1515 1606 1701 1802 1909 2023 2143 2271 2406 2549 Actual 261.719 277.344 293.945 311.523 330.078 349.609 370.117 391.602 415.039 440.430 465.820 494.141 523.438 554.688 586.914 622.070 659.180 698.242 740.234 784.180 831.055 879.883 932.617 987.305 1046.875 1108.398 1174.805 1244.141 1318.359 1396.484 1479.492 1568.359 1661.133 1759.766 1864.258 1975.586 2092.773 2217.773 2349.609 2489.258 Error (%) 0.04 0.06 0.10 0.13 0.14 0.11 0.03 -0.10 -0.06 0.10 -0.07 0.05 0.04 0.06 -0.07 -0.03 -0.01 -0.03 0.03 0.02 0.05 -0.01 0.03 -0.05 0.04 -0.03 0.01 -0.03 -0.01 -0.03 -0.03 0.02 -0.01 -0.01 -0.02 0.00 -0.01 0.01 0.01 0.01 (Middle-C)
MS140132KT
4-13
Functional Characteristics of the SH-POTS System: CODSP Clock Recovery PLL
Table 4-8. Required Frequency Setting Values (N) for a Melody Generator (Western Equal-Tempered Scale) (continued)
Octave 5 5 5 5 5 5 5 5 Note E F F# G Ab A Bb B Frequency (Hz) 2637.020 2793.826 2959.955 3135.963 3322.438 3520.000 3729.310 3951.066 N 2700 2861 3031 3211 3402 3604 3819 4046 Actual 2636.719 2793.945 2959.961 3135.742 3322.266 3519.531 3729.492 3951.172 Error (%) -0.01 0.00 0.00 -0.01 -0.01 -0.01 0.00 0.00
&2'63 &/2&. 5(&29(5< 3//
The CODSP device derives its internal clocks from the PCM/SPI input by means of a PLL. The PLL automatically detects the clock mode in use, and sets the multiplication factor accordingly. The PLL loop filter requires an external capacitor as shown in the application schematic.
4-14
MS140132KT
6(&7,21
(/(&75,&$/ &+$5$&7(5,67,&6
$%62/87( 0$;,080 5$7,1*6
Operation of the device at or near these conditions is not guaranteed. Sustained exposure to these limits will adversely affect device reliability.
Table 5-1. Absolute Maximum Ratings
Parameter Battery voltage BATR (ref. to VSSB) of SHLIC Battery voltage BATS (ref. to VSSB) of SHLIC Difference between the batteries BATR and BATS, BATR-BATS of SHLIC VDD5A (ref. to VSSA) of SHLIC VSSB (ref. to VSSA) of SHLIC Ambient temperature under bias of SHLIC Maximum absolute power dissipation, TA = 85C VDD3A,VDD3D to CODSP Voltage on any device pin (see Note) of CODSP Function temperature under bias of CODSP Storage temperature Lead temperature (soldering 10 s) NOTE: Except special 5 V tolerant I/Os of CODSP as noted in Table 3-1. Tstg VDD3 Vin Symbol BATR BATS DBAT VDD5A VSSB TA Min -75 -35 -40 -0.5 -0.5 -40 -- VSS - 0.3 VSS - 0.3 -55 -65 -- Max 0.5 0.5 0.5 7 0.5 85 1.3 4 VDD3 + 0.3 150 150 300 Unit V V V V V C W V V C C C
23(5$7,1* &21',7,216
Operating ranges define the limits for functional operation and parametric characteristics of the device as described in this document, and for the reliability specifications. Correct functioning outside of these limits is not implied. Total cumulative exposure outside the normal power supply voltage range or ambient temperature under bias, must be less than 0.1% of the normal useful life as defined in Table 5-1.
MS140132KT
5-1
Electrical Characteristics: Thermal Shutdown SHLIC
Table 5-2. Operating Conditions
(All Voltages Referenced to VSSA = VSSB or VSS = VSSA, as Appropriate) Limits Symbol BATR BATS DBAT VDD5A Trange VDD3D VDD3A Parameter Ringing battery voltage Speech battery voltage Difference between the batteries BATR and BATS, BATR-BATS Supply voltage SHLIC (ref. to VSSA) Operating temperature range VDD of CODSP (3.3 V 8%) Min -72 -35 -40 4.75 -40 3.036 Typ -65 -32 -35 5 -- 3.3 Max -18 -18 0 5.5 85 3.564 Unit V V V V C (Note) V
NOTE: See Section 5.4; maximum power dissipation is dependent on maximum ambient temperature.
7+(50$/ 6+87'2:1 6+/,&
Thermal limiting circuitry on chip of the SHLIC will shut down the circuit at a junction temperature of about 165C. The device should never be run at this temperature. Operation above 145C junction temperature might degrade device reliability. Thermal resistance = 55C/w typ.
7UDQVLHQW (QHUJ\ &DSDELOLW\
During testing, each device termination withstands being shorted to the supply voltages or ground as specified below. The shorting must be limited to 1 s. Shorted to VSSA, VDD5A or VSSB: VAG, PU, RNG, BR, TST, TA, DCC, DCO, DCI, Tx to Rx Shorted to VSSA, VSSB or BATS: AW, BW, SA to SB
'& &+$5$&7(5,67,&6 0& 6+/,& 81/(66 27+(5:,6( 127('
Unless otherwise stated, these characteristics apply for the operating conditions specified in Section 5.2. All parameters are explicitly or implicitly tested during production at the operating conditions unless they are marked with an asterisk (*), where they are guaranteed by design. Parameters marked with a double asterisk (**) are meant as user information only. Tests are performed using an equivalent of the application schematic.
5-2
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
Table 5-3. Power Supply Currents
Limits Symbol IBATR Parameter BATR current (IL = 0) Test Condition Power RNG = 0 Up RNG = 1 Power RNG = 0 Down RNG = 1 IBATS BATS current (IL = 0) Power RNG = 0 Up RNG = 1 Power RNG = 0 Down RNG = 1 IVDD VDD current (IV3 = 0) Power-up Power-down PCC Power dissipation of CODSP (@ 3.45 V VDD3A and VDD3D) Power-down Power-up 1 line active* Power-up 2 lines active Min -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 0.35 3.5 0.35 2.5 3.5 3.5 1.5 -- 3 2.5 -- -- -- Max 0.5 5.0 0.5 3.5 5 5 2.5 0.5 5.5 4 30 140 180 Unit mA mA mA mA mA mA mA mA mA mA mW mW mW
NOTES: 1. IL is the line current; i.e., these parameters are measured without line current. 2. IV3 is the load current in pin V3. 3. The maximum values in the table are valid for the full battery voltage ranges: -18 V to -72 V for ringing battery BATR. -18 V to -35 V for battery BATS. (BATR must always be the most negative one.) 4. In case of sleep mode activation. See Tables 6-5 and 6-7 for programming values.
Table 5-4. SHLIC Dissipation
Parameter Maximum operating power dissipation, TA = 70C Symbol Pmax_op Value 1.2 Unit W
The specifications for power dissipation imply that in ring mode, the active ring phase must at least be four times shorter than the non-active ring phase. The maximum duration of the active ring phase must be below 2 s.
3RZHU2Q 5HVHW
Table 5-5 shows the power reset threshold for VDD5A of the SHLIC. As long as VDD5A is below the reset threshold, SHLIC is held in power-down, and the output pins AW and BW are high impedance. The CODSP uses a separate input pin, PWRS, for system reset at power-up.
MS140132KT
5-3
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
Table 5-5. Power-On Reset Characteristics
Limits Symbol Parameter Test Condition Min 3.0 10 1.6 Typ 3.5 -- -- Max 4.0 -- 1.7 Unit V ms V
VDDPWR Threshold voltage for power reset on VDD of SHLIC tPWRS VPWRS Active low pulse width on PWRS of CODSP Threshold voltage for reset on PWRS of CODSP
9'' 5HJXODWRU
This series regulator of the SHLIC can be used to provide the supply voltage for the CODSP or other 3.3 V devices.
Table 5-6. VDD3 Regulator Characteristics
Limits Symbol VDD3 Iload PSRR LREG Parameter VDD3 output voltage Load current range Signal rejection VDD to VDD3 Load regulation Frequency range 0 to 10 kHz Load current range from 5 to 50 mA Load current range from 0 to 50 mA VDD3 shorted to VSSA Test Condition Load current IV3V between 0 and 50 mA Min 3.05 0 20 -1 -- 70 Typ 3.3 -- -- -- 100 -- Max 3.55 50 -- 1 -- 200 Unit V mA dB nF mA
Cload (**) Maximum load capacitance ICC(*) Current limitation shorted output
5-4
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
Table 5-7. Voltage Characteristics A Wire (AW), B Wire (BW)
Test Condition Symbol VAWN VBWN VAWR VBWR VAW_H VBW_H VHWPD VLWPD VAWring VBWring Parameter Normal DC-bias on AW (ref. VSSB) Normal DC-bias on BW (ref. BAT) Reverse polarity DC-bias on AW (ref. BAT) Reverse polarity DC-bias on BW (ref. VSSB) DC bias on AW in Act_H mode (TST = 1, ref. VSSB) DC bias on BW in Act_H mode (TST = 1, ref. BAT) Voltage level high wire (IL < 5 mA) Voltage level low wire (IL < 5 mA), ref. BAT DC-level both wires in ringing mode (TST = 0) PU 1 1 1 1 1 1 0 0 1 BR 0 0 1 1 x x x x 0 RNG 0 0 0 0 1 1 0 0 1 Min -3.5 2.5 2.5 -3.5 -4 2 -0.8 -- BAT/2 -2% Limits Typ -3.1 3 3 -3.1 -3 3 -0.5 0.5 BAT/2 Max -2.7 3.5 3.5 -2.7 -2 4 -- 0.8 BAT/2 2% Unit V V V V V V V V V
NOTE: These bias values are only valid if both DCC and Rx are biased at VAG voltage level.
Table 5-8. Impedance Characteristics A Wire (AW), B Wire (BW)
Limits Symbol ZA(B)WO (*) ZA-BWO (*) ZHWOD ZLWOD ZOMD Parameter Output impedance at AW (BW) (power-up) Tracking of the output impedance on AW and BW Output impedance on high wire (power-down) Output impedance on low wire (power-down) Matching output impedance low versus high wire (power-down) Output current in and out AW (BW) with OT (overtemperature) detected Test Condition 0 mA < IL < 70 mA 0 < f < 16 kHz 0 mA < IL < 70 mA 0 < f < 16 kHz PU = 0 PU = 0 PU = 0 Min -- -- 5 5 -70 Typ -- -- -- -- -- Max 1.5 0.3 130 130 70 Unit
IA(B)OC IA(B)HIMP
A(B)W_VSSB and A(B)W_BATS
-700
--
700
A
MS140132KT
5-5
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
Table 5-9. Rx, Tx Characteristics
Limits Symbol ZTx (*) VOTx Parameter Output impedance at Tx Offset voltage on Tx (PU=1) (ref. VAG) Tx output current capability Rx input voltage range (ref. VAG) Rx input impedance f = 1 kHz Test Condition f = 1 kHz SA shorted to AW and SB to BW, DCI to VDD3, DCO to VAG Min -- -20 Typ -- 0 Max 10 20 Unit mV
IOUTTx VRx(*) ZRx
-1 -1 20
-- -- --
0.05 1 --
mA V k
'&2 '& /HYHOV ,PSHGDQFHV
These limits are generally transparent to the user, but are given here for information.
Table 5-10. DCO Characteristics
Limits Symbol ZDCO (*) VODCO IOUTDCO (*) ZDCI Parameter Output impedance at DCO Offset voltage on DCO (ref. VAG) DCO output current capability Input impedance at DCI f = 1kHz SA shorted to AW and SB to BW Test Condition Min -- -20 -1 210 Typ -- 0 -- -- Max 10 20 0.05 -- Unit mV mA k
9$* $QDORJ *URXQG ,QSXW
The analog ground is typically half the voltage of the VDD3 output voltage. It is the reference for all analog interfacing between SHLIC and the CODSP. VAG is provided by the CODSP.
Table 5-11. VAG Characteristics
Limits Symbol Parameter Test Condition Min 1.53 VAG = 1.65 V -- Typ 1.65 -- Max 1.77 0.5 Unit V mA
VVAG (**) Voltage level at VAG pin CODSP IVAG VAG input current SHLIC
5-6
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
'& /RRS )LOWHU
These limits are generally transparent to the user, but are given here for information.
Table 5-12. DC Loop Filter Characteristics
Limits Symbol VDCLF1 VDCLF2 Parameter DCLF1 output voltage (ref. VSSB) DCLF2 output voltage (ref. BAT) Test Condition RNG = 0, PU = 1 RNG = 0, PU = 1 RNG = 0, PU = 1 RNG = 0, PU = 1 Min -3.5 2.5 0.6 0.6 Typ -3.1 3.0 1 1 Max -2.7 3.5 1.4 1.4 Unit V V M M
ZDCLF1S Output impedance at DCLF, VDCLF - VDCLF1 < 0.5 V ZDCLF2S Output impedance at DCLF, VDCLF2 - VDCLF < 0.5 V
'&& ,QSXW 3LQ
These limits are generally transparent to the user, but are given here for information.
Table 5-13. DCC Input Characteristics
Limits Symbol VDCC IINDCC Parameter DCC input voltage range (ref. VAG) DCC input current, VDCC = VAG + 1 V Test Condition RNG = 0, PU = 1 RNG = 0, PU = 1 Min -1 -- Typ -- 4 Max 1 10 Unit V A
NOTE: Forcing DCC positive (ref. VAG) will result in a smaller voltage between the A and B wire. If too large of a signal is applied at DCC, both wires are clamped at the same voltage (only a small residual voltage remains on the line).
MS140132KT
5-7
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
&KDUDFWHULVWLFV IRU WKH 'LJLWDO ,2 3LQV
These include CODSP, plus TST, PU, BR, RNG of SHLIC.
Table 5-14. Digital I/O Characteristics
Limits Symbol VIL VIH IIL IIH CINP (*) RPD VOL Parameter Low-level input voltage High-level input voltage Low-level input current (except PU, see RPD below) High-level input current (except PU, see RPD below) Input capacitance Pull-down resistance at pin PU Output level PU pin, driven low Over-temperature OT activated, IPU = 0.2 mA, tested at high temperature only VDD = 5.25 V VDD = 5.25 V Test Condition Min -- 2.0 -1 -1 -- 18 -- Typ -- -- -- -- -- 30 -- Max 0.8 -- 1 1 7 40 0.5 Unit V V A A pF k V
VIL VIH VOL VOH Cin Cout IIH
Low-level input voltage, CODSP High-level input voltage, CODSP Low-level output voltage, CODSP High-level output voltage, CODSP Input pin capacitance, CODSP (see Note) Load capacitance, CODSP High-impedance leakage current VOH = 5.5 V off state
-- 0.8 x VDD3D -- -- -- -- -10
-- -- -- -- -- -- --
0.2 x VDD3D -- 0.4 5.25 4 100 10
V V V V pF pF A
NOTE: Excluding package and measured at 0 V.
Table 5-15. Sense Bridge Inputs Characteristics
Limits Symbol RAW-SB RSA-BW Parameter Bridge resistance from AW to SB Bridge resistance from BW to SA Test Condition VDD, VAG = 0 V, 25C VDD, VAG = 0 V, 25C Min 205 205 Typ 257 257 Max 309 309 Unit k k
5-8
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
7HVW 6ZLWFK
The internal test switch is between pins SB and SSB. Connecting an external load between SSB and SA allows test of the transmission characteristics in (simulated) off- and on-hook conditions. The typical on-resistance of the test switch is around 75 , and has to be taken into account when defining the external load. The test switch is on when RNG = 0, PU = 1, TST = 1, BR = 0.
Table 5-16. Test Switch Characteristics
Limits Symbol ISWoff VSWon Parameter Switch leakage current Voltage drop over test switch Test Condition |VSSB - VSB| < 72 V I SW = 80 mA ISW = 20 mA (VSSB - VSB > 0 V) Min -- 4 1 Typ -- -- -- Max 5 9 3 Unit A V V
NOTE: The test switch is normally off when VDD is below the reset level. If the battery voltages are sufficient, the switch remains on, if it was on before VDD went below the reset level.
%DWWHU\ 6ZLWFK
This switch is activated during ringing or when the higher on-hook voltage is selected (RNG = 1). When active, BATR is connected to the internal battery supply line VBAT. In other cases (RNG = 0), the switch is open; VBAT is now connected to BATS via an internal diode.
Table 5-17. Ringing Battery Switch Characteristics
Limits Symbol IBSWoff (*) IREVBATS (*) VDRBATS IBSon VBSWon Parameter Leakage current battery switch (RNG = 0) Reverse current BATS diode (RNG = 1) Forward drop BATS diode Current capability battery switch Voltage drop over battery switch (RNG = 1) Load current < 80 mA Test Condition BATR = -72 V, BATS = -32 V BATR = -72 V, BATS = -32 V Load current < 80 mA Min -- Typ -- Max 5 Unit A
-- -- 0 --
-- 0.85 -- 1
5 1.2 80 2
A V mA V
MS140132KT
5-9
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
$& &+$5$&7(5,67,&6 6+/,&
Unless otherwise stated, the characteristic limits apply over the operating conditions specified in Section 5.2 and each combination of the drive bits. All parameters are specified in the presence of a longitudinal current of max 5 mA and a dc current of between 0 mA and the current limit. The behavior of the chip in the presence of longitudinal voltages is not tested in production. The different gains in the signal paths are shown in Figure 5-1. The values of the gains are given in Table 5-18.
AWbias RPROT RB AW + VAB + RPROT RB BW BWbias G1 SENSE BRIDGE G5 DCO Tx G3 - G2 GR Rx
ZL
VL
G4
DCC I/O TO ADSP (REF. VAG)
Figure 5-1. Block Diagram Showing Gains in Various Signal Paths in SHLIC Table 5-18. Typical Gains
Gain G1 G1 G2 G3 G4 G5 GR GR Factor 1.66 0.079 2 -2 15 -1/8 1 35/2
5-10
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
The gains in Table 5-18 are not tested. They are mentioned for information only. The pin-to-pin gains in Table 5-20 (GRX, GTX, etc.) are tested and guaranteed. In case of ringing, the receive gain is changed from GR to GR, the transmit gain factor G1 is changed to G1. The default test condition of the input bits is: PU = 1, RNG = 0, BR = 0/1. DCC is shorted to VAG. NOTE 0 dBm: 1 mW in 600 ohms.
5HFHLYH 3DWK
The following equation is valid for an open loop configuration. This does not incorporate the ZCO synthesis, which is defined by the feedback from Tx to Rx. This function is performed in the CODSP. GRX = VAB = GR(G3 - G2) VRX
7UDQVPLW 3DWK
The following equation is valid under open loop conditions. Vx 2RB = G1 VL ZL
GRX =
2YHUSRZHU DQG 6KRUW &LUFXLW 3URWHFWLRQ
In power-down, the DC-loop current limitation is not active. The line current is limited directly through the line drivers. The AW and BW outputs are fully protected against short circuits to a voltage between VSSA/VSSB and BATR (see Figure 5-2). The current flowing from (or into) AW and/or BW is limited to a value ILW/IHW as long as the junction temperature TJ < 165C (electronic current limitation). The values for ILW/IHW for different conditions are given in the table below. If TJ rises above 165C (15%) the output drivers' outputs are made high impedance. Current can only flow in or out of the internal protection diodes, in case VSA and/or VSB exceeds the range between VSS and BATR. The currents should, however, be limited externally (internal clamping diodes protection) (see Section 2.2).
MS140132KT
5-11
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
VSSB
RS1 = RS2 0.3
RS1 AW
BATR VSSB VAW
RS2 BW - + VSB VSSB VSA - +
VBW BATR
Figure 5-2. Short Circuit Protection
Table 5-19. Short Circuit Protection Characteristics
Limits Symbol ILW Parameter Short circuit peak current, power-up, sink current Short circuit peak current, power-down, sink current IHW Short circuit peak current, power-up, source current Short circuit peak current, power-down, source current Test Condition PU = 1 PU = 0 PU = 1 PU = 0 Min -145 -65 95 20 Typ -120 -45 120 45 Max -95 -20 145 65 Unit mA mA mA mA
5-12
MS140132KT
Electrical Characteristics: DC Characteristics (MC1430132 SHLIC, Unless Otherwise Noted)
2))+22. &+$5$&7(5,67,&6 06.7 6<67(0
Table 5-20. Off-Hook Characteristics (MS140132KT System) (Conditions: Refer to Section 5.2)
Parameter GTX
Condition Relative gain, transmit direction Gain programming step Step accuracy Gain tolerance (ref. programmed value) Relative gain, receive direction Gain programming step Step accuracy Gain tolerance (ref. programmed value) Long-term gain stability Gain tracking, Tx path 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Gain tracking, Rx path 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 Intermodulation distortion, Tx path Intermodulation distortion, Rx path Signal to total distortion ratio, Tx (gain = 0 dB) 0 to -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -45 dBm0 Signal to total distortion ratio, Rx (gain = -7 dB) 0 to -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -45 dBm0 Single frequency noise 300 to 3400 Hz, all out-of-band frequencies 700 to 1100 Hz in-band 300 to 3400 Hz Longitudinal balance Resistor matching
Min -6 -- -- -0.5 -12 -- -- -0.5 -0.5 -0.3 -0.6 -1.6 -0.3 -0.6 -1.6 -- -- 35 34.7 32.9 24.9 19.9 35 33.8 28.8 19.5 14.5 -- -- 1% 0.1%
Max 1 0.25 0.1 0.5 1 0.25 0.05 0.5 0.5 0.3 0.6 1.6
Unit dB
Note 1
GRX
dB
1
dGLT GTTX
dB dB
2 3
GTRX
dB 0.3 0.6 1.6 -45 -50 -- -- -- -- -- dB -- -- -- -- -- dB -40 -49 40 46 dB dB dBm0 dBm0 dB
3
IMDTX IMDRX SDTX
4 4 5
SDRX
5
SFNRX
NOTES: 1. 2. 3. 4.
User programmable. Covers variations within the permitted ranges of supply voltage and temperature during any one year. Referred to the gain at 1020 Hz applied to the input at a level -10 dBm0. Intermodulation distortion measured for all intermodulation products of any non-harmonically related frequencies in the range 300 to 3400 Hz for levels between -4 and -21 dBm0. 5. Intermodulation distortion measured for all intermodulation products of a frequency in the range 300 to 3400 Hz at -9 dBm0 and 50 Hz at -23 dBm0.
MS140132KT
5-13
Electrical Characteristics: Off-Hook Detection
2))+22. '(7(&7,21
Each channel has one I/O pin used for signalling purposes, DET*. With this, one signalling bit from the SH-POTS chipset can be routed to this output: off-hook detection (LS*), alarm (AL*), or ring phase (RPH*). Register 5 [4-2] defines which bit. DET* is the default functionality. This value can be changed as follows.
OUTPUT ACTIVE
SPIin
1
1
1
0
0
1
0
1
1
0
0
X
X
X
0
0
CH*
Valid Combinations:
X 1 0 0
X 0 1 0
X Bit to DET* Pin 0 LS* 0 AL* 1 RPH*
Figure 5-3. Write Signalling Register
See the MS140131KT/D data sheet for a functional explanation of the signalling bits. The other bits should not be changed. DET0 (default) is the on/off hook and ring trip detection open drain output for line 0. When off-hook, DET0 goes low. When on-hook, DET0 is high impedance. DET1 (default) is the corresponding on/off hook and ring trip detection output for line 1.
352*5$00,1* 7+( 3&0 &/2&. )5(48(1&<
The PCMCLK clock is used for generation of the internal 512 kHz clock required for the PCM/SPI interface. Register 7 has to be programmed to the expected value.
5-14
MS140132KT
6(&7,21
'(7$,/(' 352*5$00,1* '(6&5,37,21
63, ,17(5)$&(
The data on pin SPIin is shifted in on the rising edge of SPICLK. The data on SPIout occurs at the falling edge of SPICLK. The first bit is shifted out on the falling edge of SPICLK after CH* became active (= low level) or at the falling edge of CH* after SPICLK became active (= low level). The user should ensure that the data on SPIout is stable at moment of use: the master device will normally read in the data of SPIout on the rising edge of the clock (equal to SPICLK on the SH CODSP). Both select signals CH0 and CH1 can not be simultaneously activated. Note that CH* may remain low 8 or 16 bits during shift out of data via SPIout depending on the type of read request.
MS140132KT
6-1
Detailed Programming Description: SPI Interface
1 2 SPICLK 6 CH0, CH1 8 SPIin 10 11 SPIout 7 6 7 9 6
3 4
5
7
5 11 5
4
3
2
1
0 13
4
3
2
1
0
Figure 6-1. SPI Bus Timing Parameters Table 6-1. SPI Bus Timing Characteristics
No. 1 2 3 4 5 6 7 8 9 10 11 13 Symbol 1/tSPICLK tSPICLK_H tSPICLK_L tSPICLK_R tSPICLK_F tCH_SU tCS_H tSPIIN_SU tSPIIN_H tSPIOUT_V tSPIOUT_V tSPIOUT Parameter SPICLK Frequency SPICLK High Time SPICLK Low Time SPICLK Rise Time SPICLK Fall Time CH* Setup Time Before SPICLK Rising Edge CH* Hold Time After SPICLK Rising Edge SPIin Data Setup Time Before SPICLK Rising Edge SPIin Data Hold Time After SPICLK Rising Edge SPIout Data Valid After CH* Falling Edge (see Notes 1, 2, 4) SPIout Data Valid After SPICLK Falling Edge (see Notes 1 ,2, 4) SPIout High-Z After CH* Rising Edge (see Notes 2, 3) Min 0 50 50 -- -- 50 50 50 50 0 0 0 Typ 2.048 tSPICLK/2 tSPICLK/2 -- -- -- -- -- -- -- -- -- Max 8.192 -- -- 15 15 -- -- -- -- 50 50 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values guaranteed with a maximum capacitive load of 50 pF. 2. On condition the other pin (= SPICLK or CH*) is already low. 3. When CH* transits to high at the end: bit 0 stays valid until CH* becomes high or next negative transition on SPICLK occurs. 4. SPIout valid means the moment VOL level is reached for a low level or the moment the driver becomes high impedance (High-Z) for a high level.
MS140132KT
6-2
Detailed Programming Description: PCM Interface
3&0 ,17(5)$&(
2 1 3 4 5
PCMCLK 9 7 FRAME 10 11 PCMin 12 PCMout 7 7 6 12 6 5 2 1 0 5 2 1 0 13 8 6
Figure 6-2. PCM Bus Timing Parameters Table 6-2. PCM Bus Timing Characteristics
No. 1 Symbol 1/tPCLK Parameter PCMCLK Frequency ( Note 1) PCMCLK Accuracy 2 3 4 5 6 7 8 9 10 11 12 13 tSFSCKL tHCKFSL tHCKFSH tSINCK tHCKIN tDCKDXV tDCFDXD tWCLKH tWCLKL tR tF Width of PCMCLK High Width of PCMCLK Low PCMCLK Rise Time PCMCLK Fall Time FRAME Period Setup Time From FRAME High to PCMCLK Low Hold Time of PCMCLK Low to FRAME Low Hold Time From PCMCLK Low to FRAME High Setup Time From PCMin to PCMCLK Low Hold Time From PCMCLK Low to PCMin Invalid Delay Time From PCMCLK to PCMout Valid (Notes 2, 3) Delay Time From PCMCLK to PCMout Disabled (High-Z) 50 50 50 50 50 0 0 Min 512 -100 50 50 -- -- Typ 2048 -- -- -- -- -- 125 -- -- -- -- -- -- -- Max 8192 100 -- -- 15 15 -- -- -- -- -- -- 50 50 Unit kHz ppm ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. PCMCLK must be an integer multiple of 512 kHz. 2. PCMout timing is defined with capacitive load = 50 pF. 3. PCMout valid means the moment VOL level is reached for a low level or the moment the driver becomes high impedance (High-Z) for a high level.
6-3
MS140132KT
Detailed Programming Description: PCM Interface
)81&7,21$/ '(6&5,37,21 2) 7+( 352*5$00,1* ,17(5)$&( 63,
The SPI block operates on a totally independent clock, SPICLK. This clock can vary from dc up to 8192 kHz. If the pin CH0 or CH1 is pulled low (= activation), the clock is gated through the interface block and the other CH* pin is deactivated. With this, the registers of the PCM2GCI interface block can be programmed. The data is shifted in via the SPIin pin at the rising edge of SPICLK. The data is always transmitted as bytes (or multiples). The first byte received via the SPIin pin is always the command byte. The first 2 bits define the type of command.
B7 0 0 1 1 B6 0 1 0 1 Software Reset Write Control Word Access CODEC Memory Access Interface Block Registers + Idle Command Function
These two bits are interpreted on-line and represent a specific action. The table below describes the valid commands, a short functional description and action description from the SPI interface block:
Valid Command 00000000 01XXXXXX 10000000 10001BBB 10011BBB 110YYYYY 111YYYYY 11111111 Software Reset Write Control Word ID Request Write Request Read Request Interface Block Registers: Read Request Interface Block Registers: Write Request Idle Command: Can Be Used When SPIout Data is Expected Function
SPIout is a three-state serial data (8-bits, MSB first) output. The output is activated at the moment data is available after a GCI monitor command (ID or read request) or after an interface-block-read request. The data is shifted out of SPIout on the SPICLK falling edge when CH* is low. At that moment, data on SPIin is not accepted by the interface. When both CH* are high, SPIout is in high impedance state. Before data can be shifted out on SPIOUT, CH* is set high for a small time. The same CH* signal as used for the command must also be used for the data that will be shifted out of SPIout. At power-up, the chipset is programmed to power down, and the output SPIout is in the high-impedance state (refer also to the memory map). In case multiple bytes are required for execution of a command (e.g., writing data in the CODSP memory), these can be send in separate cycles, or within the same activation of CH0 or CH1. Only the command 01* is dependent on which CH0 or CH1 is activated. None of the bytes received via the SPIin are echoed via the SPIout; only the requested read-data is returned.
MS140132KT
6-4
Detailed Programming Description: Programmability of the SH-POTS Chipset
BUSY Function: This signal (when low) indicates that the SPI interface is busy with transmitting program data to the required location inside the CODSP. The time BUSY is low depends on the type of command. For example, the control word takes maximum 12 FRAME periods. When BUSY is low due to a write of the control word via one channel (CH0 or CH1), a control word via the other channel (CH1 or CH0) can be written. The commands are executed in the same order as they are programmed. When BUSY is low, due to execution of a previous command, the user must wait until BUSY is high again before issuing any new command.
352*5$00$%,/,7< 2) 7+( 6+3276 &+,36(7
The following sections describe how the SH-POTS chipset can be programmed.
6RIWZDUH 5HVHW RI WKH &KLSVHW
The software reset unconditionally forces the chipset into the reset state. It can be activated by writing 1 byte via either of the two CH* signals.
EXECUTION RESET
SPIin
0
0
0
0
0
0
0
0
CH*
Figure 6-3. Software Reset
&RQWURO :RUG
The control word provides an easy and fast access to the operating states of the chipset. Both lines have thier own dedicated control word. The difference is usually chosen by the use of the corresponding CH0 signal for line 0 and CH1 for line 1. It is also possible to address both lines by any CH* signal activation. The control word is a 1-byte command.
6-5
MS140132KT
Detailed Programming Description: ID Request
SPIin
0
1
X
X
X
X
X
X READY FOR NEW DATA
CH*
BUSY
TRANSFER BUSY
NOTE: Activating CH0 or CH1 program the corresponding channel.
Figure 6-4. Write Control Word
The bits have following functions.
Bit 7 6 5 4 3 2 1 0 Activation of Always 0 for Control Word Always 1 for Control Word TBD (see Note) TBD (see Note) Polarity Reversal Power-Up (ADSI Mode) Ringing Mode Metering 1 1 1 1 1 1 When
NOTE: Bits should always be written 0, foreseen for future extension.
$FFHVV WR WKH &2'63 0HPRU\
The first byte of these commands all begin with B7-6 = 10. (They are exactly the same commands as the MS140131KT SH-POTS chipset with GCI interface.). The BUSY signal becomes low after acceptance of the commands (when all required bytes are received) and remain low during execution of the command. When the result is available at the SPIout pin, the BUSY signal becomes high again.
,' 5(48(67
There is one required byte. The command returns 2 bytes that are the software revision of the CODSP (see explanation in the MS140131KT SH-POTS datasheet). The command itself is not echoed.
MS140132KT
6-6
Detailed Programming Description: Read Request
START GCI TRANSFER SPIin 1 0 0 0 0 0 0 0
GCI OPERATION FINISHED
CH* BUSY
SPIout
ID OF CODSP
Figure 6-5. ID Request
5($' 5(48(67
ADDRESS HIGH ADDRESS LOW
nnnnnnnn
SPIin CH* BUSY SPIout
10011BBB nnnnnnnn
ADDRESS HIGH
10011BBB nnnnnnnn
ADDRESS LOW
nnnnnnnn
DATA HIGH
dddddddd
DATA LOW
dddddddd
Figure 6-6. Read Request
This is a 3-byte command, which returns 2 bytes; the codec-memory contents at the specified address. The read request is exactly the same as in the SH-POTS GCI interface description. See explanation in the MS140131KT SH-POTS datasheet. The command itself is not returned.
6-7
MS140132KT
Detailed Programming Description: Write Request
:5,7( 5(48(67
ADDRESS HIGH SPIin CH* BUSY SPIout
10011BBB nnnnnnnn
ADDRESS LOW
nnnnnnnn
DATA HIGH
dddddddd
DATA LOW
dddddddd
Figure 6-7. Write Request
This is a 5-byte command (see explanation in the MS140131KT SH-POTS datasheet).
352*5$00,1* 27+(5 )($785(6 9,$ 7+( 63, ,17(5)$&(
The SPI interface has a memory map in which the setup for the PCM interface can be changed, as well as the clock frequency and the signaling pin. See Section 6.12 for a description of the memory map.
:ULWH 63, ,QWHUIDFH 0HPRU\
Each address can be written to via the SPI interface independently. The command to be used is 111YYYYY + byte to be loaded in the register. The address is defined by YYYYY. It is possible to write more than 1 byte with the same command. For this, the relevant CH* signal has to be pulled low for a multiple of 8 clocks. Each time, the byte with the address = previous +1 is written. For valid addresses, see memory map.
MS140132KT
6-8
Detailed Programming Description: Idle Command
DATA LATCHED SPIin CH* SPIout REGISTER WRITE REQUEST TYPE 1 DATA LATCHED SPIin CH* SPIout REGISTER WRITE REQUEST TYPE 3 (ALSO FUNCTIONAL IF CH* IS NOT GOING HIGH)
111YYYYY DATA ADD. YYYYY 111YYYYY DATA ADD. YYYYY
DATA LATCHED SPIin CH* SPIout REGISTER WRITE REQUEST TYPE 2 DATA LATCHED DATA LATCHED DATA LATCHED
111YYYYY DATA ADD. YYYYY
DATA ADD. YYYYY+1 DATA ADD. YYYYY+2
DATA ADD. YYYYY+X
Figure 6-8. Register Write Request Types
5HDG 63, ,QWHUIDFH 0HPRU\
Read operation will return the data of the corresponding register. The data is sampled during the bytes following the request, on condition that the idle command is written during the access of the SPI interface.
IDLE COMMAND SPIin 1 1 0 Y Y Y Y Y 1 1 1 1 1 1 1 1
CH*
SPIout
d
d
d
d
d
d
d
d
DATA FROM REGISTER YYYYY
Figure 6-9. Register Read Request
,'/( &200$1'
This command is used to read the data from the SPIout pin and has no programming effect in the PCM2GCIM interface block. FF is returned via SPIout if no data is available.
6-9
MS140132KT
Detailed Programming Description: Registers in the SPI Interface Block
5(*,67(56 ,1 7+( 63, ,17(5)$&( %/2&.
There are 11 addressable registers: from 0x05 to 0x0F (hex), and 0x11(hex). These registers are used to control the functions of other interface blocks: PCM interface, GCI interface, and clock generator. These registers are controlled by the SPI interface.
Addresses 5 6 7 8-D E-F 11 Control of: Which Signaling Signal is Directed to DET* Direct C/I bits programming PCMCLK Frequency PCM Interface Control Word Registers Direct C/I Bits Monitoring
Table 6-3 lists the memory map and function.
Table 6-3. Memory Map: SPI
Address (Hex) 5 6 7 Function Write Registers DET* pins control register. See Section 5.7. Normal SH-POTS GCI Downstream C/I bits (B7-2): see SH-POTS, excluding the AE bits. PCMCLK clock frequency: the user must program the applied clock frequency at PCMCLK pin as a multiple of 512 kHz. Program B7-4 = B3-0: -- 1 x 512 to 15 x 512 write 0001 to 1111 -- 16 x 512 write 0000 PCMin delay versus FRAME rising edge for line 0 per byte (B6-0: channel 0 - 127), default is 0 bytes. B7 is always = 0. PCMout delay versus FRAME rising edge for line 0 per byte (B6-0: channel 0 - 127), default is 0 bytes. Activation of the channel = B7, default = 0 = deactivated. PCM delay versus FRAME rising edge for line 0 per bit, default is B7-5 = 0; B4 = 1/2 clock period only for PCMout, other bits are for expansion and should be programmed 0. PCMin delay versus FRAME rising edge for line 1 per byte (B6-0: channel 0 - 127), default is 1 byte. B7 is always = 0. PCMout delay versus FRAME rising edge for line 1 per byte (B6-0: channel 0 - 127), default is 1 byte. Activation of the channel = B7, default = 0 = deactivated. Default 90 FF (non-active) 44 (2048 kHz) Content When Read Idem Idem Idem
8
00
Idem
9
00
Idem
A
00 (no shift)
Idem
B
01
Idem
C
01
Idem
MS140132KT
6-10
Detailed Programming Description: Programming the PCM Interface
Table 6-3. Memory Map: SPI (continued)
Address (Hex) D Function Write Registers PCM delay versus FRAME rising edge for line 1 per bit, default is B7-5 = 0; B4 = 1/2 clock period only for PCMout, other bits are for expansion and should be programmed 0. Control word Channel 0. See Section 6.4.2. Control word Channel 1. See Section 6.4.2. NA. Remark: Writing to this register may put the system into an undefined mode. Default 00 (no shift) Content When Read Idem
E F 11
40 40 FF
Idem Idem Normal GCI upstream C/I bits (B7-2): see the MS140131KT datasheet. Some bits can be sent to outputs DET*. Bits 1-0 are always High.
Registers 0 to 4 and higher then 11 are for internal use only. Writing to these registers may put the system into an undefined mode.
352*5$00,1* 7+( 3&0 ,17(5)$&(
The PCM interface consists of inputs PCMCLK, FRAME, PCMin, and output PCMout. PCMCLK controls the internal operation of the PCM interface and shifts/latches the PCM data from PCMin in the interface on its falling edge, and sends the PCM data onto PCMout* on its rising edge. The data is read/written in the B-channels of the GCI interface via the control block. FRAME is an 8-kHz frame-sync pulse. Its rising edge determines the beginning of the PCM data transfer out of PCMout and into PCMin. A register in the interface block defines the shift between this FRAME signal and the corresponding PCM channel. Default values are as defined in the interface block register map. The FRAME pulse is one or more PCMCLK periods long, with timing relationships as specified in Figure 6-10. The PCMout open drain output buffer is enabled with reference to the rising edge of FRAME or the rising edge of PCMCLK, depending on whichever comes later, and the first bit clocked out is the PCM sign bit. The following 7 rising edges of PCMCLK shift out the remaining 7 bits, MSB first. Default compression of PCM data is A-law as defined in the CODSP core. The PCMout output is disabled by the falling edge of PCMCLK following the eighth rising edge. A rising edge of the FRAME will cause PCM data at PCMin to be latched after the last of the next 8 falling edges of PCMCLK. See register 8-D for a description of how the activation and time delay can be programmed. Figure 6-10 is an example of the default timing and programming a different setup.
6-11
MS140132KT
Detailed Programming Description: Memory Map of the CODSP
FRAME
PCMCLK
PCMout
7 654321076543210
HIGH IMPEDANCE
PCMin
7 654321076543210 DEFAULT TIMING PCM INTERFACE
DON'T CARE
FRAME
PCMCLK
PCMout
76543210
76543210
HIGH IMPEDANCE
PCMin
76543210
76543210
DON'T CARE
TIMING EXAMPLE PCM INTERFACE: IDL 10-BIT MODE TIMING
NOTE: Default values + Program Reg. A = 20 and D = 60 for timing shift Program Reg. 9 = 80 for activation line 0 Program Reg. C = 81 for activation line 1.
Figure 6-10. Timing Example of PCM Interface
0(025< 0$3 2) 7+( &2'63
Global memory map and MemID definitions: * * * * All addresses can be read and written, though writing to locations or individual bits which are not described here may result in unpredictable behavior. The default parameter and coefficient values that are used at startup and after reset are listed in the following tables. The memory block to be accessed is given as part of the READ or WRITE command (see above) as the "B" bits in the command byte. The control registers of the SH-POTS system, accessed via the SPI, are organized in a number of memory blocks. Within each block, a number of addresses are used directly to control the operation of specific functions of the SH-POTS system.
MS140132KT
6-12
Detailed Programming Description: Data RAM -- MemID = 2
Table 6-4. Memory Map for CODSP
MemID 2 Memory Data RAM Start Address 0x 02 0000 Memory Contents C-code read/write data C-code stack region C-code IRQ stack region Filter coefficients Data packet buffers Label vectors, FIFO control
4 5
Coprocessor Coef RAM Shared RAM
0x 04 0000 0x 05 0000
'$7$ 5$0 0(0,'
Table 6-5. Data RAM: Memory Map
Address 00 (0x0000) 01 (0x0001) 02 (0x0002) 03 (0x0003) 04 (0x0004) 05 (0x0005) 06 (0x0006) 07 (0x0007) 08 (0x0008) 09 (0x0009) 10 (0x000A) 11 (0x000B) 12 (0x000C) 13 (0x000D) 14 (0x000E) 15 (0x000F) 16 (0x0010) 17 (0x0011) 18 (0x0012) 19 (0x0013) 20 (0x0014) 21 (0x0015) 22 (0x0016) 23 (0x0017) 24 (0x0018) IDC0 IAC0 IAC1 TG1 TG0 MS1 MS0 TestTone_Ampl1_L0 TestTone_Ampl1_L1 TestTone_Ampl2_L0 TestTone_Ampl2_L1 IDC1 RTDAC_ThresholdLow RTDAC_Debouncetime Ringing_DC_Offset Ringing_Off_Period CurLim_Rlarge CurLim_Threshold RW RIL RM RF Tx Gain 0 Tx Gain 1 Rx Gain 0 Rx Gain 1 Dzd1 Dzd0 Td1 Td0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Br0 Br1 1 0 Bbs0 Bbs1 Bsa0 Bs0 Bsa1 Bs1 Tst0 Sh0 Tst1 Sh1
Ringing_Amplitude Ringing_On_Period LBO RTDAC_ThresholdHigh RTDAC_GapTime AlarmReg
6-13
MS140132KT
Detailed Programming Description: LBO Register
Table 6-5. Data RAM: Memory Map (continued)
Address 25 (0x0019) 26 (0x001A) 27 (0x001B) 28 (0x001C) 29 (0x001D) 30 (0x001E) 31 (0x001F) 32 (0x0020) Sleep2 Pd1 Pd0 DialP_SatTxLevel DialP_DebTime Rzd1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TestTone_Freq1_L0 TestTone_Freq1_L1 TestTone_Freq2_L0 TestTone_Freq2_L1 ACG Rzd0 Sleep1
NOTE: Bit positions and memory locations not documented must not be changed.
/%2 5(*,67(5
This register controls various loopback modes, as well as the routing of the GCI B channels to or from the physical line analog channels. The bits are codes as shown in Table 6-6.
Table 6-6. LBO Register Description
Mode Normal Simplex loop B2 Simplex loop B1 Simplex loop B1 and B2 Duplex loopback Reserved Reserved Swap mode NOTE: BnDown: BnUp: Tx(m): Rx(m): D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Tx(0) -> B2Up Tx(1) -> B1Up B1Down -> Rx(1) B2Down -> Rx(0) GCI Side Tx(0) -> B1Up Tx(1) -> B2Up Tx(0) -> B1Up B2Down -> B2Up B1Down -> B1Up Tx(1) -> B2Up B1Down -> B1Up B2Down -> B2Up B2Down -> B1Up B1Down -> B2Up Analog Side B1Down -> Rx(0) B2Down -> Rx(1) B1Down -> Rx(0) Tx(1) -> Rx(1) Tx(0) -> Rx(0) B2Down -> Rx(1) Tx(0) -> Rx(0) Tx(1) -> Rx(1) Tx(0) -> Rx(1) Tx(1) -> Rx(0)
GCI B channel 1 or 2, downstream direction. GCI B channel 1 or 2, upstream direction. Analog "transmit" signal (upstream direction), line 1 or 2. Analog "receive" signal (downstream direction), line 1 or 2.
MS140132KT
6-14
Detailed Programming Description: Alarm Bits
$/$50 %,76
* After initialization (e.g., due to a hardware reset), the CODSP itself will make the upstream Alarm bit active, and set the AlarmReg with an InitRequest value (i.e., "1xx"). The Alarm bit will remain active until the InitRequest is cleared by the PCM/SPI supervisor (indicating that the supervisor has done the necessary reinitialization of system parameters). In order to check the contents of the AlarmReg, execute the following PCM/SPI command: ReadRequest ( MemId=2, Add=0x0010 ); This results in a four-nibble value; e.g., "0xabgd," read by the supervisor. * In order to clear the InitRequest alarm, in principle, one must only clear one bit. Therefore, the supervisor should execute the following commands: NewValue = "0xabgd" AND "0xFFFB"; WriteRequest ( MemId=2, Add=0x0010, NewValue ); * Note that the other bits in the alarm register are updated by the DSP at a 8 kHz rate, and that they are only used by the PCM/SPI supervisor; therefore, the other bits might also be overwritten for one cycle, clearing all bits (inclusive the InitRequest bit) in one command: WriteRequest ( MemId=2, Add=0x0010, 0x0000 );
*
0($1,1* $1' '()$8/7 9$/8(6 2) 7+( 3$5$0(7(56
Table 6-7. Data RAM: Description and Default Values
Name (Note 1) Sh0, Sh1 Tst0, Tst1 Br0, Br1 Bs0, Bs1 Address 00, 01 00, 01 00, 01 00, 01 Position 0 1 2 3 Description Mapping Default 0 (normal) 0 (open) 0 (non rev.) 0 (NonAct_L) 0 (ActAdsi_L) 0 (ActRng_Sph_L) SHLIC test mode control 0: normal mode bit 1: test mode SHLIC test switch control bit SHLIC battery reversal control bit 0: open switch 1: closed switch 0: non-reversed 1: reversed
SHLIC battery selection 0: BATS selection L control bit for NonAct_X 1: BATR selection H variant SHLIC battery selection 0: BATS selection L control bit for ActAdsi_X 1: BATR selection H variant SHLIC battery selection 0 = "00":BATS L control bit for 1 = "01":BATR H ActRng_Sph_X variant 2 = "10":BATS + bias LA 3 = "11":BATR + bias HA
Bsa0, Bsa1
00, 01
4
Bbs0, Bbs1
00, 01
6:5
6-15
MS140132KT
Detailed Programming Description: Meaning and Default Values of the Parameters
Table 6-7. Data RAM: Description and Default Values (continued)
Name (Note 1) Tx_Gain_0 Tx_Gain_1 Rx_Gain_0 Rx_Gain_1 Dzd1, Dzd0 Td1, Td0 CurLim_Threshold Address 03 04 05 06 07 08 09 Position 15:0 Description Gain factor in Tx direction for Line0 and Line1 Gain factor in Rx direction for Line0 and Line1 Mapping
20 log Tx-Gain_* 320
Default 320 (0 dB) 384 ( - 7dB) 1 (disabled) 0 (enabled) 51 (32 mA) 64 (3 k)
15:0
-7 + 20 log
Rx-Gain_* 384
1:0 1:0 7:0
Disable digital ZCO path 0: enable 1: disable Disable Tx path at pdm level Current limitation threshold parameter Current limitation RLarge resistance parameter (internal resistance) Ringing frequency 0: enable 1: disable val = 0 ... 127 unit = 0.63 mA (eq = 0 ... 80 mA) val = 0 ... 210 unit = 47 (eq = 0 ... 10 k) 0 = "00": 16 Hz 1 = "01": 20 Hz 2 = "10": 25 Hz 3 = "11": 50 Hz 0: on/off mode 1: burst mode 0: non-interleaved 1: interleaved 0: sine wave 1: trapezoidal wave val = 0 ... 255 unit = 194 mV rms
CurLim_RLarge
09
15:8
RF
10
1:0
3 (50 Hz)
RM RIL RW Ringing_Amplitude Ringing_DC_Offset
10 10 10 11 11
2 3 5 7:0 15:8
Ringing mode Enable interleaved ringing Ringing waveform Amplitude of ringing signal
0 (on/off) 1 (interleaved) 0 (sine) 255 (max ampl) 0 (no offset) 32 (1 s) 96 (3 s) 0 (no loop) 27 (43.2 mA) 7 (11.2 mA) 10 (1.25 ms)
DC offset of ringing val = 0 ... 255 signal unit = 250 mV (Between A and B wire) Length of active ringing phase to be used in burst mode Length of silent ringing phase to be used in burst mode GCI loopback register (encoding see below) Threshold level high during ringing Threshold level low during ringing val = 0 ... 255 unit = 32 ms val = 0 ... 255 unit = 32 ms val = 0 ... 15 val = 0 ... 255 unit = 1.6 mA val = 0 ... 255 unit = 1.6 mA
Ringing_On_Period
12
7:0
Ringing_Off_Period
12
15:8
LBO RTDAC_ThresholdHigh RTDAC_ThresholdLow RTDAC_GapTime
13 14 14 15
3:0 7:0 15:8 7:0
Gaptime during RTDAC val = 0 ... 255 peak detection unit = 125 s
MS140132KT
6-16
Detailed Programming Description: Meaning and Default Values of the Parameters
Table 6-7. Data RAM: Description and Default Values (continued)
Name (Note 1) RTDAC_Debouncetime AlarmReg IDC1 IDC0 IAC0 IAC1 TG1, TG0 MS1, MS0 TestTone_Ampl1_L0 TestTone_Ampl1_L1 TestTone_Ampl2_L0 TestTone_Ampl2_L1 TestTone_Freq1_L0 TestTone_Freq1_L1 TestTone_Freq2_L0 TestTone_Freq2_L1 ACG Pd1, Pd0 Sleep2 (Note 2) Sleep1 (Note 2) Rzd1, Rzd0 DialP_SatTxLevel Address 15 16 17 17 18 19 20 20 21 22 23 24 25 26 27 28 29 30 30 30 30 31 Position 15:8 2:0 7:0 15:8 15:0 15:0 3, 2 1, 0 7:0 7:0 15:0 15:0 7:0 11:10 13:12 2:0 4:3 15:0 Description Deb. time during RTDAC Alarm status register (encoding) Mapping val = 0 ... 255 unit = 125 s val = 0 ... 7 Default 240 (30 ms) 4 (InitReq'st) 0 0
DC line current of Line1, val = 0 ... 127 sampled at 2 kHz unit = 0.63 mA DC line current of Line0, val = 0 ... 127 sampled at 2 kHz unit = 0.63 mA
AC line current of Line0, unit = 215/1.6 V @ Tx 0 sampled at 8 kHz AC line current of Line1, unit = 215/1.6 V @ Tx 0 sampled at 8 kHz Tone generator control bit for Line1 and Line0 Mute speech control bit for Line1 and Line0 0 : do not add tone 1 : add tone 0 : pass speech 1 : mute speech 0 (no tone) 0 (no mute) 63 (0 dBm) 63 (0 dBm) 1024/256 (1 kHz) 512/256 (500 Hz) 103/128 (600 ) 0 (disable) 00 active 0 (0% sleep) 0 (enabled) 8192 (400 mV) 40 (5 ms)
Amplitude of first sine for val = 0 ... 255 Line0 and Line1 Amplitude of second val = 0 ... 255 sine for Line0 and Line1 Frequency of first sine for Line0 and Line1 unit = 250 Hz/256
Frequency of second unit = 250 Hz/256 sine for Line0 and Line1 Rx amplitude correction val = 0 ... 255/128 for ZCO synthesis Power denial mode Line1 Low power activation Sleep factor to be used when one line inactive Disable analog ZCO path 1 = enable 0 = disable 00 = inactive 11 = active val = 0 ... 7 eq = 0 ... 70% sleepy 0: enable 1: disable
Tx saturation level to be unit = 48.83 V @ Tx used for dial pulse detection Debounce time to be used for dial pulse detection unit = 125 s
DialP_DebTime
32
15:0
NOTES: 1. Parameter names with 0 or 1 at the end refer to the analog Line0 or Line1. 2. In low power applications: recommended program value is sleep 1 = 5 combined with sleep 2 = 3 will save power consumption when only one line off-hook.
6-17
MS140132KT
Detailed Programming Description: Coprocessor Coefficient RAM -- MemID = 4
&2352&(6625 &2()),&,(17 5$0 0(0,'
Access is similar to that of the data RAM parameters. Note, however, that the PCM/SPI commands work with 2-byte values whereas the memory contains only 3-nibble values. Because all values are <12, 0>, the most significant nibble of the 2-byte PCM/SPI value will be a sign-extension of the 12-bit value. In the case of a ReadRequest; the most significant nibble of a WriteRequest will be neglected.
Table 6-8. Coprocessor Coefficient RAM: Memory Map
Address 00 (0x0000) 01 (0x0001) 02 (0x0002) 03 (0x0003) 04 (0x0004) 05 (0x0005) 06 (0x0006) 07 (0x0007) 08 (0x0008) 09 (0x0009) 10 (0x000A) 11 (0x000B) 12 (0x000C) 13 (0x000D) 14 (0x000E) 15 (0x000F) 16 (0x0010) 17 (0x0011) 18 (0x0012) 19 (0x0013) 20 (0x0014) 21 (0x0015) 22 (0x0016) 23 (0x0017) 24 (0x0018) 25 (0x0019) 26 (0x001A) 27 (0x001B) 28 (0x001C) 11 10 9 8 7 6 5 4 3 2 1 0 Rx32KFilter coefficient : r0 r1 r4 s1 s2 r2 r3 r5 s3 s4 m0 m1 u0 u1 Hyb16KFilter coefficient : h0 h1 h2 h3 a0 c5 b0 Tx32KFilter coefficient : t0 t1 t8 q1 q2 t2 t3 t9
MS140132KT
6-18
Detailed Programming Description: Meaning and Default Values of the Parameters
Table 6-8. Coprocessor Coefficient RAM: Memory Map (continued)
Address 29 (0x001D) 30 (0x001E) 31 (0x001F) 32 (0x0020) 33 (0x0021) 34 (0x0022) 35 (0x0023) 36 (0x0024) 37 (0x0025) 38 (0x0026) 39 (0x0027) 40 (0x0028) 41 (0x0029) 42 (0x002A) 43 (0x002B) 44 (0x002C) 45 (0x002D) 46 (0x002E) 11 10 9 8 7 6 q3 q4 t4 t5 t10 q5 t6 t7 t11 q6 q7 c2 c3 ZcoTxFilter coefficient : Ftx Ap NAn Constants : HLF ONE_EIGHT 5 4 3 2 1 0
0($1,1* $1' '()$8/7 9$/8(6 2) 7+( 3$5$0(7(56
Table 6-9. Coprocessor Coefficient RAM: Description and Default Values
Name r0 r1 r4 s1 s2 r2 r3 r5 s3 s4 Address 00 01 02 03 04 05 06 07 08 09 Position 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 Description Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Mapping unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 Default int96 int78 int96 int642 int263 int256 int303 int256 int746 int450
6-19
MS140132KT
Detailed Programming Description: Meaning and Default Values of the Parameters
Table 6-9. Coprocessor Coefficient RAM: Description and Default Values (continued)
Name m0 m1 u0 u1 h0 h1 h2 h3 a0 c5 b0 t0 t1 t8 q1 q2 t2 t3 t9 q3 q4 t4 t5 t10 q5 t6 t7 t11 q6 q7 c2 c3 Ftx Address 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Position 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 11:0 Description Rx filter coefficient Rx filter coefficient Rx filter coefficient Rx filter coefficient Echo cancelling coefficient Echo cancelling coefficient Echo cancelling coefficient Echo cancelling coefficient Echo cancelling coefficient Echo cancelling coefficient Echo cancelling coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient Tx filter coefficient ZCOTx filter coefficient Mapping unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 Default int512 int512 int0 int0 int109 int2 int8 int32 int127 int512 int157 int48 int37 int48 int728 int439 int390 int492 int390 int573 int227 int64 int128 int64 int442 int384 int768 int384 int962 int458 int512 int512 int237
MS140132KT
6-20
Detailed Programming Description: Shared Memory -- MemID = 5
Table 6-9. Coprocessor Coefficient RAM: Description and Default Values (continued)
Name Ap NAn HLF ONE_EIGHT Address 43 44 45 46 Position 11:0 11:0 11:0 11:0 Description ZCOTx filter coefficient ZCOTx filter coefficient Constant definition Constant definition Mapping unit = intval / 512 unit = intval / 512 unit = intval / 512 unit = intval / 512 Default int0 int0 int256 int64
6+$5(' 0(025< 0(0,'
Table 6-10. Shared Memory: Memory Map
Address 85 (0x0055) 86 (0x0056) 87 (0x0057) 88 (0x0058) 89 (0x0059) 90 (0x005A) 91 (0x005B) 94 (0x005E) NOTE: Bit positions and memory locations not described here must not be changed. ZcoShAlfa3 15 14 13 VLM 12 11 10 HT 9 8 Deb 7 6 5 4 MF SR* SR* HSD_ThresholdLow RTD_ThresholdLow 3 MM SR* SR* 2 1 0
SpiDo SpiDi SpiSk SpiCs SpiSe RBD HSD_ThresholdHigh RTD_ThresholdHigh MeteringDutyCycle ZcoA2 RZco Rxd*
Alo*
Sleep* ZcoAlfa3 TL
ZcoGamma
6-21
MS140132KT
Detailed Programming Description: Meaning and Default Values of the Parameters
0($1,1* $1' '()$8/7 9$/8(6 2) 7+( 3$5$0(7(56
Table 6-11. Shared Memory: Description and Default Values
Name VLM Address 85 Position 14:11 Description Metering amplitude (unit value = depending on ZCO) HSD debounce time Mapping val = 0 ... 15 Default 3
HT
85
10:9
0 = "00": 8 ms 1 = "01" : 24 ms 2 = "10" : 16 ms 3 = "11": 64 ms 0 : 0 ms 1 : 30 ms 0 : 12 kHz 1 : 16 kHz 0 : burst mode 1 : on/off mode
2 (16 ms)
DEB MF MM SPIDO SPIDI SPISK SPICS SPISE RBD
85 85 85 86 86 86 86 86 86
8 4 3 15 14 13 12 11 10
RTD debounce time Metering frequency Metering mode SPI Dout port SPI Din port SPI SK port SPI CS port SPI port selection Disable automatic ring activation of SPICK and SPICK
1 (30 ms) 1 (16 kHz) 1 (on/off) 0 0 0 0 0
1 = disabled 0 = enabled
0 (enabled) 0 0 (no reset) 16 (10 mA) 10 (6.3 mA) 16 (10 mA) 10 (6.3 mA) 150 (300 ms)
SR (Note 1) Soft Resets (Note 2)
86 86
5:4 1:0 5:0
Software resets of SID1, SID0, 1 = reset block CP, GCI 0 = no reset Reset ability of HW blocks (SID0, SID1, MRT, LS, CP, GCI) HSD high threshold 0: no reset 1: reset block val = 0 ... 127 unit = 0.63 mA = 0 ... 80 mA val = 0 ... 127 unit = 0.63 mA = 0 ... 80 mA val = 0 ... 127 unit = 0.63 mA = 0 ... 80 mA val = 0 ... 127 unit = 0.63 mA = 0 ... 80 mA
HSD_ThresholdHigh
87
13:7
HSD_ThresholdLow
87
6:0
HSD low threshold
RTD_ThresholdHigh
88
13:7
RTD high threshold
RTD_ThresholdLow
88
6:0
RTD low threshold
MeteringDutyCycle
89
15:8
Length of the metering burst to val = 0 ... 255 be used in "burst" metering unit = 2 ms mode = 0 ... 510 ms
MS140132KT
6-22
Detailed Programming Description: Meaning and Default Values of the Parameters
Table 6-11. Shared Memory: Description and Default Values (continued)
Name ZcoShAlfa3 ZcoA2 RxD (Note 1) ALO (Note 2) Sleep (Note 2) RZco ZcoGamma ZcoAlfa3 TL Address 90 90 90 90 90 91 91 91 94 Position 15:1 13:7 6 4 2:0 11:8 7:4 3:0 1:0 Description Central office impedance parameter Central office impedance parameter RxDisable at input of analog part Analog loopback at pdm Sleep factor actually used by the processor Central office impedance parameter Central office impedance parameter Central office impedance parameter Transcode law selection Mapping (Note 1) (Note 1) 0: enabled Rx path 1: disable Rx path 0: disabled loop 1: enable loop val = 0 ... 7 = 0 ... 70% sleepy (Note 1) (Note 1) (Note 1) 0 = "00": A Law 1 = "01": Law 2 = "10": Linear Default 0 (600 ) 0 (600 ) 0 (enabled) 0 (disabled) 0 (0% sleep) 3 (600 ) 0 (600 ) 0 (600 ) 0 (A-Law)
NOTES: 1. Examples of other ZCO parameters are listed in Table 4-4. Otherwise, contact a Motorola sales office. 2. Do not change these values.
6-23
MS140132KT
6(&7,21
0(&+$1,&$/ 63(&,),&$7,216
0& 3$&.$*( ',0(16,216
FU SUFFIX TQFP PACKAGE CASE 824D-02
4X
0.2 (0.008) H L-M N
44 1
4X 11 TIPS
0.2 (0.008) T L-M N
-X-
X=L, M, N
PLATING
BASE METAL
F
34 33
C L
AB AB VIEW Y
40X
G
-L-
3X
VIEW Y
-M- B V
0.20 (0.008)
ROTATED 90 _ CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.53 (0.021). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.45 0.75 0.30 0.40 0.80 BSC 0.09 0.20 0.50 REF 0.09 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ 0_ --- 12_REF 12_REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.063 0.002 0.006 0.053 0.057 0.012 0.018 0.018 0.030 0.012 0.016 0.031 BSC 0.004 0.008 0.020 REF 0.004 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ 0_ --- 12_REF 12_REF
B1
11 12 22 23
V1
-N- A1 S1 A S
4X
(q 2)
C -H- -T-
SEATING PLANE 4X
VIEW AA 0.1 (0.004) T
(q 3)
C2 0.05 (0.002) (W)
S
q1
2X R
R1
0.25 (0.010)
GAGE PLANE
C1 VIEW AA
(K) E (Z)
q
DIM A A1 B B2 C C1 C2 D E F G J K R1 S S1 U V V1 W Z
q q1 q2 q3
MS140132KT
CCCC EEE CCCC EEE
J D
M
U
T L-M
S
N
SECTION AB-AB
7-1
Mechanical Specifications: MC1420233 Package Dimensions
0& 3$&.$*( ',0(16,216
DW SUFFIX SOIC PACKAGE CASE 751F-05
A
D
28 15 M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.13 0.29 B 0.35 0.49 C 0.23 0.32 D 17.80 18.05 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 L 0.41 0.90 q 0x 8x
1
14 PIN 1 IDENT
B
A
0.25 M
E
H
B
L 0.10 C C
SEATING PLANE
e B 0.025
M
A1
q
CA
S
B
S
7-2
MS140132KT
Mechanical Specifications: MC1420233 Package Dimensions
5(&200(1'(' 3$' /$<287 )25 /($' 74)3 0&
A
B
Solder Pad Size: W = 0.55 mm x L = 2.0 mm Solder Pad Pitch: 0.8 mm (center to center) Toe to Toe Dimension: A = 14.2 mm x B = 14.2 mm
Figure 7-1. Recommended Pad Layout for 44-Lead TQFP MC1420233
MS140132KT
7-3
Digital DNA is a trademark of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors/ (c) Motorola, Inc., 2001
MS140132KT/D

▲Up To Search▲

Price & Availability of MS140132KT

	To Download MS140132KT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .