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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9230/D Rev 3, 03/2003
800 MHz Low Voltage PECL Clock Synthesizer
The MPC9230 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications.
MPC9230
800 MHZ LOW VOLTAGE CLOCK SYNTHESIZER
* 50 MHz to 800 MHz synthesized clock output signal * Differential PECL output * LVCMOS compatible control inputs * On-chip crystal oscillator for reference frequency generation * Alternative LVCMOS compatible reference clock input * 3.3V power supply * Fully integrated PLL * Minimal frequency overshoot * Serial 3-wire programming interface * Parallel programming interface for power-up * 32 lead LQFP and 28 PLCC packaging * SiGe Technology * Ambient temperature range 0C to +70C * Pin and function compatible to the MC12430
FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A FN SUFFIX 28 LEAD PLCC PACKAGE CASE 776
Features
Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC - 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
(c) Motorola, Inc. 2003
1
MPC9230
XTAL_IN XTAL_OUT FREF_EXT
XTAL
10 - 20 MHz
/16
VCO Ref
/2
PLL
800-1600 MHz
FB
/1 /2 /4 /8
11 00 01 10
OE
FOUT FOUT
VCC XTAL_SEL /0 to /511 9-Bit M-Divider 9 VCC P_LOAD S_LOAD LE P/S 0 Bit 5-13 S_DATA S_CLOCK VCC M[0:8] N[1:0] OE 1 Bit 3-4 14 Bit Shift Register 0 1 Bit 0-2 M-Latch
/2
Test 2 N-Latch 3 T-Latch
TEST
Figure 1. MPC9230 Logic Diagram
M[8]
M[7]
M[6]
M[5] 18
FOUT
FOUT
TEST
VCC
GND
VCC
GND
S_CLOCK S_DATA S_LOAD VCC_PLL FREF_EXT XTAL_SEL XTAL_IN
25 26 27 28 1 2 3 4 5 XTAL_OUT
24
23
22
21
20
19 18 17 16 N[1] N[0] M[8] M[7] M[6] FOUT 13 12 M[5] M[4] FOUT VCC 30 31 32 GND TEST VCC VCC GND 14 25 26 27 28 29
24
23
22
21
20
19
17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT
M[4] 13 12 11 10 9 8 TIMING SOLUTIONS XTAL_IN
N[1] 2
MPC9230
15
6 OE
7 P_LOAD
8 M[0]
9 M[1]
10 M[2]
11 M[3]
1
N[0] 3
NC
MPC9230
4
5
6
7
VCC_PLL
S_CLOCK
VCC_PLL
S_LOAD
Figure 2. MPC9230 28-Lead PLCC Pinout (Top View)
Figure 3. MPC9230 32-Lead Package Pinout (Top View)
MOTOROLA
2
FREF_EXT
XTAL_SEL
S_DATA
MPC9230
Table 1. Pin Configuration
Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL S_LOAD Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVPECL LVPECL LVCMOS LVCMOS Crystal oscillator interface Alternative PLL reference input Differential clock output Test and device diagnosis output PLL reference select input Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. This input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation PLL positive power supply (analog power supply) Function
P_LOAD
Input
1
LVCMOS
S_DATA S_CLOCK M[0:8] N[1:0] OE
Input Input Input Input Input
0 0 1 1 1
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
GND VCC VCC_PLL
Supply Supply Supply
Supply Supply Supply
Ground VCC VCC
Table 2. Output frequency range and PLL Post-divider N
N 1 0 0 1 1 0 0 1 0 1 Output di i i O t t division 2 4 8 1 Output f O t t frequency range 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz
Table 3. Function Table
Input XTAL_SEL OE 0 FREF_EXT Outputs disabled, FOUT is stopped in the logic low state (FOUT = L, FOUT = H) 1 XTAL interface Outputs enabled
TIMING SOLUTIONS
3
MOTOROLA
MPC9230
Table 4. General Specifications
Symbol VTT MM HBM LU CIN JA Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Input capacitance LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board 200 2000 200 4.0 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 23.0 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 26.3 Min Typ VCC - 2 Max Unit V V V mA pF C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Inputs Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 Condition
JESD 51-6, 2S2P multilayer test board
JC
LQFP 32 Thermal resistance junction to case
Table 5. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 4.6 VCC + 0.3 VCC + 0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C)
Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE) VIH VIL Input High Voltage Input Low Voltage Input Currenta 2.0 VCC + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VCC or GND
IIN Differential clock output FOUTb VOH VOL Output High Voltage Output Low Voltage VCC-1.02 VCC-1.95
VCC-0.74 VCC-1.60
V V
LVPECL LVPECL
Test and diagnosis output TEST VOH VOL Output High Voltage Output Low Voltage VCC-1.02 VCC-1.95 VCC-0.74 VCC-1.60 V V LVPECL LVPECL
Supply current ICC_PLL ICC a. b. Maximum PLL Supply Current Maximum Supply Current 20 110 mA mA VCC_PLL Pins All VCC Pins
Inputs have pull-down resistors affecting the input current. Outputs terminated 50W to VTT = VCC - 2V.
MOTOROLA
4
TIMING SOLUTIONS
MPC9230
Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0C to +70C)a
Symbol fXTAL fREF fVCO fMAX Characteristics Crystal interface frequency range FREF_EXT reference frequency range VCO frequency rangec Output Frequency N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) Min 10 10 800 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) 20 20 20 20 20 80 90 130 160 60 70 120 140 50 55 0.3 Typ Max 20 Unit MHz Condition
(fVCO,MAX/M)4b MHz 1600 800 400 200 100 10 MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps ps ps ps ps ps ps 20% to 80%
fS_CLOCK tP,MIN DC tr, tf tS
Serial interface programming clock frequencyd Minimum pulse width Output duty cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD)
tS tJIT(CC)
Hold Time Cycle-to-cycle jitter
tJIT(PER)
Period Jitter
a b c d
tLOCK Maximum PLL Lock Time 10 ms AC characteristics apply for parallel output termination of 50 to VTT. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M / 4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See application section for more details.
TIMING SOLUTIONS
5
MOTOROLA
MPC9230
Programming the MPC9230 Programming the MPC9230 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: fOUT = (fXTAL / 16) (4 M) / (2 N) or fOUT = (fXTAL / 8) M / N (1) (2) to match the VCO frequency range of 800 to 1600 MHz in order to achieve stable PLL operation: MMIN = 4fVCO,MIN / fXTAL and MMAX = 4fVCO,MAX / fXTAL (3) (4)
For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M=200 and M = 400. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 2 M / N (5)
where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured Table 8. MPC9230 Frequency Operating Range
VCO frequency for an crystal interface frequency of M 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 370 380 390 400 410 420 430 440 450 510 M[8:0] 010100000 010101010 010110100 010111110 011001000 011010010 011011100 011100110 011110000 011111010 100000100 100001110 100011000 100100010 100101100 100110110 101000000 101001010 101010100 101011110 101110010 101111100 110000110 110010000 110011010 110100100 110101110 110111000 111000010 111111110 800 825 850 875 925 950 975 1000 1025 1050 1075 1100 1125 1275 810 840 870 900 930 960 990 1020 1050 1110 1140 1170 1200 1230 1260 1290 1320 1350 1530 805 840 875 910 945 980 1015 1050 1085 1120 1155 1190 1225 1295 1330 1365 1400 1435 1470 1505 1540 1575 800 840 880 920 960 100 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1480 1520 1560 1600 810 855 900 945 990 1035 1080 1125 1170 1215 1260 1305 1350 1395 1440 1485 1530 1575 10 12 14 16 18 20 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1600
Output frequency for fXTAL=16 MHz and for N = 1 2 4 8
400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 740 760 780 800
200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 370 380 390 400
100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 185 190 195 200
50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 82.5 85 87.5 92.5 95 97.5 100
MOTOROLA
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TIMING SOLUTIONS
MPC9230
Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz
N 1 0 0 1 1 0 0 1 0 1 Value 2 4 8 1 M M/2 M/4 2M 200 - 400 MHz 100 - 200 MHz 50 - 100 MHz 400 - 800 MHz 1 MHz 500 kHz 250 kHz 2 MHz FOUT FOUT range FOUT step
Example frequency calculation for an 16 MHz input frequency If an output frequency of 131 MHz was desired the following steps would be taken to identify the appropriate M and N values. According to Table 9, 131 MHz falls in the frequency set by a value of 4 so N[1:0] = 01. For N = 4 the output frequency is FOUT = M / 2 and M = FOUT x 2. Therefore M = 2 x 131 = 262, so M[8:0] = 010000011. Following this procedure a user can generate any whole frequency between 50 MHz and 800 MHz. Note than for N > 2 fractional values of can be realized. The size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: fSTEP = fXTAL / 8 / N Using the parallel and serial interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[8:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[8:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 4 illustrates the timing diagram for both a parallel and a serial load of the MPC9230 synthesizer. M[8:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. (6)
Using the test and diagnosis output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVPECL compatible TEST output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the LVPECL compatible FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9230 itself. However the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9230 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clock tree. Table 10 shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 50 MHz as the divide ratio of the Post-PLL divider is 4 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle. Table 10. Test and Debug Configuration for TEST
T[2:0] T2 0 0 0 0 1 1 1 1 a. T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 14-bit shift register outa Logic 1 fXTAL / 16 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode FOUT / 4 TEST output
Clocked out at the rate of S_CLOCK
Table 11. Debug Configuration for PLL bypassa
Output FOUT TEST a. b. S_CLOCK / N M-Counter outb Configuration
T[2:0]=110. AC specifications do not apply in PLL bypass mode clocked out at the rate of S_CLOCK/(2N)
TIMING SOLUTIONS
7
MOTOROLA
MPC9230
S_CLOCK
S_DATA
T2 First Bit M, N
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0 Last Bit
S_LOAD M[8:0] N[1:0] P_LOAD
Figure 4. Serial Interface Timing Diagram RF = 10-15 Power Supply Filtering VCC_PLL VCC The MPC9230 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if C2 CF = 22 F MPC9230 this noise is seen on the power supply pins. Random noise on the VCC_PLL pin impacts the device characteristics. The VCC MPC9230 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. C1, C2 = 0.01...0.1 F C1 The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled Figure 5. VCC_PLL Power Supply Filter environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment Layout Recommendations where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The The MPC9230 provides sub-nanosecond output edge simplest form of isolation is a power supply filter on the rates and thus a good power supply bypassing scheme is a VCC_PLL pin for the MPC9230. Figure 5. illustrates a typical must. Figure 6. shows a representative board layout for the power supply filter scheme. The MPC9230 is most susceptible MPC9230. There exists many different potential board layouts to noise with spectral content in the 1 kHz to 1 MHz range. and the one pictured is but one. The important aspect of the Therefore, the filter should be designed to target this range. layout in Figure 6. is the low impedance connections between The key parameter that needs to be met in the final filter design VCC and GND for the bypass capacitors. Combining good is the DC voltage drop that will be seen between the VCC quality general purpose chip capacitors with good PCB layout supply and the MPC9230 pin of the MPC9230. From the data techniques will produce effective capacitor resonances at sheet, the VCC_PLL current (the current sourced through the frequencies adequate to supply the instantaneous switching VCC_PLL pin) is maximum 20 mA, assuming that a minimum current for the MPC9230 outputs. It is imperative that low of 2.835 V must be maintained on the VCC_PLL pin. The inductance chip capacitors are used; it is equally important resistor shown in Figure 5. must have a resistance of 10-15 that the board layout does not introduce back all of the to meet the voltage drop criteria. The RC filter pictured will inductance saved by using the leadless capacitors. Thin provide a broadband filter with approximately 100:1 interconnect traces between the capacitor and the power attenuation for noise whose spectral content is above 20 kHz. plane should be avoided and multiple large vias should be As the noise frequency crosses the series resonant point of an used to tie the capacitors to the buried power planes. Fat individual capacitor its overall impedance begins to look interconnect and large vias will help to minimize layout inductive and thus increases with increasing frequency. The induced inductance and thus maximize the series resonant parallel capacitor combination shown ensures that a low point of the bypass capacitors. Note the dotted lines circling impedance path to ground exists for frequencies well above the crystal oscillator connection to the device. The oscillator is the bandwidth of the PLL. Generally, the resistor/capacitor a series resonant circuit and the voltage amplitude across the filter will be cheaper, easier to implement and provide an crystal is relatively small. It is imperative that no actively adequate level of supply filtering. A higher level of attenuation switching signals cross under the crystal as crosstalk energy can be achieved by replacing the resistor with an appropriate coupled to these lines could significantly impact the jitter of the valued inductor. A 1000 H choke will show a significant device. Special attention should be paid to the layout of the impedance at 10 kHz frequencies and above. Because of the crystal to ensure a stable, jitter free interface between the current draw and the voltage that must be maintained on the crystal and the on-board oscillator. Although the MPC9230 VCC_PLL pin, a low DC resistance inductor is required (less has several design features to minimize the susceptibility to than 15 ). power supply noise (isolated power and grounds and fully
MOTOROLA
8
TIMING SOLUTIONS
MPC9230
differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. surface mount crystals are recommended, but not required. Because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. For crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. Although typically not required it is a good idea to layout the PCB with the provision of adding this external resistor. The resistor value will typically be between 500 and 1K. The oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. Unfortunately most crystals are characterized in a parallel resonant mode. Fortunately there is no physical difference between a series resonant and a parallel resonant crystal. The difference is purely in the way the devices are characterized. As a result a parallel resonant crystal can be used with the MPC9230 with only a minor error in the desired frequency. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. Table 12 below specifies the performance requirements of the crystals to be used with the MPC9230. Table 12. Recommended Crystal Specifications
Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Value Fundamental AT Cut Series Resonance* 75ppm at 25C 150pm 0 to 70C 0 to 70C 5-7pF 50 to 80 100W 5ppm/Yr (First 3 Years)
1 CF C2
Figure 6. PCB Board Layout Recommendation for the PLCC28 Package Using the On-Board Crystal Oscillator The MPC9230 features a fully integrated on-board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. The series resonant design provides better stability and eliminates the need for large on chip capacitors. The oscillator is totally self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC9230 as possible to avoid any board level parasitics. To facilitate co-location
TIMING SOLUTIONS
EE EE
Xtal
EEE EEE EEE EEE
= VCC = GND = Via 9
EEE EEE EEE EEE
C1
C1
EE EE
* See accompanying text for series versus parallel resonant discussion.
MOTOROLA
MPC9230
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
0.007 (0.180)
M
T L-M
S
N
S S
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M
T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
MOTOROLA
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TIMING SOLUTIONS
MPC9230
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-03 ISSUE B
4X
6 D1 D1/2
PIN 1 INDEX 32 25
0.20 H A-B D e/2 3 A, B, D
1
E1/2 A 6 E1
DETAIL G 8 17
B E E/2 4
F
F DETAIL G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP.
7
9
D D 4
D/2
4X
0.20 C A-B D
H
SEATING PLANE
28X
e
32X
0.1 C
C
DETAIL AD
PLATING BASE METAL
b1 c
8X
( q1_)
R R2 R R1
A
A2
0.25
GAUGE PLANE
A1
(S) (L1) DETAIL AD
L
q_
TIMING SOLUTIONS
EEEE EEEE
b 0.20
M
c1
DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 1 R1 R2 S
5
8
C A-B D
SECTION F-F
MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0_ 7_ 12 _REF 0.08 0.20 0.08 --- 0.20 REF
11
MOTOROLA
MPC9230
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners.
E Motorola Inc. 2003
HOW TO REACH US: USA / EUROPE / LOCATIONS NOT LISTED: TECHNICAL INFORMATION CENTER: 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 HOME PAGE: http://motorola.com/semiconductors
MOTOROLA
12
MPC9230/D TIMING SOLUTIONS

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