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ML4801
Variable Feedforward PFC/PWM Controller Combo
Features
* * * * * * * * * Internally synchronized PFC and PWM in one IC Low start-up current (200A typ.) Low operating current (5.5mA typ.) Low total harmonic distortion Reduces ripple current in the storage capacitor between the PFC and PWM sections Average current continuous boost leading edge PFC High efficiency trailing edge PWM optimized for current mode operation Current fed gain modulator for improved noise immunity Brown-out control, overvoltage protection, UVLO, and soft start
General Description
The ML4801 is a controller for power factor corrected, switched mode power supplies. Key features of this combined PFC and PWM controller are low start-up and operating currents. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specifications. The ML4801 includes circuits for the implementation of a leading edge, average current "boost" type power factor correction and a trailing edge pulse width modulator (PWM). The PFC frequency of the ML4801 is automatically set at half that of the PWM frequency generated by the internal oscillator. This technique allows the user to design with smaller output components while maintaining the optimum operating frequency for the PFC. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brown-out protection.
Block Diagram
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 RAMP 2 9 8V VDC 6 VCC SS 5 8V 25A 1.25V
+ +
1 IEAO POWER FACTOR CORRECTOR OVP +
+ - -
13 VCC VCC 7.5V REFERENCE S -1V
+ -
VEA +
VREF 14
1.6k
IEA +
2.75V
-
Q
GAIN MODULATOR 1.6k
R S
Q PFC OUT Q 12
PFC ILIMIT
R
Q
OSCILLATOR
/2 DUTY CYCLE LIMIT
PWM OUT S VFB 2.5V
+
Q
VIN OK
+
11
R DC ILIMIT
Q GND 10
1.5V
-
PULSE WIDTH MODULATOR
VCC
UVLO
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ML4801
PRODUCT SPECIFICATION
Pin Configuration
ML4801 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N)
IEAO 1 IAC 2 ISENSE 3 VRMS 4 SS 5 VDC 6 RTCT 7 RAMP 1 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 PWM OUT 10 GND 9 RAMP 2
TOP VIEW
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name IEAO IAC ISENSE VRMS SS VDC RTCT RAMP 1 RAMP 2 GND PWM OUT PFC OUT VCC VREF VFB VEAO PFC gain control reference input Current sense input to the PFC current limit comparator Input for PFC RMS line voltage compensation Connection point for the PWM soft start capacitor PWM voltage feedback input Connection for oscillator frequency setting components PFC ramp input PWM ramp current sense input Ground PWM driver output PFC driver output Positive supply (connected to an internal shunt regulator). Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output Function PFC transconductance current error amplifier output
2
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PRODUCT SPECIFICATION
ML4801
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VCC ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (JA) Plastic DIP Plastic SOIC -65 -3 GND - 0.3 Min. Max. 18 5 VCC + 0.3 20 10 500 500 1.5 150 150 260 80 105 Units V V V mA mA mA mA J C C C C/W C/W
Operating Conditions
Temperature Range ML4801CX ML4801IX Min. 0 -40 Max. 70 85 Units C C
Electrical Characteristics
Unless otherwise specified, VCC = 15V, RT = 29.4k, RRAMP1 = 15.4k, CT = 270pF, CRAMP1 = 620pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage
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Conditions
Min. 0
Typ.
Max. Units 5 V V A V 0.4 -150 150 V A A dB dB 2 V mV
3
Voltage Error Amplifier VNON INV = VINV, VEAO = 3.75V Note 2 6.0 VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 11V < VCC < 16.5V -40 40 60 60 -1.5 VNON INV = VINV, VEAO = 3.75V 60 0 100 8 40 2.43 65 2.50 -0.5 6.7 0.1 -70 70 70 70 80 2.57 -1.0
120 15
ML4801
PRODUCT SPECIFICATION
Electrical Characteristics(Continued)
Unless otherwise specified, VCC = 15V, RT = 29.4k, RRAMP1 = 15.4k, CT = 270pF, CRAMP1 = 620pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain PSRR OVP Comparator Threshold Voltage Hysteresis PFC ILIMIT Comparator Threshold Voltage PFC ILIMIT Threshold - Gain Modulator Output Delay to Output DC ILIMIT Comparator Threshold Voltage Input Bias Current Delay to Output VIN OK Comparator Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) IAC = 100A, VRMS = VFB = 0V IAC = 50A, VRMS = 1V, VFB = 0V IAC = 50A, VRMS = 1.8V, VFB = 0V IAC = 100A, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage PFC Dead Time CT Discharge Current Reference Output Voltage Line Regulation
4
Conditions
Min. 6.0
Typ. -0.5 6.7 0.65
Max. Units -1.0 1.0 -150 150 A V V A A dB dB 2.85 325 -1.1 V mV V mV 300 1.6 1 300 2.6 1.2 1.05 2.40 1.25 0.40 MHz 0.85 212 V kHz % % 218 kHz V 600 7.5 7.6 25 ns mA V mV ns V A ns V V
VIN = 0.5V, VOUT = 6V VIN = 0.5V, VOUT = 1.5V 11V < VCC < 16.5V
-40 40 55 60 2.65 175 -0.9 120
-70 70 65 75 2.75 250 -1.0 220 150
1.4
1.5 0.3 150
2.4 0.8 0.65 1.90 0.90 0.20 0.65 188
2.5 1.0 0.85 2.20 1.05 0.30 10 0.75 200 1 2
IAC = 100A IAC = 350A, VRMS = 1V, VFB = 0V TA = 25C 11V < VCC < 16.5V Over Line and Temp 182
2.5 350 VRAMP 2 = 0V, VRAMP 1 = 2.5V TA = 25C, I(VREF) = 1mA 11V < VCC < 16.5V 3.5 7.4 470 5.5 7.5 10
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PRODUCT SPECIFICATION
ML4801
Electrical Characteristics(Continued)
Unless otherwise specified, VCC = 15V, RT = 29.4k, RRAMP1 = 15.4k, CT = 270pF, CRAMP1 = 620pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Load Regulation Temperature Stability Total Variation Long Term Stability PFC Minimum Duty Cycle Maximum Duty Cycle Output Low Voltage VIEAO > 6.7V VIEAO < 1.2V IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 9V Output High Voltage Rise/Fall Time PWM DC VOL Duty Cycle Range Output Low Voltage IOUT = -20mA IOUT = -100mA IOUT = -10mA, VCC = 9V VOH Output High Voltage Rise/Fall Time Supply Start-up Current Operating Current Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis VCC = 12V, CL = 0 VCC = 14V, CL = 0 12.4 2.7 200 5.5 13.0 3.0 350 7.0 13.6 3.3 A mA V V IOUT = 20mA IOUT = 100mA CL = 1000pF VCC - 0. 8 VCC - 2.0 50 0-44 0-47 0.4 0.7 0.4 0-50 0.8 2.0 0.8 % V V V V V ns IOUT = 20mA IOUT = 100mA CL = 1000pF VCC - 0.8 VCC - 2.0 50 90 95 0.4 0.7 0.4 0.8 2.0 0.8 0 % % V V V V V ns Line, Load, Temp TJ = 125C, 1000 Hours 7.35 5 Conditions 1mA < I(VREF) < 10mA Min. Typ. 10 0.4 7.65 25 Max. Units 20 mV % V mV
Notes 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K x 5.3V; K = (IMULO - IOFFSET) x IAC x (VEAO - 0.625V)-1.
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5
ML4801
PRODUCT SPECIFICATION
Functional Description
The ML4801 consists of a combined average-currentcontrolled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. It is distinguished from earlier combo controllers by its dramatically reduced start-up and operating currents. The PWM section is intended to be used in current mode. The PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher useable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the reduced ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4801 runs at twice the frequency of the PFC, which allows the use of smaller PWM output magnetics and filter capacitors while holding down the losses in the PFC stage power components. In addition to power factor correction, a number of protection features have been built into the ML4801. These include soft-start, PFC over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and undervoltage lockout.
By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line matches the instantaneous line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VACrms. The other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. The first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which sets an average operating level for a current error amplifier and switching output driver. The second requirement is met by using the rectified AC line voltage to modulate the instantaneous input of the current control loop. Such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. In order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/Vin2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4801 PFC is of the current-averaging type, no slope compensation is required.
Power Factor Correction
Power factor correction makes a non-linear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). A common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). If the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To maintain the input current of a device drawing power from the AC line in phase with, and proportional to, the input voltage, a way must be found to cause that device to load the line in proportion to the instantaneous line voltage. The PFC section of the ML4801 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the AC input and back to zero.
PFC Section
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the ML4801. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1. A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via an (external) resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. A voltage proportional to the long-term rms AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The gain modulator's output is inversely proportional to VRMS2 (except at unusually low values of VRMS where special gain contouring takes over to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is designated as K.
REV. 1.2 3/27/01
2.
6
PRODUCT SPECIFICATION
ML4801
16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 8 RTCT 7 GAIN MODULATOR 1.6k VEA + -
1 IEAO POWER FACTOR CORRECTOR OVP +
-
13 VCC 7.5V REFERENCE VREF 14
1.6k
IEA + PFC CONTROLLER 8V
2.75V
PFC ILIMIT -1V
+ -
PFC OUTPUT DRIVER OSCILLATOR /2 DUTY CYCLE LIMIT
PFC OUT 12
Figure 1. PFC Section Block Diagram
3.
The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage.
The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual-ground (negative) input of the current error amplifier. In this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the PFC from the power line. The general form for the output of the gain modulator is: I AC x VEAO I GAINMOD = -------------------------------- x 1V 2 V RMS More exactly, the output current of the gain modulator is given by: I GAINMOD = K x ( VEAO - 0.625V ) x I AC where K is in units of V-1. Note that the output current of the gain modulator is limited to 500A.
Current Error Amplifier
and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. In higher power applications, two current transformers are sometimes used, one to monitor the ID of the boost MOSFET(s) and one to monitor the IF of the boost diode. As stated above, the inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle will decrease to achieve a less negative voltage on the ISENSE pin.
Cycle-By-Cycle Current Limiter
(1)
The ISENSE pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the PFC section. Should the input voltage at this pin ever be more negative than -1V, the output of the PFC will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
Overvoltage Protection
The current error amplifier's output controls the PFC duty cycle to keep the current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the ISENSE pin (current into ISENSE VSENSE/1.6k). The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit,
The OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. A resistor divider from the high voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.75V, the PFC output driver is shut down. The PWM section will continue to operate. The OVP comparator has 250mV of hysteresis, and the PFC will not restart until the voltage at VFB drops below 2.5V. The OVP trip level should be set at a level where the active and passive external power components and the ML4801 are within their safe operating voltages, but not so low as to interfere with the regulator operation of the boost voltage regulation loop.
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7
ML4801
PRODUCT SPECIFICATION
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative resistor; an increase in input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: as the reference voltage comes up from zero volts, it creates a differentiated voltage on IEAO which prevents the PFC from immediately demanding a full duty cycle on its boost converter. There are two major concerns when compensating the voltage loop error amplifier; stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier's open-loop crossover frequency should be 1/2 that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). Rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier will increase significantly. This increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. The current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. It should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7kHz for a 100kHz switching frequency. There is a also a degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. However, the boost inductor will usually be the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. For more information on compensating the current and voltage control loops, see Application Notes 33, 34, and 55. Application Note 16 also contains valuable information for the design of this class of PFC.
Oscillator (RTCT)
GND
VREF
PFC OUTPUT VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 VEA +
16 IEAO
1
IEA +
+ -
GAIN MODULATOR
Figure 2. Compensation Network Connections for the Voltage and Current Error Amplifiers
The deadtime of the oscillator is derived from the following equation: V REF - 1.25 t RAMP = C T x R T x In ----------------------------- V REF - 3.75 at VREF = 7.5V: t RAMP = C T x R T x 0.51 The ramp of the oscillator may be determined using: 2.5V t DEADTIME = ---------------- x C T = 455 x C T 5.5mA The deadtime is so small (tRAMP >> tDEADTIME) that the operating frequency can typically be approximated by: 1 f OSC = --------------t RAMP (5) (4) (3)
EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: 1 f OSC = 100kHz = --------------t RAMP t RAMP = 0.51 x R T x C T = 1 x 10
-5
The oscillator frequency is set by the values of RT and CT, which determine the ramp and off-time of the ML4801's master oscillator: 1 f OSC = --------------------------------------------------t RAMP x t DEADTIME (2)
Solving for RT x CT yields 2 x 10-4. Selecting standard components values, CT = 270pF, and RT = 36.5k.
8
REV. 1.2 3/27/01
PRODUCT SPECIFICATION
ML4801
PWM Section
The PWM section of the ML4801 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, and that the PWM stage is optimized for current-mode operation. In the ML4801, the operating frequency of the PFC section is fixed at 1/2 of the PWM's operating frequency. This is done through the use of a 2:1 digital frequency divider ("T" flip-flop) linking the two functional sections of the IC. No voltage error amplifier is included in the PWM stage of the ML4801, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM's RAMP 2 input which allows VDC to command a zero percent duty cycle for input voltages below 1.25V.
PWM Current Limit
Solving for the minimum value of CSS: 25A C SS = 5ms x -------------- = 100nF 1.25V (6)
Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0F soft start capacitor will allow time for VFB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms.
Generating VCC
The RAMP 2 pin provides a direct input to the cycle-bycycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1.5V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.5V. Once this voltage reaches 2.5V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start commences.
PWM Control (RAMP 2)
The ML4801 is a voltage-fed part. It requires an external 15V10% or better Zener shunt voltage regulator, or some other VCC regulator, to maintain the voltage supplied to the part at 15V nominal. This allows a low power dissipation while at the same time delivering 13V nominal of gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor's value must be chosen to meet the operating current requirement of the ML4801 itself (8.5mA max.) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC limit of 16.5V (max) and driving a total gate charge of 110nC at 100kHz (1 IRF840 MOSFET and 2 IRF830 MOSFETs), the gate driver current required is: I GATEDRIVE = 100kHz x 110nC = 11mA 20V - 16.5V R BIAS = -------------------------------------- = 180 7.5mA + 11mA The ML4801 should be locally bypassed with a 10nF and a 1F ceramic capacitor. In most applications, an electrolytic capacitor of between 33F and 100F is also required across the part, both for filtering and as part of the start-up bootstrap circuitry.
In addition to its PWM current limit function, RAMP 2 is used as the sampling point for a voltage representing the current in the primary of the PWM's output transformer. This voltage may be derived either by a current sensing resistor or a current transformer.
Soft Start
Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25A supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: 25A C SS = t DELAY x -------------1.25V (6)
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge
where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms.
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9
ML4801
PRODUCT SPECIFICATION
modulation is determined during the ON time of the switch. Figure 3 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 4 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary "no-load" period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC's output ripple voltage can be reduced by as much as 30% using this method.
Typical Applications
Figure 9 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33.
L1 + DC I1 VIN
SW2
I2
I3 I4 RL
+ DC
L1 I1 VIN
SW2
I2
I3 I4
SW1 C1 RAMP
SW1 C1
RL RAMP
VEAO REF U3 + EA - DFF RAMP OSC U4 CLK + - VSW1 U1 R Q D U2 Q CLK
RAMP OSC U4 CLK U3 + EA -
VEAO
TIME
REF
VEAO + - CMP U1 DFF VSW1 R Q D U2 Q CLK
TIME
TIME
TIME
Figure 3. Typical Trailing Edge Control Scheme
Figure 4. Leading/Trailing Edge Control Scheme
10
REV. 1.2 3/27/01
PRODUCT SPECIFICATION
ML4801
160
180
IVEAO (A)
0
90
-160 0 1 2 VFB (V) 3 4 5
0 0 1 2 VFB (V) 3 4 5
Figure 5. IVEAO vs. VFB
Figure 6. gM of VOTA
200
500
160
120 K 80 40 0 0 1 2 VFB (V) 3 4 5 0 0 1 2 3 4 5 VRMS (V)
Figure 7. gM of IOTA
Figure 8. K of Multiplier
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11
ML4801
PRODUCT SPECIFICATION
AC INPUT 85 TO 265VAC
C1 680nF
F1 3.15A L1 3mH Q1 IRF840 R2A 357k C4 C5 10nF 100F R1A 249k R27 82k R2B 357k 15V R21 22 C25 100nF T1 R30 4.7k R15 3 D6 BYV26C D7 16V T2 D1 8A, 600V "FRED " Diode Q2 R17 IRF830 33 D5 BYV26C L2 D11 MBR2545CT 15H C24 1F 12VDC
BR1 4A, 600V
C21 1800F
R28 180
D3 BYV26C
C20 1F
RTN R24 1.2k
C3 100nF
R1B 249k R3 75k
C30 47F
C12 20F
1N4745 16V R7A 178k
R14 33
Q3 IRF830 R23 1.5k R20 1.5
10k
C22 4.7F R18 220 R22 8.66k
D12 1N5401 D13 1N5401
C7 220pF R12 27k C6 1F R7B 178k
R19 220
C23 R26 100nF 10k
R25 2.26k
C2 470nF
R4 13k
TL431
IEAO IAC ISENSE
R5 300m 1W
VDC VFB VREF VCC PFC OUT PWM OUT GND RAMP 2
D8 1N5818 D10 1N5818 C15 10nF C16 1F C13 100nF C14 1F R8 2.37k C31 1nF R11 768k C8 100nF
C9 10nF
VRMS SS VDC
C19 1.0F 60k
RTCT RAMP 1
ML4801 1nF C18 270pF R6 36.5k 20k R10 6.2k
C17 220pF
L1: Premier Magnetics #TSD-734 L2: 15H, 10A DC T1: Premier Magnetics #PMGD- 03 T2: Premier Magnetics #TSD-1048 Premier Magnetics: (714) 362-4211
C11 10nF 470pF
Figure 9. 100W Power Factor Corrected Power Supply
12
REV. 1.2 3/27/01
PRODUCT SPECIFICATION
ML4801
Mechanical Dimensions Inches (Millimeters)
Package: P16 16-Pin PD IP
0.740 - 0.760 (18.79 - 19.31) 16
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.02 MIN (0.50 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: S16N 16-Pin Narrow SOIC
0.386 - 0.396 (9.80 - 10.06) 16
PIN 1 ID
0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20)
1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE 0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
REV. 1.2 3/27/01
13
ML4801
PRODUCT SPECIFICATION
Ordering Information
Part Number ML4801CP ML4801CS ML4801IP ML4801IS Temperature Range 0C to 70C 0C to 70C -40C to 85C -40C to 85C Package 16-Pin Plastic DIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin Plastic DIP (P16) 16-Pin Narrow SOIC (S16N)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/27/01 0.0m 001 Stock#DS30004800 2001 Fairchild Semiconductor Corporation

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