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 H8/510 Hardware Manual
Preface
The H8/510 is a high-performance microcomputer, featuring a high-speed CPU with 16-bit internal data paths and a full complement of on-chip supporting modules. The H8/510 is an ideal microcontroller for a wide variety of medium-scale devices, including both office and industrial equipment and consumer products. The CPU has a highly orthogonal, optimized instruction set designed for fast execution of programs coded in the high-level C language. On-chip facilities include a DRAM refresh controller, numerous timers, serial I/O, an A/D converter, I/O ports, and other functions for compact implementation of high-performance application systems. This manual gives a hardware description of the H8/510. For details of the instruction set, refer to the H8/500 Series Programming Manual, which applies to all chips in the H8/500 Series.
Contents
Section 1 Overview*******************************************************************************************************************1
1.1 1.2 1.3 Features **********************************************************************************************************************************1 Block Diagram ***********************************************************************************************************************4 Pin Arrangements and Functions *******************************************************************************************5 1.3.1 Pin Arrangement *********************************************************************************************************5 1.3.2 Pin Functions **************************************************************************************************************6
Section 2 MCU Operating Modes and Address Space ************************************************15
2.1 Overview ******************************************************************************************************************************15 2.1.1 Selection of MCU Mode *******************************************************************************************15 2.1.2 Register Control of MCU Mode *******************************************************************************15 Mode Control Register (MDCR) *****************************************************************************************16 Mode Descriptions ***************************************************************************************************************16 Pin Functions in Each MCU Mode **************************************************************************************17 Memory Map in Each MCU Mode **************************************************************************************19
2.2 2.3 2.4 2.5
Section 3 CPU **************************************************************************************************************************21
3.1 Overview ******************************************************************************************************************************21 3.1.1 Features *********************************************************************************************************************21 3.1.2 Address Space ***********************************************************************************************************22 3.1.3 Register Configuration **********************************************************************************************23 CPU Register Descriptions **************************************************************************************************24 3.2.1 General Registers ******************************************************************************************************24 3.2.2 Control Registers ******************************************************************************************************25 3.2.3 Initial Register Values ***********************************************************************************************30 Data Formats ************************************************************************************************************************31 3.3.1 Data Formats in General Registers ***************************************************************************31 3.3.2 Data Formats in Memory ******************************************************************************************32 Instructions ***************************************************************************************************************************34 3.4.1 Basic Instruction Formats *****************************************************************************************34 3.4.2 Addressing Modes ****************************************************************************************************35 3.4.3 Effective Address Calculation **********************************************************************************37 Instruction Set **********************************************************************************************************************40 3.5.1 Overview *******************************************************************************************************************40 3.5.2 Data Transfer Instructions *****************************************************************************************42 3.5.3 Arithmetic Instructions *********************************************************************************************43 3.5.4 Logic Operations *******************************************************************************************************44 3.5.5 Shift Operations ********************************************************************************************************45 3.5.6 Bit Manipulations ******************************************************************************************************46
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.5.7 Branching Instructions **********************************************************************************************47 3.5.8 System Control Instructions **************************************************************************************49 3.5.9 Short-Format Instructions *****************************************************************************************52 Operating Modes ******************************************************************************************************************52 3.6.1 Minimum Mode ********************************************************************************************************52 3.6.2 Maximum Mode ********************************************************************************************************53 Basic Operational Timing ****************************************************************************************************53 3.7.1 Overview *******************************************************************************************************************53 3.7.2 Two-State Access Cycle *******************************************************************************************54 3.7.3 Three-State Access Cycle *****************************************************************************************55 3.7.4 On-Chip Register Field Access Cycle **********************************************************************56 3.7.5 Pin States during Register Field Access *******************************************************************57 CPU States ***************************************************************************************************************************57 3.8.1 Overview *******************************************************************************************************************57 3.8.2 Program Execution State *******************************************************************************************59 3.8.3 Exception-Handling State *****************************************************************************************59 3.8.4 Bus-Released State ****************************************************************************************************60 3.8.5 Reset State *****************************************************************************************************************64 3.8.6 Power-Down State *****************************************************************************************************64
Section 4 Exception Handling*********************************************************************************************65
4.1 Overview ******************************************************************************************************************************65 4.1.1 Types of Exception Handling and Their Priority ******************************************************65 4.1.2 Hardware Exception-Handling Sequence *****************************************************************66 4.1.3 Exception Factors and Vector Table *************************************************************************66 Reset ************************************************************************************************************************************69 4.2.1 Overview *******************************************************************************************************************69 4.2.2 Reset Sequence *********************************************************************************************************69 4.2.3 Stack Pointer Initialization ****************************************************************************************70 Address Error ***********************************************************************************************************************73 4.3.1 Illegal Instruction Prefetch ****************************************************************************************73 4.3.2 Word Data Access at Odd Address ***************************************************************************73 Trace ************************************************************************************************************************************74 Interrupts ******************************************************************************************************************************74 Invalid Instruction ****************************************************************************************************************76 Trap Instructions and Zero Divide ***************************************************************************************76 Cases in Which Exception Handling is Deferred *****************************************************************76 4.8.1 Instructions that Disable Interrupts ***************************************************************************76 4.8.2 Disabling of Exceptions Immediately after a Reset **************************************************77 4.8.3 Disabling of Interrupts after a Data Transfer Cycle **************************************************78
4.2
4.3
4.4 4.5 4.6 4.7 4.8
Stack Status after Completion of Exception Handling ********************************************************78 4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions ***************************************80 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions **********************************************************************************************80 4.10 Notes on Use of the Stack ****************************************************************************************************80
4.9
Section 5 Interrupt Controller**********************************************************************************************81
5.1 Overview ******************************************************************************************************************************81 5.1.1 Features *********************************************************************************************************************81 5.1.2 Block Diagram **********************************************************************************************************82 5.1.3 Register Configuration **********************************************************************************************83 Interrupt Types *********************************************************************************************************************83 5.2.1 External Interrupts ****************************************************************************************************83 5.2.2 Internal Interrupts ******************************************************************************************************87 5.2.3 Interrupt Vector Table ***********************************************************************************************87 Register Descriptions ***********************************************************************************************************89 5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) *************************************************89 5.3.2 Timing of Priority Setting *****************************************************************************************90 Interrupt Handling Sequence ***********************************************************************************************90 5.4.1 Interrupt Handling Flow *******************************************************************************************90 5.4.2 Stack Status after Interrupt Handling Sequence *******************************************************93 5.4.3 Timing of Interrupt Exception-Handling Sequence **************************************************94 Interrupts During Operation of the Data Transfer Controller **********************************************94 Interrupt Response Time ******************************************************************************************************97
5.2
5.3
5.4
5.5 5.6
Section 6 Data Transfer Controller ************************************************************************************99
6.1 Overview ******************************************************************************************************************************99 6.1.1 Features *********************************************************************************************************************99 6.1.2 Block Diagram **********************************************************************************************************99 6.1.3 Register Configuration ********************************************************************************************100 Register Descriptions *********************************************************************************************************101 6.2.1 Data Transfer Mode Register (DTMR) *******************************************************************101 6.2.2 Data Transfer Source Address Register (DTSR) ****************************************************102 6.2.3 Data Transfer Destination Register (DTDR) *********************************************************102 6.2.4 Data Transfer Count Register (DTCR) *******************************************************************102 6.2.5 Data Trnasfer Enable Registers A to D (DTEA to DTED) *************************************103 Data Transfer Operation *****************************************************************************************************104 6.3.1 Data Transfer Cycle ************************************************************************************************104 6.3.2 DTC Vector Table ***************************************************************************************************106 6.3.3 Location of Register Information in Memory *********************************************************108
6.2
6.3
6.4 6.5
6.3.4 Length of Data Transfer Cycle ********************************************************************************108 Procedure for Using the DTC *********************************************************************************************110 Example ******************************************************************************************************************************111
Section 7 Wait-State Controller*****************************************************************************************113
7.1 Overview ****************************************************************************************************************************113 7.1.1 Features *******************************************************************************************************************113 7.1.2 Block Diagram ********************************************************************************************************114 7.1.3 Register Configuration ********************************************************************************************114 Wait-State Control Register ************************************************************************************************115 Operation in Each Wait Mode ********************************************************************************************116 7.3.1 Programmable Wait Mode **************************************************************************************116 7.3.2 Pin Wait Mode *********************************************************************************************************117 7.3.3 Pin Auto-Wait Mode ***********************************************************************************************119
7.2 7.3
Section 8 Clock Pulse Generator **************************************************************************************121
8.1 8.2 8.3 Overview ****************************************************************************************************************************121 8.1.1 Block Diagram ********************************************************************************************************121 Oscillator Circuit ****************************************************************************************************************121 System Clock Divider ********************************************************************************************************124
Section 9 I/O Ports ****************************************************************************************************************125
9.1 9.2 Overview ****************************************************************************************************************************125 Port 1 **********************************************************************************************************************************127 9.2.1 Overview *****************************************************************************************************************127 9.2.2 Port 1 Registers *******************************************************************************************************127 9.2.3 Pin Functions in Each Mode ***********************************************************************************128 Port 2 **********************************************************************************************************************************130 9.3.1 Overview *****************************************************************************************************************130 9.3.2 Port 2 Registers *******************************************************************************************************130 9.3.3 Pin Functions in Each Mode ***********************************************************************************131 Port 3 **********************************************************************************************************************************132 9.4.1 Overview *****************************************************************************************************************132 9.4.2 Port 3 Registers *******************************************************************************************************133 9.4.3 Pin Functions **********************************************************************************************************135 Port 4 **********************************************************************************************************************************135 9.5.1 Overview *****************************************************************************************************************135 9.5.2 Port 4 Registers *******************************************************************************************************136 9.5.3 Pin Functions **********************************************************************************************************137 Port 5 **********************************************************************************************************************************139 9.6.1 Overview *****************************************************************************************************************139
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.6.2 9.6.3 Port 6 9.7.1 9.7.2 Port 7 9.8.1 9.8.2 Port 8 9.9.1 9.9.2 9.9.3
Port 5 Registers *******************************************************************************************************140 Pin Functions **********************************************************************************************************141 **********************************************************************************************************************************142 Overview *****************************************************************************************************************142 Port 6 Registers *******************************************************************************************************143 **********************************************************************************************************************************144 Overview *****************************************************************************************************************144 Port 7 Registers *******************************************************************************************************144 **********************************************************************************************************************************145 Overview *****************************************************************************************************************145 Port 8 Registers *******************************************************************************************************145 Pin Functions **********************************************************************************************************147
Section 10 16-Bit Free-Running Timers *************************************************************************151
10.1 Overview ****************************************************************************************************************************151 10.1.1 Features *******************************************************************************************************************151 10.1.2 Block Diagram ********************************************************************************************************152 10.1.3 Input and Output Pins *********************************************************************************************153 10.1.4 Register Configuration ********************************************************************************************154 10.2 Register Descriptions *********************************************************************************************************155 10.2.1 Free-Running Counter (FRC)--H'FEA2, H'FEB2 *************************************************155 10.2.2 Output Compare Registers A and B (OCRA and OCRB)--H'FEA4 and H'FEA6, H'FEB4 and H'FEB6 *************************************************************************156 10.2.3 Input Capture Register (ICR)--H'FEA8, H'FEB8 **************************************************156 10.2.4 Timer Control Register (TCR)--H'FEA0, H'FEB0 ************************************************157 10.2.5 Timer Control/Status Register (TCSR)--H'FEA1, H'FEB1 ***********************************159 10.3 CPU Interface *********************************************************************************************************************162 10.4 Operation ****************************************************************************************************************************164 10.4.1 FRC Incrementation Timing ***********************************************************************************164 10.4.2 Output Compare Timing *****************************************************************************************165 10.4.3 Input Capture Timing **********************************************************************************************167 10.4.4 Setting of FRC Overflow Flag (OVF) ********************************************************************169 10.5 CPU Interrupts and DTC Interrupts ***********************************************************************************169 10.6 Synchronization of Free-Running Timers 1 and 2 *************************************************************170 10.6.1 Synchronization after a Reset *********************************************************************************170 10.6.2 Synchronization by Writing to FRCs **********************************************************************170 10.7 Sample Application ************************************************************************************************************174 10.8 Application Notes **************************************************************************************************************174
Section 11 8-Bit Timer *********************************************************************************************************181 11.1 Overview ****************************************************************************************************************************181
11.2
11.3
11.4 11.5 11.6
11.1.1 Features *******************************************************************************************************************181 11.1.2 Block Diagram ********************************************************************************************************182 11.1.3 Input and Output Pins *********************************************************************************************183 11.1.4 Register Configuration ********************************************************************************************183 Register Descriptions *********************************************************************************************************183 11.2.1 Timer Counter (TCNT)--H'FEC4 **************************************************************************183 11.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FEC2 and H'FEC3 ******************************************************184 11.2.3 Timer Control Register (TCR)--H'FEC0 ***************************************************************184 11.2.4 Timer Control/Status Register (TCSR)--H'FEC1 **************************************************186 Operation ****************************************************************************************************************************188 11.3.1 TCNT Incrementation Timing ********************************************************************************188 11.3.2 Compare Match Timing ******************************************************************************************189 11.3.3 External Reset of TCNT *****************************************************************************************190 11.3.4 Setting of TCNT Overflow Flag *****************************************************************************191 CPU Interrupts and DTC Interrupts ***********************************************************************************192 Sample Application ************************************************************************************************************193 Application Notes **************************************************************************************************************194
Section 12 Refresh Controller ********************************************************************************************201
12.1 Overview ****************************************************************************************************************************201 12.1.1 Features *******************************************************************************************************************201 12.1.2 Block Diagram ********************************************************************************************************201 12.1.3 Register Configuration ********************************************************************************************202 12.2 Refresh Control Register (RFSHCR)--H'FED8 ****************************************************************203 12.3 Operation ****************************************************************************************************************************205 12.3.1 Wait State Insertion *************************************************************************************************206 12.3.2 TP Insertion *************************************************************************************************************207 12.4 Operation in Power-Down State ****************************************************************************************209 12.5 Operation in Reset State *****************************************************************************************************209 12.6 Application Notes **************************************************************************************************************209
Section 13 Serial Communication Interface ******************************************************************211
13.1 Overview ****************************************************************************************************************************211 13.1.1 Features *******************************************************************************************************************211 13.1.2 Block Diagram ********************************************************************************************************212 13.1.3 Input and Output Pins *********************************************************************************************213 13.1.4 Register Configuration ********************************************************************************************213 13.2 Register Descriptions *********************************************************************************************************214 13.2.1 Receive Shift Register (RSR) *********************************************************************************214 13.2.2 Receive Data Register (RDR)--H'FECD and H'FED5 ******************************************214
13.2.3 Transmit Shift Register (TSR) ********************************************************************************214 13.2.4 Transmit Data Register (TDR)--H'FECB and H'FED3 *****************************************215 13.2.5 Serial Mode Register (SMR)--H'FEC8 and H'FED0 *********************************************215 13.2.6 Serial Control Register (SCR)--H'FECA and H'FED2 ******************************************217 13.2.7 Serial Status Register (SSR)--H'FECC and H'FED4 *********************************************219 13.2.8 Bit Rate Register (BRR)--H'FEC9 and H'FED1 ***************************************************221 13.3 Operation ****************************************************************************************************************************226 13.3.1 Overview *****************************************************************************************************************226 13.3.2 Asynchronous Mode ***********************************************************************************************227 13.3.3 Synchronous Mode *************************************************************************************************231 13.4 CPU Interrupts and DTC Interrupts ***********************************************************************************234 13.5 Application Notes **************************************************************************************************************235
Section 14 A/D Converter ***************************************************************************************************239 14.1 Overview ****************************************************************************************************************************239 14.1.1 Features *******************************************************************************************************************239 14.1.2 Block Diagram ********************************************************************************************************240 14.1.3 Input Pins ****************************************************************************************************************241 14.1.4 Register Configuration ********************************************************************************************241 14.2 Register Descriptions *********************************************************************************************************242 14.2.1 A/D Data Register (ADDR)--H'FE90 to H'FE97 **************************************************242 14.2.2 A/D Control/Status Register (ADCSR)--H'FE98 **************************************************243 14.2.3 A/D Control Register (ADCR)--H'FE99 ***************************************************************245 14.2.4 External Triggering of A/D Conversion *****************************************************************245 14.3 CPU Interface *********************************************************************************************************************246 14.4 Operation ****************************************************************************************************************************247 14.4.1 Single Mode ************************************************************************************************************248 14.4.2 Scan Mode **************************************************************************************************************251 14.5 Input Sampling Time and A/D Conversion Time **************************************************************253 14.6 Interrupts and the Data Transfer Controller ***********************************************************************255 Section 15 Bus Controller****************************************************************************************************257
15.1 Overview ****************************************************************************************************************************257 15.1.1 Features *******************************************************************************************************************257 15.1.2 Block Diagram ********************************************************************************************************258 15.1.3 Register Configuration ********************************************************************************************259 15.2 Register Descriptions *********************************************************************************************************259 15.2.1 Byte Area Top Register (ARBT)--H'FF16 ************************************************************259 15.2.2 Three-State Area Top Register (AR3T)--H'FF17 **************************************************260 15.3 Operation ****************************************************************************************************************************261 15.4 Notes and Precautions *********************************************************************************************************266
Section 16 Watchdog Timer************************************************************************************************271
16.1 Overview ****************************************************************************************************************************271 16.1.1 Features *******************************************************************************************************************271 16.1.2 Block Diagram ********************************************************************************************************272 16.1.3 Register Configuration ********************************************************************************************272 16.2 Register Descriptions *********************************************************************************************************273 16.2.1 Timer Counter TCNT--H'FF10 (Write), H'FF11 (Read) ***************************************273 16.2.2 Timer Control/Status Register (TCSR)--H'FF10 ***************************************************273 16.2.3 Reset Control/Status Register (RSTCSR)--H'FF1F (Read), H'FF1E (Write) *******275 16.2.4 Notes on Register Access ****************************************************************************************276 16.3 Operation ****************************************************************************************************************************278 16.3.1 Watchdog Timer Mode *******************************************************************************************278 16.3.2 Interval Timer Mode ***********************************************************************************************279 16.3.3 Operation in Software Standby Mode *********************************************************************280 16.3.4 Setting of Overflow Flag ****************************************************************************************280 16.3.5 Setting of Watchdog Timer Reset (WRST) Bit *******************************************************281 16.4 Application Notes ***************************************************************************************************************282
Section 17 Power-Down State********************************************************************************************285
17.1 Overview ****************************************************************************************************************************285 17.2 Sleep Mode ************************************************************************************************************************286 17.2.1 Transition to Sleep Mode ****************************************************************************************286 17.2.2 Exit from Sleep Mode *********************************************************************************************286 17.3 Software Standby Mode *****************************************************************************************************286 17.3.1 Transition to Software Standby Mode ********************************************************************286 17.3.2 Software Standby Control Register (SBYCR) ********************************************************287 17.3.3 Exit from Software Standby Mode *************************************************************************288 17.3.4 Sample Application of Software Standby Mode ****************************************************288 17.3.5 Application Notes ***************************************************************************************************289 17.4 Hardware Standby Mode ***************************************************************************************************289 17.4.1 Transition to Hardware Standby Mode *******************************************************************289 17.4.2 Recovery from Hardware Standby Mode ***************************************************************290 17.4.3 Timing Sequence of Hardware Standby Mode *******************************************************290
Section 18 E Clock Interface **********************************************************************************************291
18.1 Overview ****************************************************************************************************************************291
Section 19 Electrical Specifications *********************************************************************************295
19.1 Absolute Maximum Ratings **********************************************************************************************295 19.2 Electrical Characteristics ****************************************************************************************************295 19.2.1 DC Characteristics **************************************************************************************************295
19.2.2 AC Characteristics **************************************************************************************************299 19.2.3 A/D Converter Characteristics ********************************************************************************306 19.3 MCU Operatinal Timing ****************************************************************************************************307 19.3.1 Bus Timing **************************************************************************************************************307 19.3.2 Control Signal Timing *********************************************************************************************311 19.3.3 Clock Timing **********************************************************************************************************312 19.3.4 I/O Port Timing *******************************************************************************************************314 19.3.5 16-Bit Free-Running Timer Timing ************************************************************************314 19.3.6 8-Bit Timer Timing *************************************************************************************************315 19.3.7 Serial Communication Interface Timing *****************************************************************316 19.3.8 Refresh Timing *******************************************************************************************************317
Appendix A Instructions ******************************************************************************************************319
A.1 A.2 A.3 A.4 Instruction Set ********************************************************************************************************************319 Instruction Codes ***************************************************************************************************************324 Operation Code Map **********************************************************************************************************335 Instruction Execution Cycles *********************************************************************************************340
Appendix B Register Field**************************************************************************************************351
B.1 B.2 Register Addresses and Bit Names ************************************************************************************351 Register Descriptions *********************************************************************************************************355
Appendix C I/O Port Schematic Diagrams ********************************************************************390
C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 Schematic Diagram of Port 1 Schematic Diagram of Port 2 Schematic Diagram of Port 3 Schematic Diagram of Port 4 Schematic Diagram of Port 5 Schematic Diagram of Port 6 Schematic Diagram of Port 7 Schematic Diagram of Port 8 *********************************************************************************************390 *********************************************************************************************391 *********************************************************************************************392 *********************************************************************************************396 *********************************************************************************************402 *********************************************************************************************404 *********************************************************************************************405 *********************************************************************************************406
Appendix D Memory Map *************************************************************************************************410 Appendix E Pin States **********************************************************************************************************411
E.1 E.2 States of I/O Ports **************************************************************************************************************411 Pin Status in the Reset State ***********************************************************************************************412
Appendix F Package Dimensions ************************************************************************************418
Section 1 Overview
1.1 Features
The H8/510 is an original Hitachi CMOS microcomputer unit (MCU) comprising a highperformance CPU core with an internal 16-bit architecture plus a full range of supporting functions. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. An internal 16-bit architecture and the capability for 16-bit, two-state access to external memory enhance the CPU's data-processing capability and provide the speed needed for realtime control applications. The on-chip supporting functions include timers, a serial communication interface (SCI), refresh controller, bus controller, A/D converter, and I/O ports. An on-chip data transfer controller (DTC) provides an efficient way to transfer data in either direction between memory and I/O. Table 1-1 lists the main features of the H8/510 chip.
1
Table 1-1 Features
Feature CPU Description General-register machine * Eight 16-bit general registers * Five 8-bit and two 16-bit control registers High speed * Maximum clock rate: 10 MHz (oscillator frequency: 20 MHz) Two operating modes * Minimum mode: up to 64-kbyte address space * Maximum mode: up to 16-Mbyte address space Highly orthogonal instruction set * Addressing modes and data size can be specified independently for each instruction Register and memory addressing modes * Register-register operations * Register-memory operations Instruction set optimized for C language * Special short formats for frequently-used instructions and addressing modes Each channel provides: * 1 free-running counter (which can count external events) * 2 output-compare registers * 1 input capture register * One 8-bit up-counter (which can count external events) * 2 time constant registers Each channel has the following features: * Asynchronous or synchronous mode (selectable) * Full duplex: can send and receive simultaneously * Built-in baud rate generator * Selectable refresh interval and refresh cycle length * Can output 12-bit refresh addresses * A TP state can be inserted before the T1 state to satisfy RAS precharge time requirements of DRAM chips * 10-Bit resolution * 4 channels, controllable in single mode or scan mode (selectable) * Sample-and-hold function * Conversion can be externally triggered
16-Bit freerunning timer (FRT) (2 channels) 8-Bit timer (1 channel) Serial communication interface (SCI) (2 channels) Refresh controller
A/D converter
2
Table 1-1 Features (cont)
Description * 56 input/output pins (seven 8-bit ports) * 4 input-only pins (one 4-bit port) Interrupt * 5 external interrupt pins: NMI, IRQ0 (level), IRQ1 to IRQ3 (edge) controller * 18 on-chip interrupt sources (INTC) * 8 priority levels Data transfer * Performs efficient, rapid, bidirectional data transfer between memory and I/O controller (DTC) with minimal CPU programming Wait-state * Can insert wait states in access to external memory or I/O controller (WSC) Operating 4 MCU operating modes modes * Expanded minimum modes, supporting a 64-kbyte address space (modes 1 and 2) * Expanded maximum modes, supporting a 16-Mbyte address space (modes 3 and 4) 3 power-down modes * Sleep mode * Software standby mode * Hardware standby mode Watchdog * Can output a reset signal when the timer overflows timer (1 channel) * Can also be used as an interval timer Bus controller * Can select types of bus cycles Other features * E clock output * Clock generator on-chip Product code Product code Package and package HD6415108F 112-Pin QFP (FP-112) Feature I/O ports
3
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/510 chip.
P17 /D7 P16 /D6 P15 /D5 P14 /D4 P13 /D3 P12 /D2 P11 /D1 P10 /D0 D15 D14 D13 D12 D11 D10 D9 D8
P2 7 /A 23
Data bus Port 1
P2 6 /A 22 P2 5 /A 21
Port 2 Data bus (low)
P2 4 /A 20 P2 3 /A19 P2 2 /A18 P2 1 /A17 P2 0 /A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P37 P36 P35
EXTAL XTAL o E MD2 MD1 MD0 RES STBY NMI AS RD HWR LWR RFSH
Refresh controller 16-Bit free-running timer (2 channels) Interrupt controller H8/500 CPU DTC Clock pulse generator Watchdog timer
Data bus (high)
Address bus
Address bus Port 3 Port 4 Port 5
P34 P33 P3 2 /BREQ P3 1 /BACK P3 0 /WAIT
VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS
Port 8
Wait-state controller
8-Bit timer
10-Bit A/D converter
Serial communication interface (2 channels)
P4 7 /FTCI2 P4 6 /FTI 2 P4 5 /FTCI1 P4 4 /FTI1 P4 3 /TMO P4 2 /TMRI P4 1 /TMCI P4 0 /ADTRG
Port 7
Port 6
TXD 2 /P87 RXD 2 /P86 TXD 1 /P85 RXD 1 /P84 SCK 2 /IRQ 3 /P83 SCK 1 /IRQ 2 /P82 IRQ 1 /P81 IRQ 0 /P80
AN 3 /P73 AN 2 /P72 AN 1 /P71 AN 0 /P70
P67 P66 P65 P64 P63 P62 P61 P60
Figure 1-1 Block Diagram
4
P57 P56 P55 P54 FTOB 2 /P53 FTOA 2 /P52 FTOB 1 /P51 FTOA 1 /P50
1.3 Pin Arrangements and Functions
1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the H8/510.
STBY MD 2 MD 1 MD 0 VCC RFSH LWR HWR RD AS E o VSS XTAL EXTAL VSS P8 7 /TXD 2 P8 6 /RXD2 P8 5 /TXD1 P8 4 /RXD1 P8 3 /SCK 2 /IRQ 3 P8 2 /SCK1 /IRQ 2 P8 1 /IRQ 1 P8 0 /IRQ 0 VCC AVCC P73 /AN 3 P72 /AN 2
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86
RES NMI VSS D 0 /P10 D 1 /P11 D 2 /P12 D 3 /P13 D 4 /P14 D 5 /P15 D 6 /P16 D 7 /P17 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7
85
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
84 83 82 81 80 79 78 77 76 75 74 73 72
QFP-112
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
P71 /AN 1 P70 /AN0 AVSS VSS P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 P5 7 P5 6 P5 5 P5 4 P5 3 /FTOB2 P5 2 /FTOA 2 P5 1 /FTOB1 P5 0 /FTOA1 VSS P4 7 /FTCI 2 P4 6 /FTI 2 P4 5 /FTCI1 P4 4 /FTI1 P4 3 /TMO P4 2 /TMRI P4 1 /TMCI
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
A8 A9 A10 A11 A12 A13 A14 A15 V SS A 16 /P2 0 A 17 /P2 1 A 18 /P2 2 A 19 /P2 3 A 20 /P2 4 A 21 /P2 5 A 22 /P2 6 A 23 /P2 7 V SS WAIT/P3 0 BACK/P3 1 BREQ/P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 VCC ADTRG/P4 0
Figure 1-2 Pin Arrangement (Top View)
5
56
1.3.2 Pin Functions Pin Arrangements in Each Operating Mode: Table 1-2 lists the pin arrangements in each operating mode. Table 1-2 Pin Arrangements in Each Operating Mode
Pin Name Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Expanded Minimum Modes Mode 1 RES NMI VSS P10 P11 P12 P13 P14 P15 P16 P17 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 Mode 2 RES NMI VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 RES NMI VSS P10 P11 P12 P13 P14 P15 P16 P17 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 Expanded Maximum Modes Mode 3 Mode 4 RES NMI VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5
6
Table 1-2 Pin Arrangements in Each Operating Mode (cont)
Pin Name Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Expanded Minimum Modes Mode 1 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS P20 P21 P22 P23 P24 P25 P26 P27 VSS P30/WAIT P31/BACK P32/BREQ P33 P34 P35 P36 P37 VCC Mode 2 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS P20 P21 P22 P23 P24 P25 P26 P27 VSS P30/WAIT P31/BACK P32/BREQ P33 P34 P35 P36 P37 VCC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS P30/WAIT P31/BACK P32/BREQ P33 P34 P35 P36 P37 VCC Expanded Maximum Modes Mode 3 Mode 4 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS P30/WAIT P31/BACK P32/BREQ P33 P34 P35 P36 P37 VCC
7
Table 1-2 Pin Arrangements in Each Operating Mode (cont)
Pin Name Pin No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Expanded Minimum Modes Mode 1 P40/ADTRG P41/TMCI P42/TMRI P43/TMO P44/FTI1 P45/FTCI1 P46/FTI2 P47/FTCI2 VSS P50/FTOA1 P51/FTOB1 P52/FTOA2 P53/FTOB2 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC Mode 2 P40/ADTRG P41/TMCI P42/TMRI P43/TMO P44/FTI1 P45/FTCI1 P46/FTI2 P47/FTCI2 VSS P50/FTOA1 P51/FTOB1 P52/FTOA2 P53/FTOB2 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC 8 Expanded Maximum Modes Mode 3 P40/ADTRG P41/TMCI P42/TMRI P43/TMO P44/FTI1 P45/FTCI1 P46/FTI2 P47/FTCI2 VSS P50/FTOA1 P51/FTOB1 P52/FTOA2 P53/FTOB2 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC Mode 4 P40/ADTRG P41/TMCI P42/TMRI P43/TMO P44/FTI1 P45/FTCI1 P46/FTI2 P47/FTCI2 VSS P50/FTOA1 P51/FTOB1 P52/FTOA2 P53/FTOB2 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66 P67 VSS AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 AVCC
Table 1-2 Pin Arrangements in Each Operating Mode (cont)
Pin Name Pin No. 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Expanded Minimum Modes Mode 1 VCC P80/IRQ0 P81/IRQ1 P82/IRQ2/SCK1 P83/IRQ3/SCK2 P84/RXD1 P85/TXD1 P86/RXD2 P87/TXD2 VSS EXTAL XTAL VSS o E AS RD HWR LWR RFSH VCC MD0 MD1 MD2 STBY Mode 2 VCC P80/IRQ0 P81/IRQ1 P82/IRQ2/SCK1 P83/IRQ3/SCK2 P84/RXD1 P85/TXD1 P86/RXD2 P87/TXD2 VSS EXTAL XTAL VSS o E AS RD HWR LWR RFSH VCC MD0 MD1 MD2 STBY VCC P80/IRQ0 P81/IRQ1 P82/IRQ2/SCK1 P83/IRQ3/SCK2 P84/RXD1 P85/TXD1 P86/RXD2 P87/TXD2 VSS EXTAL XTAL VSS o E AS RD HWR LWR RFSH VCC MD0 MD1 MD2 STBY Expanded Maximum Modes Mode 3 Mode 4 VCC P80/IRQ0 P81/IRQ1 P82/IRQ2/SCK1 P83/IRQ3/SCK2 P84/RXD1 P85/TXD1 P86/RXD2 P87/TXD2 VSS EXTAL XTAL VSS o E AS RD HWR LWR RFSH VCC MD0 MD1 MD2 STBY
9
Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3 Pin Functions
Type Power Symbol VCC Pin No. 55, 88, 108 I/O Name and Function I Power: Connected to the power supply (+ 5 V). Connect all VCC pins to the system power supply (+ 5 V). The chip will not operate if any VCC pin is left unconnected. I Ground: Connected to ground (0 V). Connect all VSS pins to the system power supply (0 V). The chip will not operate if any VSS pin is left unconnected. I Crystal: Connected to a crystal oscillator. The crystal frequency should be double the desired system clock frequency. If an external clock is input at the EXTAL pin, the XTAL pin should be left open. I External Crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be double the desired system clock frequency. See section 8.2, "Oscillator Circuit," for examples of connections to a crystal and external clock. O System Clock: Supplies the system clock to peripheral devices. O Enable Clock: Supplies an E clock to peripheral devices. O Bus Request Acknowledge: Indicates that the bus right has been granted to an external device. Notifies an external device that issued a BREQ signal that it now has control of the bus.
VSS
3, 20, 37, 46, 64, 81, 97, 100 99
Clock
XTAL
EXTAL
98
o E System control BACK
101 102 48
10
Table 1-3 Pin Functions (cont)
Type System control Symbol BREQ STBY Pin No. 49 112 I/O Name and Function I Bus Request: Sent by an external device to the H8/510 chip to request the bus right. I Standby: A transition to the hardware standby mode (a power-down state) occurs when a Low input is received at the STBY pin. I/O Reset: A Low input resets the H8/510 chip. O Address Bus: Address output pins. I/O Data Bus: 16-bit bidirectional data bus. I Wait: Requests the CPU to insert one or more Tw states when accessing an off-chip address. O Address Strobe: Goes Low to indicate that there is a valid address on the address bus. O Refresh Cycle: Goes Low to indicate that the address output on the address bus is a refresh address. O Read: Goes Low to indicate that the CPU is reading an external address. O Low Write: Goes Low to indicate that the CPU is writing to an external address using the low data bus. O High Write: Goes Low to indicate that the CPU is writing to an external address using the high data bus.
Address bus Data bus Bus control
RES A23 - A16 A15 - A0 D15 - D0 WAIT AS RFSH
1 45 - 38 36 - 21 19 - 4 47 103 107
RD LWR HWR
104 106 105
11
Table 1-3 Pin Functions (cont)
Type Interrupt signals Symbol NMI Pin No. 2 I/O Name and Function I NonMaskable Interrupt: Highest priority interrupt request. The NMI control register (NMICR) determines whether the interrupt is requested on the rising or falling edge of the NMI input. I Interrupt Request 0, 1, 2, and 3: Maskable interrupt request pins.
IRQ0 IRQ1 IRQ2 IRQ3 Operating MD2 mode MD1 control MD0
89 90 91 92 111 110 109
I
Mode: Input pins for setting the MCU operating mode according to the table below. MD2 MD1 MD0 Mode Description 0 0 0 Mode 0 -- 0 0 1 Mode 1 Expanded minimum mode (8-bit bus) 0 1 0 Mode 2 Expanded minimum mode (16-bit bus) 0 1 1 Mode 3 Expanded maximum mode (8-bit bus) 1 0 0 Mode 4 Expanded maximum mode (16-bit bus) 1 0 1 Mode 5 -- 1 1 0 Mode 6 -- 1 1 1 Mode 7 -- The inputs at these pins are indicated in mode select bits 2 to 0 (MDS2 - MDS0) of the mode control register (MDCR).
12
Table 1-3 Pin Functions (cont)
Type 16-Bit freerunning timer (FRT) Symbol FTOA1 FTOA2 FTOB1 FTOB2 FTCI1 FTCI2 FTI1 FTI2 8-Bit timer TMO TMCI TMRI Serial communication interface TXD1 TXD2 RXD1 RXD2 SCK1 SCK2 A/D AN3 - AN0 converter AVCC AVSS ADTRG Pin No. 65 67 66 68 61 63 60 62 59 57 62 94 96 93 95 91 92 86 - 83 87 82 56 I/O Name and Function O FRT Output Compare A (channels 1 and 2): Output pins for the output compare A function of the free-running timer channels 1 and 2. O FRT Output Compare B (channels 1 and 2): Output pins for the output compare B function of the free-running timer channels 1 and 2. I FRT Counter Clock Input (channels 1 and 2): External clock input pins for the free-running counters (FRCs) of free-running timer channels 1 and 2. I FRT Input Capture (channels 1 and 2): Input capture pins for free-running timer channels 1 and 2. O 8-bit Timer Output: Compare-match output pin for the 8-bit timer. I 8-bit Timer Clock Input: External clock input pin for the 8-bit timer counter. I 8-bit Timer Counter Reset Input: High input at this pin resets the 8-bit timer counter. O Transmit Data: Data output pins for the serial communication interface. I Receive Data: Data input pins for the serial communication interface. I/O Serial Clock: Input/output pins for the serial interface clock. I Analog Input: Analog signal input pins. I Analog Reference Voltage: Reference voltage pin for the A/D converter. If not used, connect to VCC. I Analog Ground: Ground pin for the A/D converter. If not used, connect to VSS. I A/D Trigger: External trigger input pin for the A/D converter.
13
Table 1-3 Pin Functions (cont)
Type I/O ports Symbol P17 - P10 Pin No. 11 - 4 I/O Name and Function I/O Port 1: An 8-bit input/output port. The direction of each bit is determined by the port 1 data direction register (P1DDR). I/O Port 2: A 8-bit input/output port. The direction of each bit is determined by the port 2 data direction register (P2DDR). I/O Port 3: An 8-bit input/output port. The direction of each bit is determined by the port 3 data direction register (P3DDR). I/O Port 4: An 8-bit input/output port with Schmitt inputs. The direction of each bit is determined by the port 4 data direction register (P4DDR). I/O Port 5: An 8-bit input/output port. The direction of each bit is determined by the port 5 data direction register (P5DDR). I/O Port 6: An 8-bit input/output port. The direction of each bit is determined by the port 6 data direction register (P6DDR). I Port 7: A 4-bit input port. I/O Port 8: An 8-bit input/output port. The direction of each bit is determined by the port 8 data direction register (P8DDR).
P27 - P20
45 - 38
P37 - P30
54 - 47
P47 - P40
63 - 56
P57 - P50
72 - 65
P67 - P60
80 - 73
P73 - P70 P87 - P80
86 - 83 96 - 89
14
Section 2 MCU Operating Modes and Address Space
2.1 Overview
2.1.1 Selection of MCU Mode The H8/510 microcomputer unit (MCU) operates in four modes numbered 1, 2, 3, and 4. The mode is selected by the inputs at the mode pins (MD2 to MD0). Table 2-1 Operating Modes
MCU Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 MD2 Low Low Low Low High High High High MD1 Low Low High High Low Low High High MD0 Low High Low High Low High Low High Description -- Expanded minimum mode Expanded minimum mode Expanded maximum mode Expanded maximum mode -- -- -- CPU Mode -- Minimum mode Minimum mode Maximum mode Maximum mode -- -- -- Data Bus Width -- 8 Bits 16 Bits 8 Bits 16 Bits -- -- --
Note: Modes marked with dashes (--) cannot be used.
The expanded minimum modes (modes 1 and 2) support a maximum address space of 64 kbytes. The expanded maximum modes (modes 3 and 4) support a maximum address space of 16 Mbytes. The H8/510 does not support modes 0, 5, 6, and 7. The mode pins should never be set to these values. The MCU mode determines the size of the address space and the usage of I/O pins. 2.1.2 Register Control of MCU Mode The MCU operating mode is monitored by the mode control register (MDCR) described in table 2-2. Table 2-2 Mode Control Register
Name Mode control register Abbreviation MDCR Read/Write R Address H'FF19
15
2.2 Mode Control Register (MDCR)
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 * R 1 MDS1 * R 0 MDS0 * R
* Determined by MD2 to MD0 inputs.
The MDCR bits are set by the inputs at the mode pins (MD2 to MD0). MDCR is an 8-bit register that is used to monitor the current operating mode of the H8/510. The MDCR bits can be read but not written. Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the values of the mode pins (MD2 to MD0) thus indicating the current MCU mode. MDS2 corresponds to MD2, MDS1 to MD1, and MDS0 to MD0.
2.3 Mode Descriptions
Mode 1 (Expanded Minimum Mode): Mode 1 supports a maximum 64-kbyte address space which is accessed via an 8-bit data bus. The byte area register is ignored. (See section 15, "Bus Controller," for details of the byte area register). Mode 2 (Expanded Minimum Mode): Mode 2 supports a maximum 64-kbyte address space that is accessed via a 16-bit data bus. Part of the address space, designated by the byte area register, is accessed via an 8-bit data bus. Port 1 is used as part of the data bus. Mode 3 (Expanded Maximum Mode): Mode 3 supports a maximum 16-Mbyte address space that is accessed via an 8-bit bus. The byte area register is ignored. Port 2 is used as part of the address bus. Mode 4 (Expanded Maximum Mode): Mode 4 supports a maximum 16-Mbyte address space
16
that is accessed via a 16-bit data bus. Part of the address space, designated by the byte area register, is accessed via an 8-bit data bus. Port 1 is used as part of the data bus. Port 2 is used as part of the address bus.
2.4 Pin Functions in Each MCU Mode
The functions of the I/O ports depend on the MCU mode. Table 2-3 lists the pin functions in modes 1 to 4. For a more detailed description of the control of pin functions, see section 9, "I/O Ports."
17
Table 2-3 Pin Functions in Each MCU Mode
MCU Mode Expanded Minimum Modes Expanded Maximum Modes Mode 1 Mode 2 Mode 3 Mode 4 I/O port Data bus I/O port Data bus (D7 - D0) (D7 - D0) I/O port I/O port Address bus Address bus (A23 - A16) (A23 - A16) I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port/BREQ I/O port/BREQ I/O port/BREQ I/O port/BREQ I/O port/BACK I/O port/BACK I/O port/BACK I/O port/BACK I/O port/WAIT I/O port/WAIT I/O port/WAIT I/O port/WAIT I/O port* I/O port* I/O port* I/O port* I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port* I/O port I/O port I/O port I/O port Input port* Input port* Input port* Input port* I/O port* I/O port* I/O port* I/O port*
Port Port 1 Port 2 Port 3 P37 P36 P35 P34 P33 P32 P31 P30 P57 P56 P55 P54 P53 P52 P51 P50
Port 4 Port 5
Port 6 Port 7 Port 8
* Also used as input/output pins for on-chip supporting modules.
18
2.5 Memory Map in Each MCU Mode
Figure 2-1 shows a memory map in modes 1 to 4.
Expanded Minimum Modes Mode 1
8 bits H'0000 H'0000
Expanded Maximum Modes Mode 2
16 bits H'000000
Mode 3
8 bits H'000000
Mode 4
16 bits
Vector tables
H'00FF H'00FF
Vector tables
H'0001FF
Vector tables
H'0001FF
Vector tables
Memory
Page 0
Memory
Page 0
Memory
Page 0
Memory
Page 0
H'FE80
H'FE80
H'00FE80
H'00FE80
Register field
H'FF80 H'FF80
Register field
H'00FF80
Register field
H'00FF80
Register field External I/O
H'010000
External I/O
H'FFFF H'FFFF
External I/O
H'010000
External I/O
Page 1
Page 1
H'020000
H'020000
Memory
Memory
H'FF0000
H'FF0000
Page 255
Page 255
H'FFFFFF
H'FFFFFF
Figure 2-1 Memory Map in Each MCU Mode
Section 3 CPU
3.1 Overview
The H8/510 chip has the H8/500 Family CPU: a high-speed central processing unit designed for realtime control of a wide range of medium-scale office and industrial equipment. It features eight 16-bit general registers, internal 16-bit data paths, and an optimized instruction set. Section 3 summarizes the CPU architecture and instruction set. 3.1.1 Features The main features of the H8/500 CPU are listed below. * General-register machine -- Eight 16-bit general registers -- Seven control registers (two 16-bit registers, five 8-bit registers) * High speed: maximum 10 MHz At 10 MHz a register-register add operation takes only 200 ns. * Address space managed in 64-kbyte pages, expandable to 16 Mbytes Page registers make four pages available simultaneously: a code page, stack page, data page, and extended page. * Two CPU operating modes: -- Minimum mode: Maximum 64-kbyte address space -- Maximum mode: Maximum 16-Mbyte address space * Highly orthogonal instruction set Addressing modes and data sizes can be specified independently within each instruction. * Addressing modes Register-register and register-memory operations are supported. * Optimized for efficient programming in C language In addition to the general registers and orthogonal instruction set, the CPU has special short formats for frequently-used instructions and addressing modes.
21
3.1.2 Address Space The CPU has two operating modes as shown in figure 3-1. The CPU operating mode is selected by the input to the mode pins (MD2 to MD0).
Minimum mode CPU operating mode Maximum mode
Maximum address space: 64 kbytes
Maximum address space: 16 Mbytes
Figure 3-1 CPU Operating Modes Figure 3-2 compares the memory maps of these two modes.
H'000000 Page 0 (64 kbytes) H'00FFFF H'010000 Page 1 (64 kbytes) H'01FFFF H'020000 Maximum mode Minimum mode
H'FF0000 Page 255 (64 kbytes) H'FFFFFF
Figure 3-2 Memory Map
22
3.1.3 Register Configuration Figure 3-3 shows the register structure of the CPU. There are two groups of registers: the general registers (Rn) and control registers (CR).
General registers (Rn) 15 R0 R1 R2 R3 R4 R5 R6 R7 Control registers (CR) 15 PC (FP) (SP)
0
FP: Frame Pointer SP: Stack Pointer
0 PC: Program Counter
SR
CCR 15 87 0 SR: Status Register CCR: Condition Code Register CP DP EP TP BR CP: Code page register DP: Data Page register EP: Extended Page register TP: sTack Page register BR: Base Register
T -- -- -- -- I2 I1 I0 -- -- -- -- N Z V C
Figure 3-3 Registers in the CPU
23
3.2 CPU Register Descriptions
3.2.1 General Registers All eight of the 16-bit general registers are functionally alike; there is no distinction between data registers and address registers. When these registers are accessed as data registers, either byte or word size can be selected. R6 and R7, in addition to functioning as general registers, have special assignments. R7 is the stack pointer, used implicitly in exception handling and subroutine calls. It can be designated by the name SP, which is synonymous with R7. As indicated in figure 3-4, it points to the top of the stack. It is also used implicitly by the LDM and STM instructions, which load and store multiple registers from and to the stack and pre-decrement or post-increment R7 accordingly. R6 functions as a frame pointer (FP). The LINK and UNLK instructions use R6 implicitly to reserve or release a stack frame.
Unused area SP Stack area
Figure 3-4 Stack Pointer
24
3.2.2 Control Registers The CPU control registers (CR) include a 16-bit program counter (PC), a 16-bit status register (SR), four 8-bit page registers, and one 8-bit base register (BR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Status Register (SR): This 16-bit register contains internal status information. The lower half of the status register is referred to as the condition code register (CCR): it can be accessed as a separate condition code byte.
CCR Bit 15 T 14 -- 13 -- 12 -- 11 -- 10 I2 9 I1 8 I0 7 -- 6 -- 5 -- 4 -- 3 N 2 Z 1 V 0 C
Bit 15--Trace (T): When this bit is set to 1, the CPU operates in trace mode and generates a trace exception after every instruction. See section 4.4, "Trace" for a description of the trace exception-handling sequence. When the value of this bit is 0, instructions are executed in normal continuous sequence. This bit is cleared to 0 at a reset. Bits 14 to 11--Reserved: These bits cannot be modified and are always read as 0. Bits 10 to 8--Interrupt Mask (I2, I1, I0): These bits indicate the interrupt request mask level (7 to 0). As shown in table 3-1, an interrupt request is not accepted unless it has a higher level than the value of the mask. A nonmaskable interrupt (NMI) is accepted at any mask level. After an interrupt is accepted, I2, I1, and I0 are changed to the level of the interrupt. Table 3-2 indicates the values of the I bits after an interrupt is accepted. A reset sets all three of theses bits (I2, I1, and I0) to 1, masking all interrupts except NMI.
25
Table 3-1 Interrupt Mask Levels
Mask Level 7 6 5 4 3 2 1 0 Mask Bits I2 I1 I0 111 110 101 100 011 010 001 000
Priority High
Low
Interrupts Accepted NMI Level 7 and NMI Levels 7 to 6 and NMI Levels 7 to 5 and NMI Levels 7 to 4 and NMI Levels 7 to 3 and NMI Levels 7 to 2 and NMI Levels 7 to 1 and NMI
Table 3-2 Interrupt Mask Bits after an Interrupt is Accepted
Level of Interrupt Accepted NMI 7 6 5 4 3 2 1 I2 1 1 1 1 1 0 0 0 I1 1 1 1 0 0 1 1 0 I0 1 1 0 1 0 1 0 1
26
Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 0. Bit 3--Negative (N): This bit indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry (C): This bit is set to 1 when a carry or borrow occurs at the most significant bit, and is cleared to 0 (or left unchanged) at other times. The specific changes that occur in the condition code bits when each instruction is executed are listed in appendix A.1, "Instruction Tables." See the H8/500 Series Programming Manual for further details. Page Registers: The code page register (CP), data page register (DP), extended page register (EP), and stack page register (TP) are 8-bit registers that are used only in the maximum mode. No use of their contents is made in the minimum mode. In the maximum mode, the page registers combine with the program counter or general registers to generate 24-bit effective addresses as shown in figure 3-5, thereby expanding the program area, data area, and stack area.
27
Page register 8 Bits
PC or general register 16 Bits
CP
PC
R0 R1 DP R2 R3 @ aa : 16
R4 EP R5
R6 TP R7
24 Bits (effective address)
Figure 3-5 Combinations of Page Registers with Other Registers Code Page Register (CP): The code page register and the program counter combine to generate a 24-bit program code address. In the maximum mode, the code page register is initialized at a reset to a value loaded from the vector table, and both the code page register and program counter
28
are saved and restored in exception handling. Data Page Register (DP): The data page register combines with general registers R3 to R0 to generate a 24-bit effective address. The data page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R3 to R0, and in the 16-bit absolute addressing mode (@aa:16). The data page register is rewritten by the LDC instruction. Extended Page Register (EP): The extended page register combines with general register R4 or R5 to generate a 24-bit operand address. The extended page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R4 or R5. The extended page can be used as an additional data page. Stack Page Register (TP): The stack page register combines with R6 (FP) or R7 (SP) to generate a 24-bit stack address. The stack page register contains the upper 8 bits of the address. It is used to calculate effective addresses in the register indirect addressing mode using R6 or R7, in exception handling, and subroutine calls. Base Register (BR): This 8-bit register stores the base address used in the short absolute addressing mode (@aa:8). In this addressing mode a 16-bit effective address in page 0 is generated by using the contents of the base register as the upper 8 bits and an address given in the instruction code as the lower 8 bits. See figure 3-6. In the short absolute addressing mode the address is always located in page 0.
8 Bits
8 Bits
BR
@ aa : 8
16 Bits (effective address)
Figure 3-6 Short Absolute Addressing Mode and Base Register
29
3.2.3 Initial Register Values When the CPU is reset, its internal registers are initialized as shown in table 3-3. Note that the stack pointer (R7) and base register (BR) are not initialized to fixed values. Also, of the page registers used in maximum mode, only the code page register (CP) is initialized; the other three page registers come out of the reset state with undetermined values. Accordingly, in the minimum mode the first instruction executed after a reset should initialize the stack pointer. The base register must also be initialized before the short absolute addressing mode (@aa:8) is used. In the maximum mode, the first instruction executed after a reset should initialize the stack page register (TP) and the next instruction should initialize the stack pointer. Later instructions should initialize the base register and the other page registers as necessary.
30
Table 3-3 Initial Values of Registers
Initial Value Maximum Mode Undetermined
Register General registers 15 R7 - R0 Control registers 15 PC SR CCR
Minimum Mode 0 Undetermined
0
Loaded from vector table
Loaded from vector table
15 87 0 T- - - - I2I1I0 - - - - NZVC 7 0 CP 7 0 DP 7 0 EP 7 0 TP 7 0 BR
H'070x (x: undetermined) Undetermined Undetermined Undetermined Undetermined Undetermined
H'070x (x: undetermined) Loaded from vector table Undetermined Undetermined Undetermined Undetermined
3.3 Data Formats
The H8/500 can process 1-bit data, 4-bit BCD data, 8-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data. * Bit manipulation instructions operate on 1-bit data. * Decimal arithmetic instructions operate on 4-bit BCD data. * Almost all instructions operate on byte and word data. * Multiply and divide instructions operate on longword data. 3.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in table 3-4.
31
Bit data locations are specified by bit number. Bit 15 is the most significant bit. Bit 0 is the least significant bit. BCD and byte data are stored in the lower 8 bits of a general register. Word data use all 16 bits of a general register. Longword data use two general registers: the upper 16 bits are stored in Rn (n must be an even number); the lower 16 bits are stored in Rn+1. Operations performed on BCD data or byte data do not affect the upper 8 bits of the register. Table 3-4 General Register Data Formats
Data Type 1-Bit Rn BCD
15 8 Don't care 7 Upper digit 4 3 Lower digit 0
Register No.
Data Structure
15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0
Rn Byte
15
8 Don't care
7 MSB LSB
0
Rn Word
15
0 LSB
Rn Longword Rn* Rn+1*
MSB
31 MSB Upper 16 bits Lower 16 bits 15 LSB
16
0
* For longword data n must be even (0, 2, 4, or 6).
3.3.2 Data Formats in Memory Table 3-5 indicates the data formats in memory. Instructions that access bit data in memory have byte or word operands. The instruction specifies a bit number to indicate a specific bit in the operand. Access to word data in memory must always begin at an even address. Access to word data starting at an odd address causes an address error. The upper 8 bits of word data are stored in address n (where n is an even number); the lower 8 bits are stored in address n+1.
32
Table 3-5 Data Formats in Memory
Data Type 1-Bit (in byte operand data) Data Format
7 Address n 1-Bit (in word operand data) Even address Odd address Byte 15 7 14 6 13 5 12 4 11 3 10 2 9 1 7 6 5 4 3 2 1
0 0
8 0
Address n Word
MSB
LSB
Even address Odd address
MSB
Upper 8 bits Lower 8 bits LSB
When the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size. Similarly, when the stack is accessed by an instruction using the pre-decrement or postincrement register indirect addressing mode specifying R7 (@-R7 or @R7+), which is the stack pointer, word access is performed regardless of the operand size specified in the instruction. An address error will therefore occur if the stack pointer indicates an odd address. Programs should be coded so that the stack pointer always indicates an even address. Table 3-6 shows the data formats on the stack.
33
Table 3-6 Data Formats on the Stack
Data Type Byte data on stack Data Format
Even address Odd address Word data on stack Even address Odd address MSB MSB
Don't-care LSB
Upper 8 bits Lower 8 bits LSB
3.4 Instructions
3.4.1 Basic Instruction Formats There are two basic CPU instruction formats: the general format and the special format. General Format: This format consists of an effective address (EA) field, an effective address extension field, and an operation code (OP) field. The effective address is placed before the operation code because this results in faster execution of the instruction.
Effective address field Effective address extension Operation code
* Effective address field:
One byte containing information used to calculate the effective address of an operand.
* Effective address extension: Zero to two bytes containing a displacement value, immediate data, or an absolute address. The size of the effective address extension is specified in the effective address field. * Operation code: Defines the operation to be carried out on the operand located at the address calculated from the effective address information. Some instructions (DADD, DSUB, MOVFPE, MOVTPE) have an extended format in which the operand code is preceded by a one-byte prefix code.
34
* (Example of prefix code in DADD instruction)
Effective address Prefix code Operation code
10100rrr
00000000
10100rrr
Special Format: In this format the operation code comes first, followed by the effective address field and effective address extension. This format is used in branching instructions, system control instructions, and other instructions that can be executed faster if the operation is specified before the operand.
Operation code
Effective address field
Effective address extension
* Operation code: One or two bytes defining the operation to be performed by the instruction. * Effective address field and effective address extension: Zero to three bytes containing information used to calculate an effective address. 3.4.2 Addressing Modes The CPU supports 7 addressing modes: (1) register direct; (2) register indirect; (3) register indirect with displacement; (4) register indirect with pre-decrement or post-increment; (5) immediate; (6) absolute; and (7) PC-relative. Due to the highly orthogonal nature of the instruction set, most instructions having operands can use any applicable addressing mode from (1) through (6). The PC-relative mode (7) is used by branching instructions. In most instructions, the addressing mode is specified in the effective address field. The effectiveaddress extension, if present, contains a displacement, immediate data, or an absolute address. Table 3-7 indicates how the addressing mode is specified in the effective address field.
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Table 3-7 Addressing Modes
No. 1 Addressing Mode Register direct Mnemonic Rn EA Field 1 0 1 0 Sz r r r
*1 *2
EA Extension None
2 3
Register indirect Register indirect with displacement
@Rn @(d:8, Rn) @(d:16, Rn)
1 1 0 1 Sz r r r 1 1 1 0 Sz r r r 1 1 1 1 Sz r r r 1 0 1 1 Sz r r r
None Displacement (1 byte) Displacement (2 bytes)
4
Register indirect with pre-decrement Register indirect with post-increment Immediate
@-Rn @Rn+
None 1 1 0 0 Sz r r r
5
#xx: 8 #xx: 16
00000100 00001100 0 0 0 0 Sz 1 0 1 0 0 0 1 Sz 1 0 1 No EA field. Addressing mode is specified in the operation code.
Immediate data (1 byte) Immediate data (2 bytes) 1-byte absolute address (offset from BR) 2-byte absolute address 1- or 2-byte displacement
6
Absolute *3
@aa: 8 @aa: 16
7
PC-relative
disp
Notes: * 1 Sz: Specifies the operand size. When Sz = 0: byte operand When Sz = 1: word operand * 2 rrr: Register number field, specifying a general register number. 0 0 0 -- R0 0 0 1 -- R1 0 1 0 -- R2 0 1 1 -- R3 1 0 0 -- R4 1 0 1 -- R5 1 1 0 -- R6 1 1 1 -- R7 * 3 The @aa: 8 addressing mode is also referred to as the short absolute addressing mode.
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3.4.3 Effective Address Calculation Table 3-8 explains how the effective address is calculated in each addressing mode. Table 3-8 Effective Address Calculation
No. 1 Addressing Mode Effective Address Calculation Register direct -- Rn 1010Sz rrr Register indirect @Rn 1101Sz rrr -- Effective Address Operand is contents of Rn
2
23 DP *1
15 Rn
0
Or TP or EP *2 3 Register indirect with displacement @(d:8,Rn) 8 Bits 15 Rn 15 0 Displacement with sign extension 16 Bits 15 Rn 15 Displacement 4 Register indirect 15 with pre-decrement @-Rn 1011Sz rrr 0 Rn 1 or 2 0
0
23 DP
*1
15 Result
0
+
Or TP or EP *2
1110Sz
rrr
@(d:16,Rn) 1111Sz rrr
0
23 DP
*1
15 Result
0
Or TP or EP *2
+
23 DP *1 15 Result 0
-
Or TP or EP *2
Rn is decremented by -1 or -2 before instruction execution.*3*4*5 23 DP *1 Or TP or EP *2 15 Rn 0
Register indirect -- with post-increment @Rn+ Rn is incremented by +1 or +2 1100Sz rrr after instruction execution.*3*4*5 37
Table 3-8 Effective Address Calculation (cont)
No. 5 Addressing Mode Effective Address Calculation Absolute address -- @aa:8 0000Sz101 @aa:16 0001Sz101 6 Immediate #xx:8 00000100 #xx:16 00001100 7 -- Effective Address 23 15 0 H'00 BR EA extension data 23 DP -- 15 0 EA extension data
Operand is 1-byte EA extension data.
--
Operand is 2-byte EA extension data.
PC-relative 8 bits disp:8 15 0 No EA code PC Specified in OP code 15 0 Displacement with sign extension disp:16 16 bits No EA code 15 Specified in OP code 15 Displacement
23 CP
*1
15 Result
0
23 0 PC 0 CP *1
15 Result
0
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Notes: * 1 The page register is ignored in minimum mode. * 2 The page register used in addressing modes 2, 3, and 4 depends on the general register: DP for R0, R1, R2, or R3; EP for R4 or R5; TP for R6 or R7. * 3 Decrement by -1 for a byte operand, and by -2 for a word operand. * 4 The pre-decrement or post-increment is always 2 when R7 is specified, even if the operand is byte size. * 5 The drawing below shows what happens when the @-SP and @ SP+ addressing modes are used to save and restore the stack pointer.
SP
Old SP-2 (upper byte) Old SP-2 (lower byte)
SP
SP MOV.W SP, @-SP MOV.W @SP+, SP
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3.5 Instruction Set
3.5.1 Overview The main features of the CPU instruction set are: * A general-register architecture. * Orthogonality. Addressing modes and data sizes can be specified independently in each instruction. * Addressing modes supporting register-register and register-memory operations. * Affinity for high-level languages, particularly C, with short formats for frequently-used instructions and addressing modes. The CPU instruction set includes 63 types of instructions, listed by function in table 3-9. Table 3-9 Instruction Classification
Function Data transfer Arithmetic operations Instructions MOV, LDM, STM, XCH, SWAP, MOVTPE, MOVFPE ADD, SUB, ADDS, SUBS, ADDX, SUBX, DADD, DSUB, MULXU, DIVXU, CMP, EXTS, EXTU, TST, NEG, CLR, TAS Logic operations AND, OR, XOR, NOT Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Bit manipulation BSET, BCLR, BTST, BNOT Branch Bcc*, JMP, PJMP, BSR, JSR, PJSR, RTS, PRTD, PRTS, RTD, SCB (/F, /NE, /EQ) System control TRAPA, TRAP/VS, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP, LINK, UNLK Total * Bcc is a conditional branch instruction in which cc represents a condition code. Types 7 17
4 8 4 11 12 63
Tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. The MOV, ADD, and CMP instructions have special short formats, which are listed in table 3-17. For detailed descriptions of the instructions, refer to the H8/500 Series Programming Manual. The notation used in tables 3-10 to 3-17 is defined below.
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Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR CR Control register PC Program counter CP Code page register SP Stack pointer FP Frame pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move Exchange Not
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3.5.2 Data Transfer Instructions Table 3-10 describes the seven data transfer instructions. Table 3-10 Data Transfer Instructions
Instruction Data MOV transfer MOV:G MOV:E MOV:I MOV:F MOV:L MOV:S LDM STM XCH SWAP MOVTPE Size* B/W B W B/W B/W B/W W W W B B Function (EAs) (EAd), #IMM (EAd) Moves data between two general registers, or between a general register and memory, or moves immediate data to a general register or memory.
MOVFPE
B
Stack Rn (register list) Pops data from the stack to one or more registers. Rn (register list) stack Pushes data from one or more registers onto the stack. Rs Rd Exchanges data between two general registers. Rd (upper byte) Rd (lower byte) Exchanges the upper and lower bytes in a general register. Rn (EAd) Transfers data from a general register to memory in synchronization with the E clock. (EAs) Rd Transfers data from memory to a general register in synchronization with the E clock.
Note: B--byte; W--word
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3.5.3 Arithmetic Instructions Table 3-11 describes the 17 arithmetic instructions. Table 3-11 Arithmetic Instructions
Instruction Arithmetic ADD operations ADD:G ADD:Q SUB ADDS SUBS ADDX SUBX Size B/W B/W B/W B/W B/W B/W B/W Function Rd (EAs) Rd, (EAd) #IMM (EAd) Performs addition or subtraction on data in a general register and data in another general register or memory, or on immediate data and data in a general register or memory.
DADD DSUB MULXU
B B B/W
DIVXU
B/W
CMP CMP:G CMP:E CMP:I Note: B--byte; W--word
B/W B W
Rd (EAs) C Rd Performs addition or subtraction with carry or borrow on data in a general register and data in another general register or memory, or on immediate data and data in a general register or memory. (Rd)10 (Rs)10 C (Rd)10 Performs decimal addition or subtraction on data in two general registers. Rd x (EAs) Rd Performs 8-bit x 8-bit or 16-bit x 16-bit unsigned multiplication on data in a general register and data in another general register or memory, or on data in a general register and immediate data. Rd / (EAs) Rd Performs 16-bit / 8-bit or 32-bit / 16-bit unsigned division on data in a general register and data in another general register or memory, or on data in a general register and immediate data. Rn - (EAs), (EAd) - #IMM Compares data in a general register with data in another general register or memory, or with immediate data, or compares immediate data with data in memory.
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Table 3-11 Arithmetic Instructions (cont)
Instruction Arithmetic operations Size B Function ( of ) ( of ) Converts byte data in a general register to word data by extending the sign bit. 0 ( of ) Converts byte data in a general register to word data by padding with zero bits. (EAd) - 0 Compares general register or memory contents with 0. 0 - (EAd) (EAd) Obtains the two's complement of general register or memory contents. 0 (EAd) Clears general register or memory contents to 0. (EAd) -- 0, (1)2 ( of ) Tests general register or memory contents, then sets the most significant bit (bit 7) to 1.
EXTS
EXTU
B
TST NEG
B/W B/W
CLR TAS
B/W B
Note: B--byte; W--word
3.5.4 Logic Operations Table 3-12 lists the four instructions that perform logic operations. Table 3-12 Logic Operation Instructions
Instruction Logical operations Size B/W Function Rd (EAs) Rd Performs a logical AND operation on a general register and another general register, memory, or immediate data. Rd (EAs) Rd Performs a logical OR operation on a general register and another general register, memory, or immediate data. Rd (EAs) Rd Performs a logical exclusive OR operation on a general register and another general register, memory, or immediate data. (EAd) (EAd) Obtains the one's complement of general register or memory contents.
AND
OR
B/W
XOR
B/W
NOT
B/W
Note: B--byte; W--word
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3.5.5 Shift Operations Table 3-13 lists the eight shift instructions. Table 3-13 Shift Instructions
Instruction Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: B--byte; W--word Size B/W B/W B/W B/W B/W B/W B/W B/W Function (EAd) shift (EAd) Performs an arithmetic shift operation on general register or memory contents. (EAd) shift (EAd) Performs a logical shift operation on general register or memory contents. (EAd) rotate (EAd) Rotates general register or memory contents. (EAd) rotate through carry (EAd) Rotates general register or memory contents through the C (carry) bit.
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3.5.6 Bit Manipulations Table 3-14 describes the four bit-manipulation instructions. Table 3-14 Bit-Manipulation Instructions
Instruction Bit BSET manipulations Size B/W Function ( of ) Z, 1 ( of ) Tests a specified bit in a general register or memory, then sets the bit to 1. The bit is specified by a bit number given in immediate data or a general register. ( of ) Z, 0 ( of ) Tests a specified bit in a general register or memory, then clears the bit to 0. The bit is specified by a bit number given in immediate data or a general register. ( of ) Z, ( of ) Tests a specified bit in a general register or memory, then inverts the bit. The bit is specified by a bit number given in immediate data or a general register. ( of ) Z Tests a specified bit in a general register or memory. The bit is specified by a bit number given in immediate data or a general register.
BCLR
B/W
BNOT
B/W
BTST
B/W
Note: B--byte; W--word
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3.5.7 Branching Instructions Table 3-15 describes the 11 branching instructions. Table 3-15 Branching Instructions
Instruction Branch Bcc Size -- Function Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP PJMP BSR JSR PJSR RTS -- -- -- -- -- -- Description Always (true) Never (false) High Low or Same Carry Clear (High or Same) Carry Set (Low) Not Equal Equal Overflow Clear Overflow Set Plus Minus Greater or Equal Less Than Greater Than Less or Equal Condition True False CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
Branches unconditionally to a specified address in the same page. Branches unconditionally to a specified address in a specified page. Branches to a subroutine at a specified address in the same page. Branches to a subroutine at a specified address in the same page. Branches to a subroutine at a specified address in a specified page. Returns from a subroutine in the same page.
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Table 3-15 Branching Instructions (cont)
Instruction Branch PRTS RTD PRTD SCB/F SCB/NE SCB/EQ Size -- -- -- -- -- -- Function Returns from a subroutine in a different page. Returns from a subroutine in the same page and adjusts the stack pointer. Returns from a subroutine in a different page and adjusts the stack pointer. Controls a loop using a loop counter and/or a specified termination condition.
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3.5.8 System Control Instructions Table 3-16 describes the 12 system control instructions. Table 3-16 System Control Instructions
Instruction System TRAPA control TRAP/VS RTE LINK UNLK SLEEP LDC Size -- -- -- -- -- -- B/W* Function Generates a trap exception with a specified vector number. Generates a trap exception if the V bit is set to 1 when the instruction is executed. Returns from an exception-handling routine. FP @-SP; SP FP; SP + #IMM SP Creates a stack frame. FP SP; @SP+ FP Deallocates a stack frame created by the LINK instruction. Causes a transition to the power-down state. (EAs) CR Moves immediate data or general register or memory contents to a specified control register. CR (EAd) Moves control register data to a specified general register or memory location. CR #IMM CR Logically ANDs a control register with immediate data. CR #IMM CR Logically ORs a control register with immediate data. CR #IMM CR Logically exclusive-ORs a control register with immediate data. PC + 1 PC No operation. Only increments the program counter.
STC
B/W*
ANDC ORC XORC
B/W* B/W* B/W*
NOP
--
* The size depends on the control register.
When using the LDC and STC instructions to stack and unstack the BR, CCR, TP, DP, and EP control registers in the H8/500 family, note the following point. H8/500 hardware does not permit byte access to the stack. If the LDC.B or STC.B assembler mnemonic is coded with the @R7 + (@SP+) or @-R7 (@-SP) addressing mode, the stackpointer addressing mode takes precedence and hardware automatically performs word access.
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Specifically, the LDC.B and STC.B instructions are executed as follows. The following applies only to the stack-pointer addressing modes. In addressing modes that do not use the stack pointer, byte data access is performed as specified by the assembler mnemonic. 1 STC.B EP, @-SP When word data access is applied to EP, both EP and DP are accessed. This instruction stores EP at address SP (old) -2, and DP at address SP (old) -1.
Old SP - 2 Old SP - 1 Old SP Before execution EP a DP b New SP New SP + 1 New SP + 2 After execution a b
2
LDC.B @SP+, EP When word data access is applied to EP, both EP and DP are accessed. This instruction loads EP from address SP (old), and DP from address SP (old) +1, updating the DP value as well as the EP value.
EP Old SP Old SP + 1 Old SP + 2 Before execution a b DP New SP - 2 New SP - 1 New SP After execution EP a DP b
3
STC.B CCR, @-SP When word data access is applied to CCR, only CCR is accessed. This instruction stores identical CCR contents at both address SP (old) -2 and address SP (old) -1.
CCR a a a
Old SP - 2 Old SP - 1 Old SP Before execution
New SP New SP + 1 New SP + 2
After execution
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4
LDC.B @SP+, CCR When word data access is applied to CCR, only CCR is accessed. This instruction loads CCR from address SP (old) +1. Note that the value in address SP (old) is not loaded.
CCR Old SP Old SP + 1 Old SP + 2 Before execution a b New SP - 2 New SP - 1 New SP After execution CCR b
BR, DP, and TP are accessed in the same way as CCR. When DP is specified, both EP and DP are accessed, but when CCR, BR, DP, or TP is specified, only the specified register is accessed.
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3.5.9 Short-Format Instructions The ADD, CMP, and MOV instructions have special short formats. Table 3-17 lists these short formats together with the equivalent general formats. The short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster. Table 3-17 Short-Format Instructions and Equivalent General Formats
Short-Format Execution Equivalent GeneralExecution Instruction Length States *2 Format Instruction Length States *2 ADD:Q #xx,Rd *1 2 2 ADD:G #xx:8,Rd 3 3 CMP:E #xx:8,Rd 2 2 CMP:G.B #xx:8,Rd 3 3 CMP:I #xx:16,Rd 3 3 CMP:G.W #xx:16,Rd 4 4 MOV:E #xx:8,Rd 2 2 MOV:G.B #xx:8,Rd 3 3 MOV:I #xx:16,Rd 3 3 MOV:G.W #xx:16,Rd 4 4 MOV:L @aa:8,Rd 2 5 MOV:G @aa:8,Rd 3 5 MOV:S Rs,@aa:8 2 5 MOV:G Rs,@aa:8 3 5 MOV:F @(d:8,R6),Rd 2 5 MOV:G @(d:8,R6),Rd 3 5 MOV:F Rs,@(d:8,R6) 2 5 MOV:G Rs,@(d:8,R6) 3 5 Notes: * 1 The ADD:Q instruction accepts other destination operands in addition to a general register, but the immediate data value (#xx) is limited to 1 or 2. * 2 Number of execution states for access to a general register.
3.6 Operating Modes
The CPU operates in one of two modes: minimum mode or maximum mode. These modes are selected by the mode pins MD2 to MD0. 3.6.1 Minimum Mode The minimum mode supports a maximum address space of 64-kbytes. The page registers are ignored. Instructions that branch across page boundaries (PJMP, PJSR, PRTS, PRTD) are invalid.
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3.6.2 Maximum Mode In maximum mode the page registers are valid, expanding the maximum address space to 16 Mbytes. The address space is divided into 64-kbyte pages. The pages are separate; it is not possible to move continuously across a page boundary. It is possible to move from one page to another with branching instructions (PJMP, PJSR, PRTS, PRTD, TRAPA), or by branching to an interrupt-handling routine. It is not necessary for a program to be contained in a single 64-kbyte page. When data access crosses a page boundary, the program must rewrite the page register before it can access the data in the next page. For further information on the operating modes, see section 2, "MCU Operating Modes and Address Space."
3.7 Basic Operational Timing
3.7.1 Overview The CPU operates on a system clock (o) which is created by dividing an oscillator frequency (fosc) by two. One system clock cycle is referred to as a "state." The CPU accesses memory in a bus cycle consisting of two or three states. 1. Two-State Access: Is provided for high-speed processing. No wait states (Tw) can be inserted. Figure 3-7 shows the two-state access cycle. 2. Three-State Access: Is provided for interfacing low-speed devices. Figure 3-8 shows the three-state access cycle. Wait states (Tw) can be inserted by the wait-state controller (WSC). 3. Access to On-Chip Register Field: The access cycle consists of three states. The data bus is 8 bits wide. Figure 3-9 shows the on-chip register field access cycle. Figure 3-10 includes the pin states.
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3.7.2 Two-State Access Cycle
Bus cycle T1 state o T2 state
A 23 to A 0
Address
RD, AS
D15 to D 0
Read data
HWR, LWR
D15 to D 0
Write data
Figure 3-7 Two-State Access Cycle
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3.7.3 Three-State Access Cycle
Read cycle T1 state T2 state T3 state
o
A 23 to A 0
Address
AS * RD High HWR, LWR *
D15 to D0 (read access) D15 to D0 (write access)
Read data
Write data
* Write access
Figure 3-8 Three-State Access Cycle
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3.7.4 On-Chip Register Field Access Cycle
Bus cycle T1 state T2 state T3 state
o
Internal address bus
Address
Internal Read signal
Internal data bus (read access) Internal Write signal
Read data
Internal data bus (Write access)
Write data
Figure 3-9 Register Field Access Cycle
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3.7.5 Pin States during Register Field Access
T1
T2
T3
o
A 23 to A 0
Address High
AS, RD, HWR, LWR D15 to D 0 High-impedance
Figure 3-10 Pin States during Register Field Access
3.8 CPU States
3.8.1 Overview The CPU has five states: the program execution state, exception-handling state, bus-released state, reset state, and power-down state. The power-down state is further divided into the sleep mode, software standby mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a map of the state transitions.
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State
Program execution state The CPU executes program instructions in sequence.
Exception-handling state A transient state in which the CPU executes a hardware sequence (saving the program counter and status register, fetching a vector from the vector table, etc.) triggered by a reset, interrupt, or other exception.
Bus-released state The state in which the CPU has released the external bus in response to a bus request signal from an external device, and is waiting for the bus to be returned.
Reset state The state in which the CPU and all on-chip supporting modules have been initialized and are stopped.
Power-down state A state in which some or all of the clock signals are stopped to conserve power.
Sleep mode
Software standby mode
Hardware standby mode
Figure 3-11 Operating States
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BREQ = 1 BREQ = 0
Program execution state SLEEP SLEEP instruction instruction with standby flag set Sleep mode
BREQ = 1
BREQ = 0 End of exception handling Request for exception handling
Bus-released state
Interrupt request Exception-handling state NMI Software standby mode
RES = 1
Reset state * 1
STBY = 1, RES = 0
Hardware standby mode
*2
Notes: *1 From any state except the hardware standby mode, a transition to the reset state occurs whenever RES goes Low. *2 A transition to the hardware standby mode from any state occurs when STBY goes Low.
Figure 3-12 State Transitions 3.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. 3.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to an interrupt, trap instruction, address error, or other exception. In this state the CPU carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine.
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In the hardware exception-handling sequence the CPU does the following: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to 0. 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address, returning to the program execution state. See section 4, "Exception Handling," for further information on the exception-handling state. 3.8.4 Bus-Released State When so requested, the CPU can grant control of the external bus to an external device. While an external device has the bus right, the CPU is said to be in the bus-released state. The bus right is controlled by two pins: * BREQ: * BACK: Input pin for the Bus Request signal from an external device Output pin for the Bus Request Acknowledge signal from the CPU, indicating that the CPU has released the bus
The procedure by which the CPU enters and leaves the bus-released state is: 1. The CPU receives a Low BREQ signal from an external device. 2. The CPU places the address bus pins (A23 - A0), data bus pins (D15 - D0) and bus control pins (RD, LWR, HWR, and AS) in the high-impedance state, sets the BACK pin to the Low level to indicate that it has released the bus, then halts. 3. The external device that requested the bus (with the BREQ signal) becomes the bus master. It can use the data bus and address bus. The external device is responsible for manipulating the bus control signals (RD, LWR, HWR, and AS). 4. When the external device finishes using the bus, it clears the BREQ signal to the High level. The CPU then reassumes control of the bus and returns to the program execution state. Bus Release Timing: The CPU can release the bus at the following times: 1. The BREQ signal is sampled during every memory access cycle (instruction prefetch or data read/write). If BREQ is Low, the CPU releases the bus right at the end of the cycle. (In word data access to the on-chip register field, or to external memory via an 8-bit data bus, the CPU does not release the bus until it has accessed both the upper and lower data bytes.) 2. During execution of the MULXU and DIVXU instructions, since considerable time may pass without an instruction prefetch or data read/write, BREQ is also sampled at internal machine cycles, and the bus is released if BREQ is Low. 3. The bus can also be released in the sleep mode. The CPU does not recognize interrupts while the bus is released.
60
Timing Charts: Timing charts of the operation by which the bus is released are shown in figure 3-13 for the case of bus release during a two-state read cycle, in figure 3-14 for bus release during a three-state read cycle, and in figure 3-15 for bus release while the CPU is performing an internal operation.
Two-state CPU access cycle
Bus-right release cycle
CPU cycle
T2 o
T1*
T2*
TX*
TX
TX
TX
T1
A 23 -A 0
D15 -D 0
RD, HWR AS, LWR
BREQ
BACK
(1)
(2)
(3)
(4)
(5)
(1) (2) (3) (4) (5)
The BREQ pin is sampled at the start of the T1 state and the Low level is detected. At the end of the two-state access cycle, the BACK pin goes Low and the CPU releases the bus. While the bus is released, the BREQ pin is sampled at each Tx state. A High level is detected at the BREQ pin. The BACK pin is returned to the High level, ending the bus-right release cycle.
* T1 and T2: On-chip memory access states. Tx : Bus-right released state.
Figure 3-13 Bus-Right Release Cycle (During Two-State Access Cycle)
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Three-state CPU access cycle
Bus-right release cycle
CPU cycle
T1 o
T2
TW*
T3
TX*
TX
TX
T1
A 23 -A 0
D15 -D 0
RD, HWR AS, LWR
BREQ
BACK (1) (2) (3) (4)
(1) (2) (3) (4)
The BREQ pin is sampled at the start of the Tw state and the Low level is detected. At the end of the three-state access cycle, the BACK pin goes Low and the CPU releases the bus. The BREQ pin is sampled at the Tx state and a High level is detected. The BACK pin is returned to the High level, ending the bus-right release cycle.
* Tw : Wait state. Tx : Bus-right released state.
Figure 3-14 Bus-Right Release Cycle (During Three-State Access Cycle)
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Internal CPU operation
Bus-right release cycle
CPU cycle
Ti * o
Ti
Ti
Ti
TX*
TX
TX
T1
A 23 -A 0
D15 -D 0
RD, HWR AS, LWR
BREQ
BACK (1) (2) (3) (4)
(1) (2) (3) (4)
The BREQ pin is sampled at the start of a TI state and the Low level is detected. At the end of the internal operation cycle, the BACK pin goes Low and the CPU releases the bus. The BREQ pin is sampled at the TX state and a High level is detected. The BACK pin is returned to the High level, ending the bus-right release cycle.
* TI : Internal CPU operation state. TX : Bus-right released state.
Figure 3-15 Bus-Right Release Cycle (During Internal CPU Operation)
Notes: The BREQ signal must be held Low until BACK goes Low. If BREQ returns to the High level before BACK goes Low, the bus release operation may be executed incorrectly. To leave the bus-released state, the High level at the BREQ pin must be sampled two times. If the BREQ returns to Low before it is sampled two times, the bus released cycle will not end.
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The bus release operation is enabled only when the BRLE bit in the Bus Release Control (BRCR) is set to 1. When this bit is cleared to 0 (its initial value), the BREQ and BACK pins are used for general-purpose input and output, as P32 and P31. 3.8.5 Reset State In the reset state, the CPU and all on-chip supporting modules are initialized and placed in the stopped state. The CPU enters the reset state whenever the RES pin goes Low, unless the CPU is currently in the hardware standby mode. It remains in the reset state until the RES pin goes High. See section 4.2, "Reset," for further information on the reset state. 3.8.6 Power-Down State The power-down state comprises three modes: the sleep mode, the software standby mode, and the hardware standby mode. See section 17, "Power-Down State," for further information.
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Section 4 Exception Handling
4.1 Overview
4.1.1 Types of Exception Handling and Their Priority As indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error, trace, interrupt, or instruction. An instruction initiates exception handling if the instruction is an invalid instruction, a trap instruction, or a DIVXU instruction with zero divisor. Exception handling begins with a hardware exception-handling sequence which prepares for the execution of a user-coded software exception-handling routine. There is a priority order among the different types of exceptions, as shown in table 4-1 (a). If two or more exceptions occur simultaneously, they are handled in their order of priority. An instruction exception cannot occur simultaneously with other types of exceptions. Table 4-1 (a) Exceptions and Their Priority
Exception Priority Type High Reset Address error Trace Interrupt Low Source External Internal Internal External, internal Detection Timing RES Low-to-High transition Instruction fetch or data read/write bus cycle End of instruction execution, if T = 1 in status register End of instruction execution or end of exception-handling sequence Start of ExceptionHandling Sequence Immediately End of instruction execution End of instruction execution End of instruction execution
Table 4-1 (b) Instruction Exceptions
Exception Type Invalid instruction Trap instruction Zero divide Start of Exception-Handling Sequence Attempted execution of instruction with undefined code Started by execution of trap instruction Attempted execution of DIVXU instruction with zero divisor
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4.1.2 Hardware Exception-Handling Sequence The hardware exception-handling sequence varies depending on the type of exception. When exception handling is initiated by a factor other than a reset, the CPU: 1. Saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. Clears the T bit in the status register to 0. 3. Fetches the start address of the exception-handling routine from the exception vector table. 4. Branches to that address. For an interrupt, the CPU also alters the interrupt mask level in bits I2 to I0 of the status register. For a reset, step 1 is omitted. See section 4.2, "Reset," for the full reset sequence. 4.1.3 Exception Factors and Vector Table The factors that initiate exception handling can be classified as shown in figure 4-1. The starting addresses of the exception-handling routines for each factor are contained in an exception vector table located in the low addresses of page 0. The vector addresses are listed in table 4-2. Note that there are different addresses for the minimum and maximum modes.
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* Reset External interrupt NMI IRQ0 IRQ1 to IRQ3 * Interrupt
Internal interrupt
Internal interrupt requested by onchip module
Exception
* Address error
* Trace
Invalid instruction * Instruction Zero divide TRAPA instruction TRAP/VS instruction
Figure 4-1 Types of Factors Causing Exception Handling
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Table 4-2 Exception Vector Table
Vector Address Minimum Mode Maximum Mode *1 H'0000 to H'0001 H'0000 to H'0003 H'0002 to H'0003 H'0004 to H'0007 H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F H'0008 to H'0009 H'0010 to H'0013 H'000A to H'000B H'0014 to H'0017 to to H'000E to H'000F H'001C to H'001F H'0010 to H'0011 H'0020 to H'0023 H'0012 to H'0013 H'0024 to H'0027 H'0014 to H'0015 H'0028 to H'002B H'0016 to H'0017 H'002C to H'002F H'0018 to H'0019 H'0030 to H'0033 to to H'001E to H'001F H'003C to H'003F H'0020 to H'0021 H'0040 to H'0043 to to H'003E to H'003F H'007C to H'007F H'0040 to H'0041 H'0080 to H'0083 H'0042 to H'0043 H'0084 to H'0087 H'0048 to H'0049 H'004A to H'004B H'004C to H'004D H'0050 to H'0051 to H'0078 to H'0079 H'0090 to H'0093 H'0094 to H'0097 H'0098 to H'009B H'00A0 to H'00A3 to H'00F0 to H'00F3
Type of Exception Reset (initialize PC) -- (Reserved for system) Invalid instruction DIVXU instruction (zero divide) TRAP/VS instruction -- (Reserved for system) Address error Trace -- (Reserved for system) Nonmaskable external interrupt (NMI) -- (Reserved for system) TRAPA instruction (16 vectors)
External interrupt Watchdog timer interval interrupt External interrupts
IRQ0
IRQ1 IRQ2 IRQ3
Internal interrupts *2
Notes: * 1 The exception vector table is located at the beginning of page 0 in maximum mode. * 2 For details of the internal interrupt vectors, see table 5-2.
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4.2 Reset
4.2.1 Overview A reset has the highest exception-handling priority. When the RES pin goes Low, all current processing is halted and the H8/510 chip enters the reset state. A reset initializes the internal status of the CPU and the registers of the on-chip supporting modules and I/O ports. When the RES pin returns from Low to High, the H8/510 chip comes out of the reset state and begins executing the hardware reset sequence. 4.2.2 Reset Sequence The Reset signal is detected when the RES pin goes Low. To ensure that the H8/510 is reset, the RES pin should be held Low for at least 20 ms at power-up. To reset the H8/510 during operation, the RES pin should be held Low for at least 6 system clock cycles. See table E.1, "Status of I/O Ports" in appendix E for the status of other pins in the reset state. When the RES pin returns to the High state after being held Low for the necessary time, the hardware reset exception-handling sequence begins, during which: 1. In the status register (SR), the T bit is cleared to disable the trace mode, and the interrupt mask level (bits I2 to I0) is set to 7. A reset disables all interrupts, including NMI. 2. The CPU loads the reset start address from the vector table into the program counter and begins executing the program at that address. The contents of the vector table differs between minimum mode and maximum mode as indicated in figure 4-2. This affects step 3 as follows: Minimum Mode: One word is copied from addresses H'0000 and H'0001 in the vector table to the program counter. Program execution then begins from the address in the program counter (PC).
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Maximum Mode: Two words are read from addresses H'0000 to H'0003 in the vector table. The byte in address H'0000 is ignored. The byte in address H'0001 is copied to the code page register (CP). The contents of addresses H'0002 and H'0003 are copied to the program counter. Program execution starts from the address indicated by the code page register and program counter.
H'0000 H'0001
PC (Upper) PC (Lower)
H'0000 H'0001 H'0002 H'0003
Don't care CP PC (Upper) PC (Lower)
(1) Minimum mode
(2) Maximum mode
Figure 4-2 Reset Vector Figure 4-3 shows the timing of the reset sequence in minimum mode. Figure 4-4 shows the timing of the reset sequence in maximum mode. 4.2.3 Stack Pointer Initialization The hardware reset sequence does not initialize the stack pointer, so this must be done by software. If an interrupt were to be accepted after a reset and before the stack pointer (SP) is Fig. 4-2 initialized, the program counter and status register would not be saved correctly, causing a program crash. This danger can be avoided by coding the reset routine as explained next. When the chip comes out of the reset state all interrupts, including NMI, are disabled, so the instruction at the reset start address is always executed. In the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, this instruction should be an LDC instruction initializing the stack page register (TP), and the next instruction should initialize the stack pointer. Execution of the LDC instruction disables interrupts again, ensuring that the stack pointer initializing instruction is executed.
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Figure 4-3 Reset Sequence (Minimum Mode)
RES A15 to A0 (1) Vector address (3)
D15 to D0 Internal read signal Internal write signal
(2)
Vector
(4)
High
Minimum 6 states
Internal processing cycle
Reset vector
Prefetch first instruction of program
Instruction execution cycle
(1) Instruction prefetch address (2) Operation code
(3) Program start address (4) First instruction of program
Note: This timing chart applies to the minimum mode when the program and vector areas are both in a memory area accessed via a 16-bit bus, and the program starts at an even address. After a reset, the wait-state controller inserts three wait states in every bus cycle.
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Figure 4-4 Reset Sequence (Maximum Mode)
RES Vector address Vector address + 1 Vector address + 2 Vector address + 3
A 23 to A 0
(1)
D7 to D0 Read signal RD
don't care
Vector CP
Vector PC upper
Vector PC lower
(2)
Write signal LWR, HWR
Internal processing cycle
Reset vector
Prefetch first instruction of program
Instruction execution cycle
(1) Program start address (2) First instruction of program
Note: This timing chart applies to maximum mode when the program and vector areas are both accessed via an 8-bit bus. After a reset, the wait-state controller inserts three wait states in each bus cycle.
4.3 Address Error
There are two causes of address errors: * Illegal instruction prefetch * Word data access at odd address An address error initiates the address error exception-handling sequence. This sequence clears the T bit of the status register to 0 to disable the trace mode, but does not affect the interrupt mask level in bits I2 to I0. 4.3.1 Illegal Instruction Prefetch An attempt to prefetch an instruction from the register field and external I/O area in memory addresses H'FE80 to H'FFFF causes an address error regardless of the MCU operating mode. Handling of this address error begins when the prefetch cycle that caused the error has been completed and execution of the current instruction has also been completed. The program counter value pushed on the stack is the address of the instruction immediately following the last instruction executed. Program code should not be located in addresses H'FE7D to H'FE7F. If the CPU executes an instruction in these addresses, it will attempt to prefetch the next instruction from the register field, causing an address error. 4.3.2 Word Data Access at Odd Address If an attempt is made to access word data starting at an odd address, an address error occurs regardless of the MCU operating mode. The program counter value pushed on the stack in the handling of this error is the address of the next instruction (or next but one) after the instruction that attempted the illegal word access.
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4.4 Trace
When the T bit of the status register is set to 1, the CPU operates in trace mode. A trace exception occurs at the completion of each instruction. The trace mode can be used to execute a program for debugging by a debugger. In the trace exception sequence the T bit of the status register is cleared to 0 to disable the trace mode while the trace routine is executing. The interrupt mask level in bits I2 to I0 is not changed. Interrupts are accepted as usual during the trace routine. In the status-register data saved on the stack, the T bit is set to 1. When the trace routine returns with the RTE instruction, the status register is popped from the stack and the trace mode resumes. If an address error occurs during execution of the first instruction after the return from the trace routine, since the address error has higher priority, the address error exception-handling sequence is initiated, clearing the T bit in the status register to 0 and making it impossible to trace this instruction.
4.5 Interrupts
Interrupts can be requested from five external sources (NMI, IRQ0, IRQ1, IRQ2, IRQ3) and seven on-chip supporting modules: the 16-bit free-running timers (FRT1 and FRT2), the 8-bit timer, the serial communication interfaces (SCI1 and SCI2), the A/D converter, and the watchdog timer (WDT). The on-chip interrupt sources can request a total of eighteen different types of interrupts, each having its own interrupt vector. Figure 4-5 lists the interrupt sources and the number of different interrupts from each source. Each interrupt source has a priority. NMI interrupts have the highest priority, and are normally accepted unconditionally. The priorities of the other interrupt sources are set in control registers (IPRA to IPRD) in the register field at the high end of page 0 and can be changed by software. Priority levels range from 7 (high) to 0 (low), with NMI considered to be on level 8. Priorities can be assigned to IRQ0 individually and to IRQ1 to IRQ3 as a group. For the other interrupt sources, priorities are assined to the on-chip supporting module in which the interrupt originates. The on-chip interrupt controller decides whether an interrupt can be accepted by comparing its priority with the interrupt mask level, and determines the order in which to accept competing interrupt requests. Interrupts that are not accepted immediately remain pending until they can be accepted later. When it accepts an interrupt, the interrupt controller also decides whether to interrupt the CPU or start the on-chip data transfer controller (DTC). This decision is controlled by bits set in four data transfer enable registers (DTEA to DTED) in the register field. The DTC is started if the corresponding DTE bit is set to 1; otherwise a CPU interrupt is generated. DTC interrupts provide
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an efficient way to send and receive blocks of data via the serial communication interface, or to transfer data between memory and I/O without detailed CPU programming. The CPU halts during DTC operation. DTC interrupts are described in section 6, "Data Transfer Controller." The hardware exception-handling sequence for a CPU interrupt clears the T bit in the status register to 0 and sets the interrupt mask level in bits I2 to I0 to the level of the interrupt it has accepted. This prevents the interrupt-handling routine from being interrupted except by a higherlevel interrupt. The previous interrupt mask level is restored on the return from the interrupthandling routine. For further information on interrupts, see section 5, "Interrupt Controller."
External interrupts
NMI (1) IRQ0 (1) IRQ1 to IRQ3 (3)
Interrupt sources 16-Bit FRT1 (4) 16-Bit FRT2 (4) 8-Bit timer (3) Internal interrupts SCI1 (3) SCI2 (3) A/D converter (1) WDT* NMI: IRQ: FRT: SCI: WDT: NonMaskable Interrupt Interrupt Request Free-Running Timer Serial Communication Interface WatchDog Timer
* Interrupts from the watchdog timer are handled as IRQ0.
Figure 4-5 Interrupt Sources (and Number of Interrupt Types)
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4.6 Invalid Instruction
An invalid instruction exception occurs if an attempt is made to execute an instruction with an undefined operation code or illegal addressing mode specification. The program counter value pushed on the stack is the value of the program counter when the invalid instruction code was detected. In the invalid instruction exception-handling sequence the T bit of the status register is cleared to 0, but the interrupt mask level (I2 to I0) is not affected.
4.7 Trap Instructions and Zero Divide
A trap exception occurs when the TRAPA or TRAP/VS instruction is executed. A zero divide exception occurs if an attempt is made to execute a DIVXU instruction with a zero divisor. In the exception-handling sequences for these exceptions the T bit of the status register is cleared to 0, but the interrupt mask level (I2 to I0) is not affected. If a normal interrupt is requested while a trap or zero-divide instruction is being executed, after the trap or zero-divide exception-handling sequence, the normal interrupt exception-handling sequence is carried out. TRAPA Instruction: The TRAPA instruction always causes a trap exception. The TRAPA instruction includes a vector number from 0 to 15, allowing the user to provide up to sixteen different trap-handling routines. TRAP/VS Instruction: When the TRAP/VS instruction is executed, a trap exception occurs if the overflow (V) bit in the condition code register is set to 1. If the V bit is cleared to 0, no exception occurs and the next instruction is executed. DIVXU Instruction with Zero Divisor: An exception occurs if an attempt is made to divide by zero in a DIVXU instruction.
4.8 Cases in Which Exception Handling is Deferred
In the cases described next, the address error exception, trace exception, external interrupt (NMI, IRQ0 to IRQ3) requests, and internal interrupt requests (18 types) are not accepted immediately but are deferred until after the next instruction has been executed. 4.8.1 Instructions that Disable Interrupts Interrupts are disabled immediately after the execution of five instructions: XORC, ORC, ANDC, LDC, and RTE. Suppose that an internal interrupt is requested and the interrupt controller, after checking the interrupt priority and interrupt mask level, notifies the CPU of the interrupt, but the CPU is
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currently executing one of the five instructions listed above. After executing this instruction the CPU always proceeds to the next instruction. (And if the next instruction is one of these five, the CPU also proceeds to the next instruction after that.) The exception-handling sequence starts after the next instruction that is not one of these five has been executed. The following is an example: Note: If the LDC instruction modifies the interrupt mask bits in the status register, the new interrupt mask level does not take effect until the third state after the LDC instruction has been executed. If an LDC instruction in a program stored in the memory area accessed in two states via a 16-bit bus modifies the interrupt mask level in order to enable an interrupt, but the next instruction is a two-state instruction (such as NOP), the interrupt will not be accepted after this two-state instruction. It will not be accepted until another instruction has been executed. The same applies to ANDC, ORC, and XORC. (Example)
. . . . . .
Program flow
LDC.B #H'00,TP
Interrupt controller notifies CPU of interrupt request CPU executes the next instruction after LDC before starting exception handling
MOV.W #H'FE80,SP
MOV.B #H'00,@WCR
. . .
To exception-handling sequence
4.8.2 Disabling of Exceptions Immediately after a Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the program counter and status register will not be saved correctly, leading to a program crash. To prevent this, when the chip comes out of the reset state all interrupts, including the NMI, are disabled, so the first instruction of the reset routine is always executed. As noted earlier, in the minimum mode, this instruction should initialize the stack pointer (SP). In the maximum mode, the first instruction should be an LDC instruction that initializes the stack page register (TP); the next instruction should initialize the stack pointer.
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4.8.3 Disabling of Interrupts after a Data Transfer Cycle If an interrupt starts the data transfer controller and another interrupt is requested during the data transfer cycle, when the data transfer cycle ends, the CPU always executes the next instruction before handling the second interrupt. Even if a nonmaskable interrupt (NMI) occurs during a data transfer cycle, it is not accepted until the next instruction has been executed. An example of this is shown below. (Example)
. . . . . Program flow
ADD.W R2,R0
DTC interrupt request Data transfer cycle NMI interrupt request
MOV.W R0,@H'FE00
MOV.W @H'FF02,R0
. . .
After data transfer cycle, CPU executes next instruction before branching to exception handling To NMI exception-handling sequence
4.9 Stack Status after Completion of Exception Handling
The status of the stack after an exception-handling sequence is described below. Table 4-3 shows the stack after completion of the exception-handling sequence for various types of exceptions in the minimum and maximum modes.
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Table 4-3 Stack after Exception Handling Sequence
Exception Cause Minimum Mode Maximum Mode
Trace
SP SR (upper byte) SR (lower byte) Next instruction address (upper byte) TP:SP SR (upper byte) SR (lower byte) Don't care Next instruction page (8 bits) Next instruction address (upper byte)
Interrupt Trap Zero divide (DIVXU)
Next instruction address (lower byte)
Next instruction address (lower byte)
Note: The RTE instruction returns to the next instruction after the instruction being executed when the exception occurred. Exception Cause Minimum Mode Maximum Mode
Invalid instruction
SP
SR (upper byte) SR (lower byte) PC when error occurred (upper byte) PC when error occurred (lower byte)
TP:SP
SR (upper byte) SR (lower byte) Don't care CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is not necessarily the address of the first byte of the invalid instruction.
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Table 4-3 Stack after Exception Handling Sequence (cont)
Exception Cause Minimum Mode Maximum Mode
Address error
SP
SR (upper byte) SR (lower byte) PC when error occurred (upper byte) PC when error occurred (lower byte)
TP:SP
SR (upper byte) SR (lower byte) Don't care CP when error occurred (8 bits) PC when error occurred (upper byte) PC when error occurred (lower byte)
Note: The program counter value pushed on the stack is the address of the next instruction after the last instruction successfully executed.
4.9.1 PC Value Pushed on Stack for Trace, Interrupts, Trap Instructions, and Zero Divide Exceptions The program counter value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt was accepted. The RTE instruction accordingly returns to the next instruction after the instruction executed before the exception-handling sequence. 4.9.2 PC Value Pushed on Stack for Address Error and Invalid Instruction Exceptions The program counter value pushed on the stack for an address error or invalid instruction exception differs depending on the conditions when the exception occurred.
4.10 Notes on Use of the Stack
If the stack pointer is set to an odd address, an address error will occur when the stack is accessed during interrupt handling or for a subroutine call. The stack pointer should always point to an even address. To keep the stack pointer pointing to an even address, a program should use word data size when saving or restoring registers to and from the stack. In the @-SP or @SP+ addressing mode, the CPU performs word access even if the instruction specifies byte size. (This is not true in the @-Rn and @Rn+ addressing modes when Rn is a register from R6 to R0.)
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Section 5 Interrupt Controller
5.1 Overview
The interrupt controller decides which interrupts to accept, and how to deal with multiple interrupts. It also decides whether an interrupt should be served by the CPU or by the data transfer controller (DTC). This section explains the features of the interrupt controller, describes its internal structure and control registers, and details the handling of interrupts. For detailed information on the data transfer controller, see section 6, "Data Transfer Controller."
5.1.1 Features
Three main features of the interrupt controller are: * Interrupt priorities are user-programmable. User programs can set priority levels from 7 (high) to 0 (low) in four interrupt priority registers (IPRs) for IRQ0, IRQ1 to IRQ3, and each of the on-chip supporting modules--for every interrupt, that is, except the nonmaskable interrupt (NMI). NMI has the highest priority level (8) and is normally always accepted. An interrupt with priority level 0 is always masked. * Multiple interrupts on the same level are served in a default priority order. Lower-priority interrupts remain pending until higher-priority interrupts have been handled. * For most interrupts, software can select whether to have the interrupt served by the CPU or the on-chip data transfer controller (DTC). User programs can make this selection by setting and clearing bits in four data transfer enable (DTE) registers. The data transfer controller can be started by any interrupts except NMI, the error interrupt (ERI) from the on-chip serial communication interface, and the overflow interrupts (FOVI and OVI) from the on-chip timers.
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5.1.2 Block Diagram Figure 5-1 shows the block configuration of the interrupt controller.
Interrupt controller NMI IRQ 0 IRQ 1 to IRQ 3 IPRA to IPRD FRT1 Interrupt request signals from modules FRT2 8-Bit timer SCI1 SCI2 A/D converter Priority decision NMI request
Comparator
Interrupt request
DTEA to DTED
DTC request
I2 FRT: 16-Bit Free Running Timer SCI: Serial Communication Interface SR: Status Register IPR: Interrupt Priority Register DTE: Data Transfer Enable Register
I1
I0
SR (CPU)
Figure 5-1 Interrupt Controller Block Diagram
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5.1.3 Register Configuration The four interrupt priority registers (IPRA to IPRD) and four data transfer enable registers (DTEA to DTED) are 8-bit registers located in the register field in page 0 of the address space. Table 5-1 lists their attributes. Table 5-1 Interrupt Controller Registers
Name Interrupt priority register Data transfer enable register Abbreviation IPRA IPRB IPRC IPRD DTEA DTEB DTEC DTED Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Address H'FF00 H'FF01 H'FF02 H'FF03 H'FF08 H'FF09 H'FF0A H'FF0B Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00
A B C D A B C D
5.2 Interrupt Types
There are 23 distinct types of interrupts: 5 external interrupts originating off-chip and 18 internal interrupts originating in the on-chip supporting modules. 5.2.1 External Interrupts The five external interrupts are NMI and IRQ0 to IRQ3. NMI (NonMaskable Interrupt): This interrupt has the highest priority level (8) and cannot be masked. The input at the NMI pin is edge-sensed. A user program can select whether to have the interrupt occur on the rising edge or falling edge of the NMI input by setting or clearing the nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR). In the NMI exception-handling sequence, the T (Trace) bit in the CPU status register (SR) is cleared to 0, and the interrupt mask level in I2 to I0 is set to 7, masking all other interrupts. The interrupt controller holds the NMI request until the NMI exception-handling sequence begins, then clears the NMI request, so if another interrupt is requested at the NMI pin during the NMI exception-handling sequence, the NMI exception-handling sequence will be carried out again.
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NMI Control Register (NMICR)--H'FF1C
Bit 7 -- Initial value Read/Write 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 -- 1 R 2 -- 1 R 1 -- 1 R 0 NMIEG 0 R/W
The NMI control register (NMICR) is an 8-bit register that selects the edge of the NMI input signal which triggers a nonmaskable interrupt. The NMICR is initialzed to H'FE (falling edge) at a reset and in the hard ware standby mode. It is not initialized in the software standby mode. Bit 7 to 1--Reserved: These bits cannot be modified and are always read as 1. Bit 0--Nonmaskable Interrupt Edge (NMIEG): This bit selects the valid edge of the NMI input signal.
Bit 0 NMIEG Description 0 A nonmaskable interrupt is generated on the falling edge of the NMI input signal. 1 A nonmaskable interrupt is generated on the rising edge of the NMI input signal.
(Initial state)
IRQ Control Register (IRQCR)--H'FFFD
Bit 7 -- Initial value Read/Write 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
The IRQ control register (IRQCR) enables or disables external interrupts on an individual basis. When an interrupt is enabled, the corresponding pin in port 8 is used for interrupt request input. The IRQ control register is initialized to H'F0 at a reset and in the hardware standby mode, disabling all four IRQ interrupt requests. It is not initialized in the software standby mode. Bit 7 to 4--Reserved: These bits cannot be modified and are always read as 1.
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Bit 3--Interrupt Request 3 Enable (IRQ3E): This bit determines the function of pin P83.
Bit 3 IRQ3E 0 1
Description P83 is used as an input/output pin. P83 is used for IRQ3 input, regardless of the setting of P83DDR. (The CPU can also read the logic level of the P83 pin.)
(Initial state)
Bit 2--Interrupt Request 2 Enable (IRQ2E): This bit determines the function of pin P82.
Bit 2 IRQ2E 0 1
Description P82 is used as an input/output pin. P82 is used for IRQ2 input, regardless of the setting of P82DDR. (The CPU can also read the logic level of the P82 pin.)
(Initial state)
Bit 1--Interrupt Request 1 Enable (IRQ1E): This bit determines the function of pin P81.
Bit 1 IRQ1E 0 1
Description P81 is used as an input/output pin. P81 is used for IRQ1 input, regardless of the setting of P81DDR. (The CPU can also read the logic level of the P81 pin.)
(Initial state)
Bit 0--Interrupt Request 0 Enable (IRQ0E): This bit determines the function of pin P80.
Bit 0 IRQ0E 0 1
Description P80 is used as an input/output pin. P80 is used for IRQ0 input, regardless of the setting of P80DDR. (The CPU can also read the logic level of the P80 pin.)
(Initial state)
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IRQ0 (Interrupt Request 0): An IRQ0 interrupt can be requested by a low input to the IRQ0 pin and/or a watchdog timer overflow. A low IRQ0 input requests an IRQ0 interrupt if the interrupt request enable 0 bit (IRQ0E) in the IRQ control register is set to 1. IRQ0 must be held low until the CPU accepts the interrupt. Otherwise the request will be ignored. A watchdog timer overflow requests an IRQ0 interrupt if the TME bit is set to 1 and the WT/IT bit is cleared to 0 in the watchdog timer's control/status register. Different interrupt vectors are provided for low IRQ0 input and watchdog timer overflow. The IRQ0 interrupt can be assigned any priority level from 7 to 0 by setting the corresponding value in the upper four bits of IPRA. If bit 4 of data transfer enable register A (DTEA) is set to 1, an IRQ0 interrupt starts the data transfer controller. Otherwise the interrupt is served by the CPU. In the CPU interrupt-handling sequence for IRQ0, the T bit of the status register is cleared to 0, and the interrupt mask level is set to the value in the upper four bits of IPRA. IRQn (Interrupt Request n: n=1 to 3): An IRQn interrupt is requested by a high-to-low transition at the IRQn pin. The IRQn interrupt is enabled only when the interrupt request enable n bit (IRQnE) in the IRQ control register is set to 1. The interrupt controller holds IRQ1 to IRQ3 requests until the corresponding exception-handling sequence begins, then clears the request. Contention among IRQ1 to IRQ3 is resolved when the CPU accepts the interrupt by taking the interrupt with the highest priority first and holding lowerpriority interrupts pending. The IRQn interrupts can be collectively assigned any priority level from 7 (high) to 0 (low) by setting the corresponding value in the lower four bits of IPRA. Whether they are served by the data transfer controller or CPU can be selected individually by bits 2 to 0 of data transfer enable register A (DTEA). In the CPU interrupt-handling sequence for IRQn, the T bit of the CPU status register is cleared to 0, and the interrupt mask level is set to the value in the lower four bits of IPRA.
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5.2.2 Internal Interrupts Eighteen types of internal interrupts can be requested by the on-chip supporting modules. Each interrupt is separately vectored in the exception vector table, so it is not necessary for the usercoded interrupt handler routine to determine which type of interrupt has occurred. Each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the control register of the on-chip supporting module. An interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by setting interrupt priority registers B to D. Within each module, different interrupts have a fixed priority order. For most of these interrupts, values set in data transfer enable registers B to D can select whether to have the interrupt served by the CPU or the data transfer controller. In the CPU interrupt-handling sequence, the T bit of the CPU status register is cleared to 0, and the interrupt mask level in bits I2 to I0 is set to the value in the interrupt priority register. 5.2.3 Interrupt Vector Table Table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains how their priority is determined. For the on-chip supporting modules, the priority level set in the interrupt priority register applies to the module as a whole: all interrupts from that module have the same priority level. A separate priority order is established among interrupts from the same module. If the same priority level is assigned to two or more modules and two interrupts are requested simultaneously from these modules, they are served in the priority order indicated in the rightmost column in table 5-2. A reset clears the interrupt priority registers so that all interrupts except NMI start with priority level 0, meaning that they are unconditionally masked.
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Table 5-2 Interrupts, Vectors, and Priorities
Assignable Priority Levels (Initial IPR Interrupt Level) Bits NMI 8 -- (8) IRQ0 7 to 0 IPRA WDT interval timer (0) bits 6 to 4 IRQ1 7 to 0 IPRA IRQ2 (0) bits 2 to 0 IRQ3 16-bit ICI 7 to 0 IPRB FRT1 OCIA (0) bits 6 to 4 OCIB FOVI 16-bit ICI 7 to 0 IPRB FRT2 OCIA (0) bits 2 to 0 OCIB FOVI 8-bit CMIA 7 to 0 IPRC timer CMIB (0) bits 6 to 4 OVI SCI1 ERI 7 to 0 IPRC RXI (0) bits 2 to 0 TXI SCI2 ERI 7 to 0 IPRD RXI (0) bits 6 to 4 TXI A/D ADI 7 to 0 IPRD converter (0) bits 2 to 0 Vector Table Entry Address Minimum Mode H'16 - H'17 H'40 - H'41 H'42 - H'43 H'48 - H'49 H'4A - H'4B H'4C - H'4D H'50 - H'51 H'52 - H'53 H'54 - H'55 H'56 - H'57 H'58 - H'59 H'5A - H'5B H'5C - H'5D H'5E - H'5F H'60 - H'61 H'62 - H'63 H'64 - H'65 H'68 - H'69 H'6A - H'6B H'6C - H'6D H'70 - H'71 H'72 - H'73 H'74 - H'75 H'78 - H'79 Maximum Mode H'2C - H'2F H'80 - H'83 H'84 - H'87 H'90 - H'93 H'94 - H'97 H'98 - H'9B H'A0 - H'A3 H'A4 - H'A7 H'A8 - H'AB H'AC - H'AF H'B0 - H'B3 H'B4 - H'B7 H'B8 - H'BB H'BC - H'BF H'C0 - H'C3 H'C4 - H'C7 H'C8 - H'CB H'D0 - H'D3 H'D4 - H'D7 H'D8 - H'DB H'E0 - H'E3 H'E4 - H'E7 H'E8 - H'EB H'F0 - H'F3 Low Priority among Interrupts on Same Level* High
Priority within Module -- -- 2 1 0 3 2 1 0 3 2 1 0 2 1 0 2 1 0 2 1 0 --
* If two or more interrupts are requested simultaneously, they are handled in order of priority level, as set in registers IPRA to IPRD. If they have the same priority level because they are requested from the same on-chip supporting module, they are handled in a fixed priority order within the module. If they are requested from different modules to which the same priority level is assigned, they are handled in the order indicated in the right-hand column.
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5.3 Register Descriptions
5.3.1 Interrupt Priority Registers A to D (IPRA to IPRD) IRQ0, IRQ1 to IRQ3, and the on-chip supporting modules are each assigned three bits in one of the four interrupt priority registers (IPRA to IPRD). These bits specify a priority level from 7 (high) to 0 (low) for interrupts from the corresponding source. The drawing below shows the configuration of the interrupt priority registers. Table 5-3 lists their assignments to interrupt sources.
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4 3 -- 0 R 0 R/W 0 R/W 0 R/W 2 1 0
Note: Bits 7 and 3 are reserved. They cannot be modified and are always read as 0.
Table 5-3 Assignment of Interrupt Priority Registers
Interrupt Request Source Bits 6 to 4 Bits 2 to 0 IRQ0 IRQ1 - IRQ3 16-bit FRT1 16-bit FRT2 8-bit timer SCI1 SCI2 A/D converter
Register IPRA IPRB IPRC IPRD
Address H'FF00 H'FF01 H'FF02 H'FF03
As table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt sources. A user program can assign desired levels to these interrupt sources by writing 000 in bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or 111 to set priority level 7. A reset clears registers IPRA to IPRD to H'00, so all interrupts except NMI are initially masked.
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When the interrupt controller receives one or more interrupt requests, it selects the request with the highest priority and compares its priority level with the interrupt mask level set in bits I2 to I0 in the CPU status register. If the priority level is higher than the mask level, the interrupt controller passes the interrupt request to the CPU (or starts the data transfer controller). If the priority level is lower than the mask level, the interrupt controller leaves the interrupt request pending until the interrupt mask is altered to a lower level or the interrupt priority is raised. Similarly, if it receives two interrupt requests with the same priority level, the interrupt controller determines their priority as explained in table 5-2 and leaves the interrupt request with the lower priority pending. 5.3.2 Timing of Priority Setting The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies an instruction priority register, the new priority does not take effect until after the third state after the instruction has been executed.
5.4 Interrupt Handling Sequence
5.4.1 Interrupt Handling Flow The interrupt-handling sequence follows the flowchart in figure 5-2. Note that address error, trace exception, and NMI requests bypass the interrupt controller's priority decision logic and are routed directly to the CPU. 1. Interrupt requests are generated by one or more on-chip supporting modules or external interrupt sources. 2. The interrupt controller checks the interrupt priorities set in the IPRA to IPRD and selects the interrupt with the highest priority. Interrupts with lower priorities remain pending. Among interrupts with the same priority level, the interrupt controller determines priority as explained in table 5-2. 3. The interrupt controller compares the priority level of the selected interrupt request with the mask level in the CPU status register (bits I2 to I0). If the priority level is equal to or less than the mask level, the interrupt request remains pending. If the priority level is higher than the mask level, the interrupt controller accepts the interrupt request and proceeds to the next step. 4. The interrupt controller checks the corresponding bit (if any) in the data transfer enable registers (DTEA to DTED). If this bit is set to 1, the data transfer controller is started. Otherwise, the CPU interrupt exception-handling sequence is started. When the data transfer controller is started, the interrupt request is cleared (except for interrupt requests from the serial communication interface, which are cleared by writing to the TDR or reading the RDR).
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If the data transfer enable bit is cleared to 0 (or is nonexistent), the sequence proceeds as follows. For the case in which the data transfer controller is started, see section 6, "Data Transfer Controller." 5. After the CPU has finished executing the current instruction, the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3 (a) or (b). The program counter value saved on the stack is the address of the next instruction to be executed. 6. The T (Trace) bit of the status register is cleared to 0, and the priority level of the interrupt is copied to bits I2 to I0, thus masking further interrupts unless they have a higher priority level. When an NMI is accepted, the interrupt mask level in bits I2 to I0 is set to 7. 7. The interrupt controller generates the vector address of the interrupt, and the entry at this address in the exception vector table is read to obtain the starting address of the user-coded interrupt handling routine. In step 7, the same difference between the minimum and maximum modes exists as in the reset handling sequence. In the minimum mode, one word is copied from the vector table to the program counter, then the interrupt-handling routine starts executing from the address indicated in the program counter. In the maximum mode, two words are read. The lower byte of the first word is copied to the code page register. The second word is copied to the program counter. The interrupt-handling routine starts executing from the address indicated in the code page register and program counter.
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Program execution state N Interrupt requested? Address error? Y N N Trace? NMI? Y Y N N Level-7 interrupt? Y Level-6 interrupt? Y Mask level in SR 6? Y Mask level in SR 5? Y Level-1 interrupt? Y N N Mask level in SR = 0? Y N N N Y
Interrupt remains pending Data transfer enabled? N Exception-handling sequence Save PC Y Start DTC Read DTC vector Read transfer mode Read source address Read data Maximum mode? N Y Save CP Source address increment mode? N Save SR Write source address Read destination address Write data N Trace? Y Address error? Y N Update mask level Destination address increment mode? N Y Y
Increment source address (+1 or +2)
Clear T bit
Increment destination address (+1 or +2) Write destination address
Read DTCR Vectoring DTCR-1 DTCR Write DTCR To user-coded exception-handling routine Y DTCR = 0? N
Figure 5-2 Interrupt Handling Flowchart
Fig. 5-2
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5.4.2 Stack Status after Interrupt Handling Sequence Figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence.
Address
Address
2m - 4 2m - 3 2m - 2 2m - 1 2m Stack area SP
2m - 4 2m - 3 2m - 2 2m - 1 2m
Upper 8 bits of SR Lower 8 bits of SR Upper 8 bits of PC Lower 8 bits of PC
SP
(Before) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address (e.g., 2m).
(After)
Figure 5-3 (a) Stack before and after Interrupt Exception-Handling (Minimum Mode)
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Address 2m - 6 2m - 5 2m - 4 2m - 3 2m - 2 2m - 1 2m Stack area SP
Address 2m - 6 2m - 5 2m - 4 2m - 3 2m - 2 2m - 1 2m Upper 8 bits of SR Lower 8 bits of SR Don't care CP Upper 8 bits of PC Lower 8 bits of PC SP
(Before) Save to stack Notes: 1. PC: The address of the next instruction to be executed is saved. 2. Register saving and restoring must start at an even address (e.g., 2m).
(After)
Figure 5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode) 5.4.3 Timing of Interrupt Exception-Handling Sequence Figure 5-4 shows the timing of the exception-handling sequence for an interrupt in minimum mode when the user-coded interrupt handling routine starts at an even address. Figure 5-5 shows the timing of the exception-hadling sequence for an interrupt in maximum mode when the user-coded interrupt handling routine starts at an odd address.
5.5 Interrupts During Operation of the Data Transfer Controller
If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the data transfer cycle has been completed and the next instruction has been executed. This is true even if the interrupt is an NMI. An example is shown below. (Example) Program flow
DTC interrupt request
ADD.W MOV.W MOV.W
R2, R0 R0, @H'FF00 @H' FF02,R0
Data transfer cycle request
NMI interrupt
After data transfer cycle, CPU executes next instruction before starting exception handling
To NMI exception handling sequence
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o
A15 -A 0
(1)
(1)
(1)
SP -2
SP - 4
Vector address
Figure 5-4 Interrupt Sequence (Minimum Mode)
(3)
NMI, IRQ 0 to IRQ 3
D15 -D0
(2)
(2)
(2)
PC
SR
Vector
(4)
RD HWR, LWR
Internal Priority level decision and wait processing cycle for end of current instruction Interrupt accepted (1) Instruction prefetch address (2) Instruction code
Stack access
Interrupt vector
Start instruction Prefetch first execution instruction of interrupthandling routine (4) First instruction of interrupt-handling routine
(3) Starting address of interrupt-handling routine
Note: This timing chart applies to the minimum mode when the program and vector areas are both in a memory area accessed in two states via a 16-bit bus, and the interrupt-handling routine starts at an even address.
o
A23 to A 0
(1)
(1)
(1)
SP-2
SP-4
SP-6
Vector address
Vector address
(3)
Figure 5-5 Interrupt Sequence (Maximum Mode)
NMI, IRQ 0 to IRQ 3
Vector CP Vector PC
D15 to D0
(2)
(2)
(2)
PC
CP
SR
(4)
RD
HWR, LWR
Priority level decision and wait Internal for end of current processing instruction cycle Interrput accepted (1) Instruction prefetch address (2) Instruction code
Stack access
Interrupt vector
Prefetch first instruction of interrupt-handling routine
Start instruction execution
(3) Starting address of interrupt-handling routine (4) First instruction of interrupt-handling routine
Note: This timing chart applies to the maximum mode when the interrupt-handling routine starts at an odd address and the program, vector, and stack areas are all in a memory area accessed in two states via a 16-bit bus.
5.6 Interrupt Response Time
Table 5-4 indicates the number of states that may elapse between the generation of an interrupt request and the execution of the first instruction of the interrupt-handling routine, assuming that the interrupt is not masked and not preempted by a higher-priority interrupt. Fastest interrupt service can be obtained by placing the program and stack in a memory area that can be accessed in two states via a 16-bit bus. Table 5-4 Number of States before Interrupt Service
Number of States Minimum Mode Maximum Mode 2 states 2 states x (x = 38 for LDM instruction specifying all registers) y (y = 74 + 16m for LDM instruction specifying all registers) 16 21 28 + 6m 41 + 10m
Reason for Wait Interrupt priority decision and comparison with mask level in status register 2 Maximum Instruction is in 16-bit bus, number of 2-state access memory area states to completion of Instruction is in 8-bit bus, current 3-state access memory area instruction 3 Saving of PC Stack is in 16-bit bus, and SR or PC, 2-state access memory area CP, and SR Stack is in 8-bit bus, and instruction 3-state access memory area prefetch Total Stack is in 16- Instruction is in bit bus, 2-state 16-bit bus, 2-state access access memory area memory area Instruction is in 8-bit bus, 3-state access memory area Stack is in 8- Instruction is in bit bus, 3-state 16-bit bus, 2-state access access memory area memory area Instruction is in 8-bit bus, 3-state access memory area
No. 1
18 + x (56) 18 + y (92 + 16m) 30 + 6m + x (68 + 6m) 30 + 6m + y (104 + 22m)
23 + x (61) 23 + y (97 + 16m) 43 + 10m + x (81 + 10m) 43 + 10m + y (117 + 26m)
Note: m = Number of wait states inserted in memory access. Figure in parentheses are for the LDM instruction specifying all registers.
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Section 6 Data Transfer Controller
6.1 Overview
The H8/510 chip includes a data transfer controller (DTC) that can be started by designated interrupts to transfer data from a source address to a destination address located in page 0. These addresses include in particular the registers of the on-chip supporting modules and I/O ports. Typical uses of the DTC are to change the setting of a control register of an on-chip supporting module in response to an interrupt from that module, or to transfer data from memory to an I/O port or serial communication interface. Once set up, the transfer is interrupt-driven, so it proceeds independently of program execution, although program execution temporarily stops while each byte or word is being transferred. 6.1.1 Features The main features of the DTC are listed below. * The source address and destination address can be set anywhere in the 64-kbyte address space of page 0. * The DTC can be programmed to transfer one byte or one word of data per interrupt. * The DTC can be programmed to increment the source address and/or destination address after each byte or word is transferred. * After transferring a designated number of bytes or words, the DTC generates a CPU interrupt with the vector of the interrupt source that started the DTC. * This designated data transfer count can be set from 1 to 65,536 bytes or words. 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the DTC. The four DTC control registers (DTMR, DTSR, DTDR, and DTCR) are invisible to the CPU, but corresponding information is kept in a register information table in memory. A separate table is maintained for each DTC interrupt type. When an interrupt requests DTC service, the DTC loads its control registers from the table in memory, transfers the byte or word of data, and writes any altered register information back to memory.
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Internal data bus Bus interface DTC request External RAM Interrupt controller IRQ 0 IRQ 1 DTEA DTEB DTEC DTED DTMR DTSR DTDR DTCR DTC Register infomation table 0 Register infomation table 1
DTMR: DT Mode Register DTSR: DT Source Address Register DTDR: DT Destination Address Register DTCR: DT Count Register DTEA to DTED: DT Enable Register A to D
Figure 6-1 Block Diagram of Data Transfer Controller 6.1.3 Register Configuration The four DTC control registers are listed in table 6-1. These registers are not located in the address space and cannot be written or read by the CPU. To set information in these registers, a program must write the information in a table in memory from which it will be loaded by the DTC. Table 6-1 Internal Control Registers of the DTC
Name Data transfer mode register Data transfer source address register Data transfer destination address register Data transfer count register Abbreviation DTMR DTSR DTDR DTCR Read/Write Disabled Disabled Disabled Disabled
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Starting of the DTC is controlled by the four data transfer enable registers, which are located in high addresses in page 0. Table 6-2 lists these registers. Table 6-2 Data Transfer Enable Registers
Name Data transfer enable register Abbreviation DTEA DTEB DTEC DTED Read/Write R/W R/W R/W R/W Address H'FF08 H'FF09 H'FF0A H'FF0B Initial Value H'00 H'00 H'00 H'00
A B C D
6.2 Register Descriptions
6.2.1 Data Transfer Mode Register (DTMR)
Bit 15 Sz Read/Write -- 14 SI -- 13 DI -- 12 -- -- 11 -- -- 10 -- -- 9 -- -- 8 -- -- 7 -- -- 6 -- -- 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- --
The data transfer mode register is a 16-bit register, the first three bits of which designate the data size and specify whether to increment the source and destination addresses. Bit 15--Sz (Size): This bit designates the size of the data transferred.
Bit 15 Sz Description 0 Byte transfer 1 Word transfer* (two bytes at a time) * For word transfer, the source and destination addresses must be even addresses.
Bit 14--SI (Source Increment): This bit specifies whether to increment to source address.
Bit 14 SI 0 1
Description Source address is not incremented. 1) If Sz = 0: Source address is incremented by +1 after each data transfer. 2) If Sz = 1: Source address is incremented by +2 after each data transfer.
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Bit 13--DI (Destination Increment): This bit specifies whether to increment to destination address.
Bit 13 DI 0 1
Description Destination address is not incremented. 1) If Sz = 0: Destination address is incremented by +1 after each data transfer. 2) If Sz = 1: Destination address is incremented by +2 after each data transfer.
Bits 12 to 0--Reserved Bits: These bits are reserved. 6.2.2 Data Transfer Source Address Register (DTSR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
The data transfer source register is a 16-bit register that designates the data transfer source address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.3 Data Transfer Destination Register (DTDR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
The data transfer destination register is a 16-bit register that designates the data transfer destination address. For word transfer this must be an even address. In the maximum mode, this address is implicitly located in page 0. 6.2.4 Data Transfer Count Register (DTCR)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read/Write --
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
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The data transfer count register is a 16-bit register that counts the number of bytes or words of data remaining to be transferred. The initial count can be set from 1 to 65,536. A register value of 0 designates an initial count of 65,536. The data transfer count register is decremented automatically after each byte or word is transferred. When its value reaches 0, indicating that the designated number of bytes or words have been transferred, a CPU interrupt is generated with the vector of the interrupt that requested the data transfer. 6.2.5 Data Transfer Enable Registers A to D (DTEA to DTED) These four registers designate whether an interrupt starts the DTC. The bits in these registers are assigned to interrupts as indicated in table 6-3. No bits are assigned to the NMI, FOVI, OVI, and ERI interrupts, which cannot request data transfers.
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Table 6-3 Assignment of Data Transfer Enable Registers
Interrupt Source Register Module Bits 7 to 4 7 6 DTEA IRQ0 -- -- DTEB DTEC DTED 16-Bit FRT1 8-Bit timer SCI2 -- -- -- Interrupt Source Module Bits 3 to 0 3 2 IRQ1 to IRQ3 -- IRQ3 16-Bit FRT2 -- -- --
5 --
4 IRQ0 ICI
1 IRQ2
0 IRQ1 ICI -- ADI
OCIB OCIA -- TXI
OCIB OCIA TXI -- RXI --
CMIB CMIA SCI1 RXI -- A/D converter
Note: Bits marked "--" should always be cleared to 0.
If the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for DTC service. If the bit is cleared to 0, the interrupt is regarded as a CPU interrupt request. Only the 16 interrupts indicated in table 6-3 can request DTC service. DTE bits not assigned to any interrupt (indicated by "--" in table 6-3) should be left cleared to 0.
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Note on Timing of DTE Modifications: The interrupt controller requires two system clock (o) periods to determine the priority level of an interrupt. Accordingly, when an instruction modifies a data transfer enable register, the new setting does not take effect until after the next instruction has been executed.
6.3 Data Transfer Operation
6.3.1 Data Transfer Cycle When started by an interrupt, the DTC executes the following data transfer cycle: 1. From the DTC vector table, the DTC reads the address at which the register information table for that interrupt is located in memory. 2. The DTC loads the data transfer mode register and source address register from this table and reads the data (one byte or word) from the source address. 3. If so specified in the mode register, the DTC increments the source address register and writes the new source address back to the table in memory. 4. The DTC loads the data transfer destination address register and writes the byte or word of data to the destination address. 5. If so specified in the mode register, the DTC increments the destination address register and writes the new destination address back to the table in memory. 6. The DTC loads the data transfer count register from the table in memory, decrements the data count, and writes the new count back to memory. 7. If the data transfer count is now 0, the DTC generates a CPU interrupt. The interrupt vector is the vector of the interrupt type that started the DTC. At an appropriate point during this procedure the DTC also clears the interrupt request by clearing the corresponding flag bit in the status register of the on-chip supporting module to 0. But the DTC does not clear the data transfer enable bit in the data transfer enable register. This action, if necessary, must be taken by the user-coded interrupt-handling routine invoked at the end of the transfer. The data transfer cycle is shown in a flowchart in figure 6-2. For the steps from the occurrence of the interrupt up to the start of the data transfer cycle, see section 5.4.1, "Interrupt Handling Flow."
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INT N
Interrupt CPU
DTC interrupt? DTC Y
Save PC and SR Read DTC vector Read vector Read transfer mode Read source address Read data Y Start executing interrupt-handling routine at that address. Read address from vector table
Source address increment mode? N
Increment source address (+1 or +2) Write source address
Read destination address Write data
Destination address increment mode? N
Y
Increment destination address (+1 or +2) Write destination address
Read DTCR DTCR-1 DTCR Write DTCR Y DTCR = 0? N DTC END
Figure 6-2 Flowchart of Data Transfer Cycle
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Fig. 6-2
6.3.2 DTC Vector Table The DTC vector table is located immediately following the exception vector table at the beginning of page 0 in memory. For each interrupt that can request DTC service, the DTC vector table provides a pointer to an address in memory where the table of DTC control register information for that interrupt is stored. The register information tables can be placed in any available locations in page 0.
Vector table RAM
DTMR0 Register information table 0 DTSR0 DTDR0 DTCR0
Exception vector table
TA0
DTMR1 TA0 TA1 TA1 DTC vector table Register information table 1 DTSR1 DTDR1 DTCR1
Note: TA0, TA1, ...: Addresses of DTC register information tables in memory.
Note: TA 0 , TA1,... : Addresses of DTC register information tables in memory.
Normally the register information tables are placed on RAM. If software does not need to modify the register information (addresses are fixed and transfer count is 1), it can be placed on ROM.
Figure 6-3 DTC Vector Table In minimum mode, each entry in the DTC vector table consists of two bytes, pointing to an address in page 0. In maximum mode, for compatibility reasons, each DTC vector table entry Fig. 6-3 consists of four bytes but the first two bytes are ignored; the last two bytes point to an address which is implicitly assumed to be in page 0, regardless of the current page specifications. Figure 6-4 shows one DTC vector table entry in minimum and maximum mode.
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DTC vector table Address m Address (H)
RAM
DTC vector table Address
Register information
Don't care
2m*
m+1
Address (L)
Don't care
2 m + 1*
Address (H)
2m+2
Address (L)
2m+3
(1) Minimum mode * Address 2m and 2m + 1 are not accessed at vector read.
(2) Maximum mode
Figure 6-4 DTC Vector Table Entry Table 6-4 lists the addresses of the entries in the DTC vector table for each interrupt. Table 6-4 Addresses of DTC Vectors
Interrupt IRQ0 IRQ1 IRQ2 IRQ3 16-Bit FRT1 16-Bit FRT2 8-Bit timer SCI1 SCI2 A/D converter
Fig. 6-4
ICI OCIA OCIB ICI OCIA OCIB CMIA CMIB RXI TXI RXI TXI ADI
Address of DTC Vector Minimum Mode Maximum Mode H'00C0 - H'00C1 H'0180 - H'0183 H'00C8 - H'00C9 H'0190 - H'0193 H'00CA - H'00CB H'0194 - H'0197 H'00CC - H'00CD H'0198 - H'019B H'00D0 - H'00D1 H'01A0 - H'01A3 H'00D2 - H'00D3 H'01A4 - H'01A7 H'00D4 - H'00D5 H'01A8 - H'01AB H'00D8 - H'00D9 H'01B0 - H'01B3 H'00DA - H'00DB H'01B4 - H'01B7 H'00DC - H'00DD H'01B8 - H'01BB H'00E0 - H'00E1 H'01C0 - H'01C3 H'00E2 - H'00E3 H'01C4 - H'01C7 H'00EA - H'00EB H'01D4 - H'01D7 H'00EC - H'00ED H'01D8 - H'01DB H'00F2 - H'00F3 H'01E4 - H'01E7 H'00F4 - H'00F5 H'01E8 - H'01EB H'00F8 - H'00F9 H'01F0 - H'01F3
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6.3.3 Location of Register Information in Memory For each interrupt, the DTC control register information is stored in four consecutive words in memory in the order shown in figure 6-5.
DTC vector table RAM
DTMR TA + 2 TA TA + 4 TA + 6 DTSR DTDR DTCR 8 Bits 8 Bits
Mode register Source address register Destination address register
Count register
Figure 6-5 Order of Register Information 6.3.4 Length of Data Transfer Cycle
Fig. 6-5 Table 6-5 lists the number of states required per data transfer, assuming that the DTC control register information is stored in a memory area accessed in two states via a 16-bit bus.
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Table 6-5 Number of States per Data Transfer
Increment Mode Source (SI) 0 0 1 1 Destination (DI) 0 1 0 1 16-Bit Bus, 2State Access Module or I/O Memory Area Register Byte Transfer 31 33 33 35 Word Transfer 34 36 36 38 8-Bit Bus, 3State Access Module or I/O Memory Area Register Byte Transfer 32 34 34 36 Word Transfer 38 40 40 42
Note: Numbers in the table are the number of states.
The values in table 6-5 are calculated from the formula: N = 26 + 2 x SI + 2 x DI + MS + MD Where MS and MD have the following meanings: MS: Number of states for reading source data MD: Number of states for writing destination data The values of MS and MD depend on the data location as follows: 1. Byte or word data in 16-bit bus, 2-state-access memory area: 2. Byte data in 8-bit bus, 3-state-access memory area or register field: 3. Word data in 8-bit bus, 3-state-access memory area or register field:

2 states 3 states 6 states
If the DTC control register information is stored in the RAM, 20 + 4 x SI + 4 x DI must be added to the values in table 6-5. The values given above do not include the time between the occurrence of the interrupt request and the starting of the DTC. This time includes two states for the interrupt controller to check priority and a variable wait until the end of the current CPU instruction. At maximum, this time equals the sum of the values indicated for items No. 1 and 2 in table 6-6. If the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is executed is the value given for item No. 3 in table 6-6.
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Table 6-6 Number of States before Interrupt Service
Number of States Minimum Mode Maximum Mode 2 states 2 states 38 (LDM instruction specifying all registers) 74 + 16m (LDM instruction specifying all registers) 16 21 28 + 6m 41 + 10m
No. Reason for Wait 1 Interrupt priority decision and comparison with mask level in status register 2 Maximum number of Instruction is in 16-bit bus, states to completion 2-state access memory area of current instruction Instruction is in 8-bit bus, 3-state access memory area 3 Saving of PC and SR Stack is in 16-bit bus, or PC, CP, and SR, 2-state access memory area and instruction prefetch Stack is in 8-bit bus, 3-state access memory area m: Number of wait states inserted in memory access
6.4 Procedure for Using the DTC
A program that uses the DTC to transfer data must do the following: 1. Set the appropriate DTMR, DTSR, DTDR, and DTCR register information in the memory location indicated in the DTC vector table. 2. Set the data transfer enable bit of the pertinent interrupt to 1, and set the priority of the interrupt source (in the interrupt priority register) and the interrupt mask level (in the CPU status register) so that the interrupt can be accepted. 3. Set the interrupt enable bit in the control register for the interrupt source. (For IRQ0 and IRQ1, the control register is the port 1 control register, P1CR). Following these preparations, the DTC will be started each time the interrupt occurs. When the number of bytes or words designated by the DTCR value have been transferred, after transferring the last byte or word, the DTC generates a CPU interrupt. The user-coded interrupt-handling routine must take action to prepare for or disable further DTC data transfer: by readjusting the data transfer count, for example, or clearing the interrupt enable bit. If no action is taken, the next interrupt of the same type will start the DTC with an initial data transfer count of 65,536.
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6.5 Example
1. Purpose To receive 128 bytes of serial data via serial communication interface1. 2. Conditions * * * * Operating mode: Minimum mode Received data are to be stored in consecutive addresses starting at H'FC00. DTC control register information for the RXI interrupt is stored at addresses H'FB80 to H'FB87. Accordingly, the DTC vector table contains H'FB at address H'00EA and H'80 at address H'00EB. * The desired interrupt mask level in the CPU status register is 4, and the desired SCI1 interrupt priority level is 5. 3. Procedure 1. The user program sets DTC control register information as shown in table 6-7. Table 6-7 DTC Control Register Information Set in RAM
Register DTMR DTSR DTDR DTCR Description Byte transfer Source address fixed Increment destination address Address of SCI1 receive data register Address H'FC00 Number of bytes to be received: 128 Value Set H'2000 H'FECD H'FC00 H'0080
2. The program sets the RXI (SCI Receive Interrupt) bit in the data transfer enable register (DTEC) to 1. 3. The program sets the interrupt mask in the CPU status register to 4, and the SCI interrupt priority in bits 2 to 0 of interrupt priority register IPRC to 5. 4. The program sets SCI1 to the appropriate receive mode, and sets the receive interrupt enable (RIE) bit in the serial control register (SCR) to 1 to enable receive interrupts. 5. Thereafter, each time SCI1 receives one byte of data, it requests an RXI interrupt, which the interrupt controller directs toward the DTC. The DTC transfers the byte from the SCI1's receive data register (RDR) into RAM, and clears the interrupt request before ending.
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6. When 128 bytes have been transferred (DTCR = 0), the DTC generates a CPU interrupt. The interrupt type is RXI from SCI1. 7. The user-coded RXI interrupt-handling routine processes the received data and disables further data transfer (by clearing the RIE bit, for example). Figure 6-6 shows the DTC vector table and data in RAM for this example.
DTC vector table
Address H'FB80 H'FB81
RAM H'20 Mode H'00 H'FE Source address H'CD H'FC Destination address H'00 H'00 Counter
Address H'00EA H'00EB H'FB H'80
H'FB87
H'80
H'FC00
Receive data 1 Receive data 2
Transferred by DTC H'FC7F Receive data 128
RDR SCI
Figure 6-6 Use of DTC to Receive Data via Serial Communication Interface
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Section 7 Wait-State Controller
7.1 Overview
To simplify interfacing to low-speed external devices, the H8/510 has an on-chip wait-state controller (WSC) that can insert wait states (TW) to prolong bus cycles. The wait-state function can be used in CPU and DTC access cycles to the three-state-access memory area. It is not used in access to the two-state-access memory area or on-chip supporting modules. The TW states are inserted between the T2 state and T3 state in the bus cycle. The number of wait states can be selected by a value set in the wait-state control register (WCR), or by holding the WAIT pin Low for the required interval. 7.1.1 Features The main features of the wait-state controller are: * Selection of three operating modes Programmable wait mode, pin wait mode, or pin auto-wait mode * 0, 1, 2, or 3 wait states can be inserted. And in the pin wait mode, 4 or more states can be inserted by holding the WAIT pin Low.
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7.1.2 Block Diagram Figure 7-1 shows a block diagram of the wait-state controller.
Internal data bus
WCR -- -- -- -- WMS1 WMS0 WC1 WC0
Wait counter
WAIT request
Control logic
WAIT input
WCR: Wait-state Control Register WMS1, 0: Wait Mode Select 1, 0 WC1, 0: Wait Count 1, 0
Figure 7-1 Block Diagram of Wait-State Controller 7.1.3 Register Configuration
Fig. 7-1
The wait-state controller has one control register: the wait-state control register described in table 7-1. Table 7-1 Register Configuration
Name Wait-state control register Abbreviation WCR Read/Write R/W Initial Value H'F3 Address H'FF14
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7.2 Wait-State Control Register
The wait-state control register (WCR) is an 8-bit register that specifies the wait mode and the number of wait states to be inserted. A reset initializes the WCR to specify the programmable wait mode with three wait states. The WCR is not initialized in the software standby mode.
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W
Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1 and WMS0): These bits select the wait mode as shown below.
Bit 3 WMS1 0 0 1 1 Bit 2 WMS0 0 1 0 1
Description Programmable wait mode (Initial value) No wait states are inserted, regardless of the wait count. Pin wait mode Pin auto-wait mode
Bits 1 and 0--Wait Count (WC1 and WC0): These bits specify the number of wait states to be inserted. Wait states are inserted only in bus cycles in which the CPU or DTC accesses the three-stateaccess memroy area.
Bit 1 WC1 0 0 1 1 Bit 0 WC0 0 1 0 1
Description No wait states are inserted, except in pin wait mode. 1 Wait state in inserted. 2 Wait states are inserted. 3 Wait states are inserted. (Initial value)
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7.3 Operation in Each Wait Mode
Table 7-2 summarizes the operation of the three wait modes. Table 7-2 Wait Modes
WAIT Insertion Pin Function Conditions Disabled Inserted on access to three-state-access memory area Enabled Number of Wait States Inserted 1 to 3 wait states are inserted, as specified by bits WC0 and WC1.
Mode Programmable wait mode WMS1 = 0 WMS0 = 0 Pin wait mode WMS1 = 1 WMS0 = 0 Pin auto-wait mode WMS1 = 1 WMS0 = 1
Enabled
Inserted on access to 0 to 3 wait states are inserted, as three-state-access specified by bits WC0 and WC1, memory area plus additional wait states while the WAIT pin is held Low. Inserted on access to 1 to 3 wait states are inserted, as three-state-access specified by bits WC0 and WC1. memory area if the WAIT pin is Low
7.3.1 Programmable Wait Mode The programmable wait mode is selected when WMS1 = 0 and WMS0 = 0. Whenever the CPU or DTC accesses an address in the three-state-access memory area, the number of wait states set in bits WC1 and WC0 are inserted. The WAIT pin is not used for wait control; it is available as an I/O pin (P30).
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Figure 7-2 shows the timing of the operation in this mode when the wait count is 1 (WC1 = 0, WC0 = 1).
T2 or T3 o
T1
T2
TW
T3
A 23 -A 0
Three-state-access address
RD, AS (Read) Read data D15 -D0 Read data
HWR, LWR (Write)
D15 -D 0
Write data
Figure 7-2 Programmable Wait Mode
7.3.2 Pin Wait Mode The pin wait mode is selected when WMS1 = 1 and WMS0 = 0. In this mode the WAIT function of the P30 /WAIT pin is used automatically. The number of wait states indicated by bits WC1 and WC0 are inserted into any bus cycle in which the CPU or DTC accesses an address in the three-state-access memory area. In addition, wait states continue to be inserted as long as the WAIT pin is held low. In particular, if the wait count is 0 but the WAIT pin is low at the rising edge of the system clock in the T2 state, wait states are inserted until the WAIT pin goes high. This mode is useful for inserting four or more wait states, or when different external devices require different numbers of wait states.
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Figure 7-3 shows the timing of the operation in this mode when the wait count is 1 (WC1 = 0, WC0 = 1) and the WAIT pin is held low to insert one additional wait state.
T1
T2
Wait count TW
WAIT pin TW
T3
o
*
*
WAIT pin
A 23 -A 0 RD, AS (Read)
Three-state-access address
Read data D15 -D0 HWR, LWR (Write)
D15 -D0
Write data
* The arrowheads indicate the times at which the WAIT pin is sampled.
Figure 7-3 Pin Wait Mode
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7.3.3 Pin Auto-Wait Mode The pin auto-wait mode is selected when WMS1 = 1 and WMS0 = 1. In this mode the WAIT function of the P30 /WAIT pin is used automatically. In this mode, the number of wait states indicated by bits WC1 and WC0 are inserted, but only if there is a Low input at the WAIT pin. Figure 7-4 shows the timing of this operation when the wait count is 1. In the pin auto-wait mode, the WAIT pin is sampled only once, on the falling edge of the o clock in the T2 state. If the WAIT pin is Low at this time, the wait-state controller inserts the number of wait states indicated by bits WC1 and WC0. The WAIT pin is not sampled during the Tw and T3 states, so no additional wait states are inserted even if the WAIT pin continues to be held Low. This mode offers a simple way to interface a low-speed device: the wait states can be inserted by routing an address decode signal to the WAIT pin.
T1 T2 T3 T1 T2 TW T3
o
*
*
WAIT
A 23 -A 0
3-state access address
3-state access address
RD, AS (Read) Read data D15 -D 0 Read data
HWR, LWR (Write)
D15 -D 0
Write data
Write data
* The arrowheads indicate the times at which the WAIT pin is sampled.
Figure 7-4 Pin Auto-Wait Mode
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The H8/510 wait-state-controller supports programmable wait mode, pin wait mode, and pin auto wait mode. These functions will be effective to bus cycles when the CPU accesses external address space. On the other hand, the refresh-controller supports a wait state insertion programmable by the refresh control register independently of the wait-state controller. The refresh-controller, however, supports only programmable wait mode and pin wait mode, not pin wait mode. Therefore, if pin auto wait mode is selected by the wait-state-controller, and if CS of DRAM is connected to WAIT, the wait state will not be released in refresh cycles. Please refer and follow the flowchart below.
Pin auto wait mode?
No
No restriction
Yes No
Refresh controller enabled? Yes
Initialize using the following sequence. =0 1. Disable or set refreshcontroller. 2. Set wait-state-controller.
The number of refresh wait cycles? =0 /
Gate the WAIT signal by RFSH in order to keep the WAIT "high" level. And program the wait state of refresh cycle by register of refresh-controller.
RFSH CS (DRAM)
WAIT
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Section 8 Clock Pulse Generator
8.1 Overview
The H8/510 chip has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a system (o) clock divider, an E clock divider, and a group of prescalers. The prescalers generate clock signals for the on-chip supporting modules. 8.1.1 Block Diagram
CPG
Prescaler Divider /2 Divider /8
XTAL EXTAL
Oscillator
o
E
o/2 to o/4096
Figure 8-1 Block Diagram of Clock Pulse Generator
8.2 Oscillator Circuit
Fig. 8-1
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. Alternatively, an external clock signal can be applied directly. 1. Connecting an External Crystal Circuit Configuration: An external crystal can be connected as in the example in figure 8-2. An AT-cut parallel resonating crystal should be used.
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CL1 EXTAL
XTAL CL2 CL1 =C L2 =10 to 22 pF
Figure 8-2 Connection of Crystal Oscillator (Example) Crystal Oscillator: The external crystal should have the characteristics listed in table 8-1.
CL L XTAL Fig. 8-2 RS EXTAL
C0 AT-cut parallel resonating crystal
Figure 8-3 Crystal Oscillator Equivalent Circuit Table 8-1 External Crystal Parameters
Frequency (MHz) Rs max () C0 (pF) 2 4 500 120 7 pF max 8 60
Fig. 8-3 12
40
16 30
20 20
Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 8-4. When the board is designed, the crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins.
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Not allowed
Signal A
Signal B
H8/510
CL2 XTAL
EXTAL CL1
Figure 8-4 Notes on Board Design around External Crystal 2. Input of External Clock Signal Circuit Configuration: An external clock signal can be input at the EXTAL and XTAL pins as shown in the example in figure 8-5.
EXTAL External clock input XTAL Open
Figure 8-5 External Clock Input (Example)
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External Clock Input
Frequency Duty factor Double the system clock (o) frequency 45% to 55%
Note on Connection: Leave the XTAL pin open.
8.3 System Clock Divider
The system clock divider divides the crystal oscillator or external clock frequency (fosc) by 2 to create the o clock. An E clock signal is created by dividing the o clock by 8. The E clock is used for interfacing to E clock based devices. Figure 8-6 shows the phase relationship of the E clock to the o clock.
o
E E
Figure 8-6 Phase Relationship of o Clock and E Clock
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Section 9 I/O Ports
9.1 Overview
The H8/510 has eight ports. Ports 1, 2, 3, 4, 5, 6, and 8 are eight-bit input/output ports. Port 7 is a four-bit input port. Table 9-1 summarizes the functions of each port. Input and output are memory-mapped. The CPU views each port as a data register (DR) located in the on-chip register field at the high end of page 0 of the address space. Each port (except port 7) also has a data direction register (DDR) which determines which pins are used for input and which for output. In addition to the data and data direction registers, the bus release control register (BRCR) affects the operation of port 3. To read data from an I/O port, the CPU selects input in the data direction register and reads the data register. This causes the input logic level at the pin to be placed directly on the internal data bus. There is no intervening input latch. To send data to an output port, the CPU selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. The latch output drives the pin through a buffer amplifier. If the CPU reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. Outputs from ports 1 to 2 can drive one TTL load and a 90-pF capacitive load. Outputs from ports 3 to 6 and port 8 can drive one TTL load and a 30-pF capacitive load. Port 4 has Schmitt-triggered inputs. Outputs from ports 1 to 6 and port 8 can also drive a Darlington transistor pair. Schematic diagrams of the I/O port circuits are shown in appendix C.
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Table 9-1 Input/Output Port Summary
Port Description Port 1 8-Bit I/O port Port 2 8-Bit I/O port Port 3 8-Bit I/O port Pins Mode 1 Mode 2 Mode 3 Mode 4 P17 - P10 I/O port Data bus I/O port Data bus D7 - D0 (D7 - D0) (D7 - D0) P27 - P20 I/O port Address bus (A23 - A16) A23 - A16 P37 8-Bit I/O port, also used for BACK, BREQ, and WAIT P36 * BACK, BREQ, WAIT: These pin functions are used when P35 the corresponding control register bit is set to 1. If the P34 control bit is cleared to 0, the pin is used as an P33 input/output port. P32 / BREQ * The three pins used for these signals are P30 to P32. P31 / BACK P30 / WAIT P47 / FTCI2 Input and output pins (FTI1, FTI2, FTCI1, FTCI2) for the P46 / FTI2 16-bit free-running timers (FRT1 and FRT2), input (TMCI, P45 / FTCI1 TMRI) and output (TMO) pins for the 8-bit timer, input pin P44 / FTI1 for ADTRG,and I/O port. P43 / TMO * ADTRG: This pin function is used when the P42 / TMRI corresponding control register bit is set to 1. If the control P41 / TMCI bit is cleared to 0, the pin is used as an input/output port. P40 / ADTRG P57 8-Bit I/O port, also providing output pins (FTOB2, FTOA2, P56 FTOB1, FTOA1) for FRT1 and FRT2. P55 * The four pins with dual functions are P50 to P53. P54 P53 / FTOB2 P52 / FTOA2 P51 / FTOB1 P50 / FTOA1 P67 - P60 I/O port P73 -P70 / Input port, also providing analog input pins (AN3 to AN0) AN3 - AN0 for the A/D converter P87 / TXD2 I/O port, also providing input and output pins (RXD1, TXD1, P86 / RXD2 RXD2, TXD2, SCK1, SCK2) for the serial communication P85 / TXD1 interfaces (SCI1 and SCI2) and interrupt request input pins P84 / RXD1 (IRQ0 to IRQ3). P83 / IRQ3/SCK2 P82 / IRQ2/SCK1 P81 / IRQ1 P80 / IRQ0 126
Port 4 8-Bit I/O port
Port 5 8-Bit I/O port
Port 6 8-Bit I/O port Port 7 4-Bit input port Port 8 8-Bit I/O port
9.2 Port 1
9.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. The pins are used for the data bus in modes 2 and 4, and as general-purpose input or output pins in modes 1 and 3. Outputs from port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington pair.
Pin P17 / D7 P16 / D6 P15 / D5 P14 / D4 P13 / D3 P12 / D2 P11 / D1 P10 / D0 Modes 2 and 4 D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Modes 1 and 3 P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output)
Port 1
Figure 9-1 Pin Functions of Port 1 9.2.2 Port 1 Registers Table 9-2 lists the registers of port 1. Table 9-2 Port 1 Registers
Name Port 1 data direction register Port 1 data register Abbreviation P1DDR P1DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE80 H'FE82
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1. Port 1 Data Direction Register (P1DDR)--H'FE80
Bit 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P1DDR is an 8-bit register that selects the direction of each pin in port 1. Modes 1 and 3: A pin functions as an output pin if the corresponding bit in P1DDR is set to 1, and as in input pin if the bit is cleared to 0. P1DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P1DDR is initialized to H'00 by a reset and in the hardware standby mode. P1DDR is not initialized in the software standby mode, so if a P1DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 1 data register. 2. Port 1 Data Register (P1DR)--H'FE82
Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W
P1DR is an 8-bit register containing output data for pins P17 to P10. P1DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P1DR, for output pins it reads the value in the P1DR latch. For input pins, it reads the logic level directly from the pin. 9.2.3 Pin Functions in Each Mode The function of port 1 depends on whether the chip is operating in mode 1 or 3, or in mode 2 or 4. This information is summarized below.
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Pin Functions in Modes 2 and 4: Port 1 is automatically used for the data bus. The direction bits in P1DDR are ignored. Figure 9-2 shows the pin functions in modes 2 and 4.
Pin D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output)
Port 1
Figure 9-2 Pin Functions of Port 1 in Modes 2 and 4 Pin Functions in Modes 1 and 3: Port 1 is a general-purpose input/output port in which each pin can be set individually for input or output. See figure 9-3. A pin becomes an output pin when the corresponding P1DDR bit is set to 1, and an input pin when this bit is cleared to 0.
Pin P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output)
Port 1
Figure 9-3 Pin Functions of Port 1 in Modes 1 and 3
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9.3 Port 2
9.3.1 Overview Port 2 is a 8-bit input/output port with the pin configuration shown in figure 9-4. The pins are used for page address output (A23 to A16) in the maximum modes, and as general-purpose input or output pins in the minimum modes. Outputs from port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington pair.
Pin P27 / A23 P26 / A22 P25 / A21 P24 / A20 P23 / A19 P22 / A18 P21 / A17 P20 / A16 Maximum Modes A23 (output) A22 (output) A21 (output) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) Minimum Modes P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output)
Port 2
Figure 9-4 Pin Functions of Port 2 9.3.2 Port 2 Registers Table 9-3 lists the registers of port 2. Table 9-3 Port 2 Registers
Name Port 2 data direction register Port 2 data register Abbreviation P2DDR P2DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE81 H'FE83
1. Port 2 Data Direction Register (P2DDR)--H'FE81
Bit 7 6 5 4 3 2 1 0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P2DDR is an 8-bit register that selects the direction of each pin in port 2.
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Minimum Modes: A pin functions as an output pin if the corresponding bit in P2DDR is set to 1, and as an input pin if the bit is cleared to 0. P2DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P2DDR is initialized to H'00 by a reset and in the hardware standby mode. P2DDR is not initialized in the software standby mode, so if a P2DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 2 data register. Modes 2 and 4: All bits in P2DDR are automatically set to 1 and cannot be modified. 2. Port 2 Data Register (P2DR)--H'FE83
Bit 7 P27 Initial value Read/Write 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W
P2DR is an 8-bit register containing output data for pins P27 to P20. P2DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P2DR, for output pins it reads the value in the P2DR latch. For input pins, it reads the logic level directly from the pin. 9.3.3 Pin Functions in Each Mode The function of port 2 depends on whether the chip is operating in maximum mode (mode 3 or 4) or minimum mode (mode 1 or 2). This information is summarized below. Pin Functions in Maximum Modes: P2DDR is automatically set for output and port 2 is used for output of the page address (A23 to A16). Figure 9-5 shows the pin functions in the maximum modes.
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Port 2
Pin A23 (output) A22 (output) A21 (output) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output)
Figure 9-5 Pin Functions of Port 2 in Maximum Modes Pin Functions in Minimum Modes: Port 2 is a general-purpose input/output port in which each pin can be set individually for input or output. See figure 9-6. A pin becomes an output pin when the corresponding P2DDR bit is set to 1, and an input pin when this bit is cleared to 0.
Pin P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output)
Port 2
Figure 9-6 Pin Functions of Port 2 in Minimum Modes
9.4 Port 3
9.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 9-7. The pin functions are the same in all MCU modes. Three of the pins are used for input and output of the BACK, BREQ, and WAIT signals. Outputs from port 3 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington pair.
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Port 3
Pin P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) / BREQ (input) P31 (input/output) / BACK (output) P30 (input/output) / WAIT (input)
Figure 9-7 Pin Functions of Port 3 9.4.2 Port 3 Registers Table 9-4 lists the registers of port 3. Table 9-4 Port 3 Registers
Name Port 3 data direction register Port 3 data register Bus release control register Abbreviation P3DDR P3DR BRCR Read/Write W R/W R/W Initial Value H'00 H'00 H'FE Address H'FE84 H'FE86 H'FF1B
1. Port 3 Data Direction Register (P3DDR)--H'FE84
Bit 7 6 5 4 3 2 1 0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P3DDR is an 8-bit register that selects the direction of each pin in port 3. A pin functions as an output pin if the corresponding bit in P3DDR is set to 1, and as in input pin if the bit is cleared to 0. P3DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values.
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P3DDR is initialized to H'00 by a reset and in the hardware standby mode. P3DDR is not initialized in the software standby mode, so if a P3DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 3 data register. 2. Port 3 Data Register (P3DR)--H'FE86
Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W
P3DR is an 8-bit register containing the data for pins P37 to P30. P3DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P3DR, for output pins it reads the value in the P3DR latch. For input pins, it reads the logic level directly from the pin. 3. Bus Release Control Register (BRCR)--H'FF1B
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 BRLE 0 R/W
BRCR controls the selection of pin functions for port 3. BRCR is initialized to H'FE by a reset and in the hardware standby mode. It is not initialized in the software standby mode. Bits 7 to 1--Reserved: These bits cannot be written and are always read as 1. Bits 0--Bus Release Enable (BRLE): Controls the functions of P32 and P31.
Bit 0 BRLE 0 1
Description P32 and P31 are general-purpose input/output pins. P32 is used for BREQ input, and P31 for BACK output.
(Initial value)
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9.4.3 Pin Functions Port 3 has same pin functions in all modes. Pins P33 to P30 are also used for input of BREQ and WAIT and output of BACK as shown in figure 9-7. Table 9-5 details the pin functions of port 3. Table 9-5 Port 3 Pin Functions
Pin P32 / BREQ Selection of Pin Functions Depends on the BRLE and P32DDR bits as follows: BRLE P32DDR Pin function P31 / BACK 0 0 P32 input 1 P32 output 1 0 1 BREQ input
Depends on the BRLE and P31DDR bits as follows: BRLE P31DDR Pin function 0 0 P31 input 1 P31 output 1 0 1 BACK output
P30 / WAIT
Depends on the wait mode select 1 bit (WMS1) in the wait state control register (WCR) and P30DDR as follows: WMS1 P30DDR Pin function 0 0 P30 input 1 P30 output 0 WAIT input 1 1
9.5 Port 4
9.5.1 Overview Port 4 is an 8-bit input/output port with the pin configuration shown in figure 9-8. It also provides input pins for the 16-bit free-running timers (FRT1 and FRT2), input (TMCI, TMRI) and output (TMO) pins for the 8-bit timer, and the ADTRG input pin. The pin functions are the same in all MCU modes. Port 4 has Schmitt inputs. Outputs from port 4 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington pair.
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Port 4
Pin P47 P46 P45 P44 P43 P42 P41 P40
(input/output) / FTCI2 (input) (input/output) / FTI2 (input) (input/output) / FTCI1 (input) (input/output) / FTI1 (input) (input/output) / TMO (output) (input/output) / TMRI (input) (input/output) / TMCI (input) (input/output) / ADTRG (input)
Figure 9-8 Pin Functions of Port 4 9.5.2 Port 4 Registers Table 9-6 lists the registers of port 4. Table 9-6 Port 4 Registers
Name Port 4 data direction register Port 4 data register Abbreviation P4DDR P4DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE85 H'FE87
1. Port 4 Data Direction Register (P4DDR)--H'FF85
Bit 7 6 5 4 3 2 1 0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P4DDR is an 8-bit register that selects the direction of each pin in port 4. A pin functions as an output pin if the corresponding bit in P4DDR is set to 1, and as in input pin if the bit is cleared to 0. P4DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P4DDR is initialized to H'00 by a reset and in the hardware standby mode. P4DDR is not initialized in the software standby mode, so if a P4DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 4 data register.
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When a pin of port 4 is used by an on-chip supporting module (as an 8-bit timer output pin, for example), if a transition to the software standby mode occurs the on-chip supporting module is initialized, so the pin becomes a general-purpose input/output pin according to P4DDR and P4DR. 2. Port 4 Data Register (P4DR)--H'FE87
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W
P4DR is an 8-bit register containing the data for pins P47 to P40. P4DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P4DR, for output pins it reads the value in the P4DR latch. For input pins, it reads the logic level directly from the pin. 9.5.3 Pin Functions Port 4 has the same pin functions in all modes. As shown in figure 9-8, it also provides input pins for FRT1 and FRT2, input and output pins for the 8-bit timer, and the ADTRG input pin. Table 9-7 lists the registers of port 4. Table 9-7 Port 4 Pin Functions
Pin P47 / FTCI2 Selection of Pin Functions Used for input of the FRT2 external clock when the CKSO and CKS1 bits in the FRT2 timer control register (TCR) select the external clock source. P47DDR Pin function 0 1 P47 input P47 output FTCI2 input
P46 / FTI2 P46DDR Pin function 0 1 P46 input P46 output FTI2 input
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Table 9-7 Port 4 Pin Functions (cont)
Pin P45 / FTCI1 Selection of Pin Functions Used for input of the FRT1 external clock when the CKS0 and CKS1 bits in the FRT1 timer control register (TCR) select the external clock source. P45DDR Pin function 0 1 P45 input P45 output FTCI1 input
P44 / FTI1 P44DDR Pin function 0 1 P44 input P44 output FTI1 input
P43 / TMO
Use depends on the P43DDR bit and output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR) of the 8-bit timer. OS3 to OS0 P43DDR Pin function All 0 0 1 P43 input P43 output Not all 0 0 1 TMO output
P42 / TMRI
Used for reset input for the 8-bit timer when counter clear bits 1 and 0 (CCLR1 and CCLR0) in the timer control register (TCR) of the 8-bit timer are both set to 1. P42DDR Pin function 0 1 P42 input P42 output TMRI input
P41 / TMCI
Used for external clock input for the 8-bit timer when clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (TCR) of the 8-bit timer select the external clock source. P41DDR Pin function 0 1 P41 input P41 output TMCI input
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Table 9-7 Port 4 Pin Functions (cont)
Pin Selection of Pin Functions P40 / ADTRG Depends on the P40DDR bit and the trigger enable bit (TRGE) in the A/D control register (ADCR) as follows: TRGE P40DDR Pin function 0 0 P40 input 1 P40 output 1 0 1 ADTRG input
9.6 Port 5
9.6.1 Overview Port 5 is an 8-bit input/output port with the pin configuration shown in figure 9-9. The pin functions are the same in all MCU modes. Four of the pins are used for output of signals from the 16-bit free-running timers (FRT1 and FRT2). Outputs from port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington pair.
Port 5
Pin P57 P56 P55 P54 P53 P52 P51 P50
(input/output) (input/output) (input/output) (input/output) (input/output) / FTOB2 (output) (input/output) / FTOA2 (output) (input/output) / FTOB1 (output) (input/output) / FTOA1 (output)
Figure 9-9 Pin Functions of Port 5
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9.6.2 Port 5 Registers Table 9-8 lists the registers of port 5. Table 9-8 Port 5 Registers
Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE88 H'FE8A
1. Port 5 Data Direction Register (P5DDR)--H'FE88
Bit 7 6 5 4 3 2 1 0
P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P5DDR is an 8-bit register that selects the direction of each pin in port 5. A pin functions as an output pin if the corresponding bit in P5DDR is set to 1, and as in input pin if the bit is cleared to 0. P5DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P5DDR is initialized to H'00 by a reset and in the hardware standby mode. P5DDR is not initialized in the software standby mode, so if a P5DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 5 data register. When a pin of port 5 is used by an on-chip supporting module (as an FRT output pin), if a transition to the software standby mode occurs the on-chip supporting module is initialized, so the pin becomes a general-purpose input/output pin according to P5DDR and P5DR.
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2. Port 5 Data Register (P5DR)--H'FE8A
Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W
P5DR is an 8-bit register containing output data for pins P57 to P50. P5DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P5DR, for output pins it reads the value in the P5DR latch. For input pins, it reads the logic level directly from the pin. 9.6.3 Pin Functions Port 5 has the same pin functions in all modes. Some pins are also used for FRT output as shown in figure 9-9. Table 9-9 details the pin functions of port 5. Table 9-9 Port 5 Pin Functions
Pin Selection of Pin Functions P53 / FTOB2 Usage depends on the P53DDR bit and the output enable B bit (OEB) in the FRT2 timer control register (TCR) as follows: OEB P53DDR Pin function 0 0 P53 input 1 P53 output 1 0 1 FTOB2 output
P52 / FTOA2 Usage depends on the P52DDR bit and the output enable A bit (OEA) in the FRT2 timer control register (TCR) as follows: OEA P52DDR Pin function 0 0 P52 input 1 P52 output 1 0 1 FTOA2 output
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Table 9-9 Port 5 Pin Functions (cont)
Pin Selection of Pin Functions P51 / FTOB1 Usage depends on the P51DDR bit and the output enable B bit (OEB) in the FRT1 timer control register (TCR) as follows: OEB P51DDR Pin function 0 0 P51 input 1 P51 output 1 0 1 FTOB1 output
P50 / FTOA1 Usage depends on the P50DDR bit and the output enable A bit (OEA) in the FRT1 timer control register (TCR) as follows: OEA P50DDR Pin function 0 0 P50 input 1 P50 output 1 0 1 FTOA1 output
9.7 Port 6
9.7.1 Overview Port 6 is an 8-bit input/output port with the pin configuration shown in fugure 9-10. Outputs from port 6 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington pair.
Pin P67 P66 P65 P64 P63 P62 P61 P60
Port 6
(input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Figure 9-10 Pin Functions of Port 6
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9.7.2 Port 6 Registers Table 9-10 lists the registers of port 6. Table 9-10 Port 6 Registers
Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE89 H'FE8B
1. Port 6 Data Direction Register (P6DDR)--H'FE89
Bit 7 6 5 4 3 2 1 0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an output pin if the corresponding bit in P6DDR is set to 1, and as in input pin if the bit is cleared to 0. P6DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P6DDR is initialized to H'00 by a reset and in the hardware standby mode. P6DDR is not initialized in the software standby mode, so if a P6DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 6 data register. 2. Port 6 Data Register (P6DR)--H'FE8B
Bit 7 P67 Initial value Read/Write 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W
P6DR is an 8-bit register containing output data for pins P67 to P60. P6DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P6DR, for output pins it reads the value in the P6DR latch. For input pins, it reads the logic level directly from the pin.
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9.8 Port 7
9.8.1 Overview Port 7 is a 4-bit input port that also receives inputs for the on-chip A/D converter. The pin functions are the same in all MCU operating modes, as shown in figure 9-11.
Port 7
Pin P73 (input) / AN3 (intput) P72 (input) / AN2 (intput) P71 (input) / AN1 (intput) P70 (input) / AN0 (intput)
Figure 9-11 Pin Functions of Port 7 9.8.2 Port 7 Registers Port 7 has only the data register described in table 9-11. Since it is exclusively an input port, there is no data direction register. Table 9-11 Port 7 Registers
Name Port 7 data register Abbreviation P7DR Read/Write R Address H'FE8E
Port 7 Data Register (P7DR)--H'FE8E
Bit 7 -- Read/Write -- 6 -- -- 5 -- -- 4 -- -- 3 P73 R 2 P72 R 1 P71 R 0 P70 R
When the CPU reads P7DR it always reads the current logic level of each pin.
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9.9 Port 8
9.9.1 Overview Port 8 is an 8-bit input/output port with the pin configuration shown in fugure 9-12. It also provides input pins for IRQ0 to IRQ3 and input and output pins for the serial communication interfaces (SCI1 and SCI2). The pin functions are the same in all MCU modes. Outputs from port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington pair.
Port 8
Pin P87 P86 P85 P84 P83 P82 P81 P80
(input/output) / TXD2 (output) (input/output) / RXD2 (input) (input/output) / TXD1 (output) (input/output) / RXD1 (input) (input/output) / IRQ3 (input) / SCK2 (input/output) (input/output) / IRQ2 (input) / SCK1 (input/output) (input/output) / IRQ1 (input) (input/output) / IRQ0 (input)
Figure 9-12 Pin Functions of Port 8 9.9.2 Port 8 Registers Table 9-12 lists the registers of port 8. Table 9-12 Port 8 Registers
Name Port 8 data direction register Port 8 data register Abbreviation P8DDR P8DR Read/Write W R/W Initial Value H'00 H'00 Address H'FE8D H'FE8F
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1. Port 8 Data Direction Register (P8DDR)--H'FE8D
Bit 7 6 5 4 3 2 1 0
P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P8DDR is an 8-bit register that selects the dirction of each pin in port 8. A pin functions as an output pin if the corresponding bit in P8DDR is set to 1, and as in input pin if the bit is cleared to 0. P8DDR can be written but not read. An attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. P8DDR is initialized to H'00 by a reset and in the hardware standby mode. P8DDR is not initialized in the software standby mode, so if a P8DDR bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 8 data register. When a pin of port 8 is used by an on-chip supporting module (as an SCI output pin, for example), if a transition to the software standby mode occurs the on-chip supporting module is initialized, so the pin becomes a general-purpose input/output pin according to P8DDR and P8DR. 2. Port 8 Data Register (P8DR)--H'FE8F
Bit 7 P87 Initial value Read/Write 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W
P8DR is an 8-bit register containing output data for pins P87 to P80. P8DR is initialized to H'00 by a reset and in the hardware standby mode. When the CPU reads P8DR, for output pins it reads the value in the P8DR latch. For input pins, it reads the logic level directly from the pin.
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9.9.3 Pin Functions Port 8 has the same pin functions in all modes. As shown in figure 9-12, it also provides input pins for IRQ0 to IRQ3 and input and output pins for the serial communication interface. Table 9-13 shows the pin functions of port 8. Table 9-13 Port 8 Pin Functions
Pin P87 / TXD2 Selection of Pin Functions Usage depends on the P87DDR bit and the transmit enable (TE) bit in the SCI2 serial control register (SCR) as follows: TE P87DDR Pin function P86 / RXD2 0 0 P87 input 1 P87 output 1 0 1 TXD2 output
Usage depends on the P86DDR bit and the receive enable (RE) bit in the SCI2 serial control register (SCR) as follows: RE P86DDR Pin function 0 0 P86 input 1 P86 output 0 RXD2 input 1 1
P85 / TXD1
Usage depends on the P85DDR bit and the transmit enable (TE) bit in the SCI1 serial control register (SCR) as follows: TE P85DDR Pin function 0 0 P85 input 1 P85 output 1 0 1 TXD1 output
P84 / TXD1
Usage depends on the P84DDR bit and the receive enable (RE) bit in the SCI1 serial control register (SCR) as follows: RE P84DDR Pin function 0 0 P84 input 1 P84 output 0 RXD1 input 1 1
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Table 9-13 Port 8 Pin Functions (cont)
Pin Selection of Pin Functions P83 / SCK2 / Usage depends on the communication mode bit (C/A) and clock enable bits 1 IRQ3 and 0 (CKE1 and CKE0) in the SCI2 serial control register (SCR) as follows: C/A 0 CKE1 0 1 CKE0 0 1 0 1 Pin function See SCI2 SCI2 input below output 1 0 0 1 SCI2 output 1 0 1 SCI2 input
When C/A, CKE1, and CKE0 are all cleared to 0, usage depends on the IRQ3E and P83DDR bits as follows: IRQ3E P83DDR Pin function 0 0 P83 input 1 P83 output 0 IRQ3 input 1 1
P82 / SCK1 / Usage depends on the communication mode bit (C/A) and clock enable bits 1 IRQ2 and 0 (CKE1 and CKE0) in the SCI1 serial control register (SCR) as follows: C/A 0 CKE1 0 1 CKE0 0 1 0 1 Pin function See SCI1 SCI1 input below output 1 0 0 1 SCI1 output 1 0 1 SCI1 input
When C/A, CKE1, and CKE0 are all cleared to 0, usage depends on the IRQ2E and P82DDR bits as follows: IRQ2E P82DDR Pin function 0 0 P82 input 1 P82 output 0 IRQ2 input 1 1
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Table 9-13 Port 8 Pin Functions (cont)
Pin P81 / IRQ1 Selection of Pin Functions Usage depends on the IRQ1E and P81DDR bits as follows: IRQ1E P81DDR Pin function P80 / IRQ0 0 0 P81 input 1 P81 output 0 IRQ1 input 1 1
Usage depends on the IRQ0E and P80DDR bits as follows: IRQ0E P80DDR Pin function 0 0 P80 input 1 P80 output 0 IRQ0 input 1 1
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Section 10 16-Bit Free-Running Timers
10.1 Overview
The H8/510 has an on-chip 16-bit free-running timer (FRT) module with two independent channels (FRT1 and FRT2). Both channels are functionally identical. Each channel has a 16-bit free-running counter that it uses as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms per channel), input pulse width measurement, and measurement of external clock periods. 10.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counters can be driven by an internal clock source (o/4, o/8, or o/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each free-running timer channel can generate two independent waveforms. * Input capture function The current count can be captured on the rising or falling edge (selectable) of an input signal. * Four types of interrupts Compare-match A and B, input capture, and overflow interrupts can be requested independently. The compare-match and input capture interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A.
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10.1.2 Block Diagram Figure 10-1 shows a block diagram of one free-running timer channel.
External clock Internal clock o/4 o/8 FTCI o/32 Clock
Clock select
OCRA
Compare-match A FTOA FTOB FTI Overflow
Comparator A Bus interface Module data bus Internal data bus
FRC Clear Compare-match B Control logic Capture ICR OCRB Comparator B
TCSR
TCR ICI OCIA OCIB FOVI Interrupt signals OCRA: OCRB: FRC: ICR: TCSR: TCR: Output Compare Register A Output Compare Register B Free Running Counter Input Capture Register Timer Control/Status Register Timer Control Register
Figure 10-1 Block Diagram of 16-Bit Free-Running Timer
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10.1.3 Input and Output Pins Table 10-1 lists the input and output pins of the free-running timer module. Table 10-1 Input and Output Pins of Free-Running Timer Module
Channel Name 1 Output compare A Output compare B or counter clock input Input capture 2 Output compare A Output compare B or counter clock input Input capture Abbreviation FTOA1 FTOB1 / FTCI1 FTI1 FTOA2 FTOB2 / FTCI2 FTI2 I/O Output Output / Input Input Output Output / Input Input Function Output controlled by comparator A of FRT1 Output controlled by comparator B of FRT1 External clock source for FRT1 Trigger for capturing current count of FRT1 Output controlled by comparator A of FRT2 Output controlled by comparator B of FRT2 External clock source for FRT2 Trigger for capturing current count of FRT2
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10.1.4 Register Configuration Table 10-2 lists the registers of each free-running timer channel. Table 10-2 Register Configuration
Initial Value H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00
Channel 1
Name Abbreviation R/W Timer control register TCR R/W Timer control/status register TCSR R/(W)* Free-running counter (High) FRC (H) R/W Free-running counter (Low) FRC (L) R/W Output compare register A (High) OCRA (H) R/W Output compare register A (Low) OCRA (L) R/W Output compare register B (High) OCRB (H) R/W Output compare register B (Low) OCRB (L) R/W Input capture register (High) ICR (H) R Input capture register (Low) ICR (L) R 2 Timer control register TCR R/W Timer control/status register TCSR R/(W)* Free-running counter (High) FRC (H) R/W Free-running counter (Low) FRC (L) R/W Output compare register A (High) OCRA (H) R/W Output compare register A (Low) OCRA (L) R/W Output compare register B (High) OCRB (H) R/W Output compare register B (Low) OCRB (L) R/W Input capture register (High) ICR (H) R Input capture register (Low) ICR (L) R * Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits.
Address H'FEA0 H'FEA1 H'FEA2 H'FEA3 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEB0 H'FEB1 H'FEB2 H'FEB3 H'FEB4 H'FEB5 H'FEB6 H'FEB7 H'FEB8 H'FEB9
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10.2 Register Descriptions
10.2.1 Free-Running Counter (FRC)--H'FEA2, H'FEB2
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). The FRC can be cleared by compare-match A. When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written or read. See section 10.3, "CPU Interface," for details. The FRCs are initialized to H'0000 at a reset and in the standby modes.
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10.2.2 Output Compare Registers A and B (OCRA and OCRB)--H'FEA4 and H'FEA6, H'FEB4 and H'FEB6
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer control register (TCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in the timer control status register (TCSR) is output at the output compare pin (FTOA or FTOB). After a reset, the FTOA and FTOB outputs are 0 until the first compare-match. Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used when they are written. See section 10.3, "CPU Interface" for details. OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes. 10.2.3 Input Capture Register (ICR)--H'FEA8, H'FEB8
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 Read/Write R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
The ICR is a 16-bit read-only register. When the rising or falling edge of the signal at the input capture input pin is detected, the current value of the FRC is copied to the ICR. At the same time, the input capture flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bit (IEDG) in the TCSR. Because the ICR is a 16-bit register, a temporary register (TEMP) is used when the ICR is written or read. See section 10.3, "CPU Interface" for details.
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To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system clock periods (1.5*o).
o
FTI
Minimum FTI Pulse Width
The ICR is initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the ICR even if the input capture flag (ICF) is already set.
10.2.4 Timer Control Register (TCR)--H'FEA0, H'FEB0
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W 3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The TCR is an 8-bit readable/writable register that selects the FRC clock source, enables the output compare signals, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes. Bit 7--Input Capture Interrupt Enable (ICIE): This bit selects whether to request an input capture interrupt (ICI) when the input capture flag (ICF) in the timer control/status register (TCSR) is set to 1.
Bit 7 ICIE 0 1
Description The input capture interrupt request (ICI) is disabled. The input capture interrupt request (ICI) is enabled.
(Initial value)
Bit 6--Output Compare Interrupt Enable B (OCIEB): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer control/status register (TCSR) is set to 1.
157
Bit 6 OCIEB 0 1
Description Output compare interrupt request B (OCIB) is disabled. Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 5--Output Compare Interrupt Enable A (OCIEA): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer control/status register (TCSR) is set to 1.
Bit 5 OCIEA 0 1
Description Output compare interrupt request A (OCIA) is disabled. Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 4--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a freerunning timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer control/status register (TCSR) is set to 1.
Bit 4 OVIE 0 1
Description The free-running timer overflow interrupt request (FOVI) is disabled. The free-running timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 3--Output Enable B (OEB): This bit selects whether to enable or disable output of the logic level selected by the OLVLB bit in the timer control/status register (TCSR) at the output compare B pin when the FRC and OCRB values match.
Bit 3 OEB 0 1
Description Output compare B output is disabled. Output compare B output is enabled.
(Initial value)
Bit 2--Output Enable A (OEA): This bit selects whether to enable or disable output of the logic level selected by the OLVLA bit in the timer control/status register (TCSR) at the output compare A pin when the FRC and OCRA values match.
158
Bit 2 OEA 0 1
Description Output compare A output is disabled. Output compare A output is enabled.
(Initial value)
Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Internal clock source (o/4) (Initial value) 0 1 Internal clock source (o/8) 1 0 Internal clock source (o/32) 1 1 External clock source (counted on the rising edge)* * Output enable bit (bit 3) must be cleared to 0.
10.2.5 Timer Control/Status Register (TCSR)--H'FEA1, H'FEB1
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)* 3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W 0 CCLRA 0 R/W
The TCSR is an 8-bit readable and partially writable* register that selects the input capture edge and output compare levels, and specifies whether to clear the counter on compare-match A. It also contains four status flags. The TCSR is initialized to H'00 at a reset and in the standby modes. * Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits. Bit 7--Input Capture Flag (ICF): This status flag is set to 1 to indicate an input capture event. It signifies that the FRC value has been copied to the ICR.
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Bit 7 ICF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ICF bit after it has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves an input capture interrupt . This bit is set to 1 when an input capture signal causes the FRC value to be copied to the ICR.
Bit 6--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value.
Bit 6 OCFB 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the OCFB bit after it has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves output compare interrupt B. This bit is set to 1 when FRC = OCRB.
Bit 5--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value.
Bit 5 OCFA 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the OCFA bit after it has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) serves output compare interrupt A. This bit is set to 1 when FRC = OCRA.
Bit 4--Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes from H'FFFF to H'0000).
Bit 4 OVF 0 1
Description This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit after it has been set to 1, then writes a 0 in this bit. This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Bit 3--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match.
160
Bit 3 OLVLB 0 1
Description A 0 logic level (Low) is output for compare-match B. A 1 logic level (High) is output for compare-match B.
(Initial value)
Bit 2--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match.
Bit 2 OLVLA 0 1
Description A 0 logic level (Low) is output for compare-match A. A 1 logic level (High) is output for compare-match A.
(Initial value)
Bit 1--Input Edge Select (IEDG): This bit selects whether to capture the count on the rising or falling edge of the input capture signal.
Bit 1 IEDG 0 1
Description The FRC value is copied to the ICR on the falling edge of the input capture signal. The FRC value is copied to the ICR on the rising edge of the input capture signal.
(Initial value)
Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match).
Bit 0 CCLRA Description 0 The FRC is not cleared. 1 The FRC is cleared at compare-match A.
(Initial value)
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10.3 CPU Interface
The FRC, OCRA, OCRB, and ICR are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these four registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows. * Register Write When the CPU writes to the upper byte, the upper byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these four registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. Coding Examples : Write the contents of R0 into OCRA in FRT1 MOV.W R0, @H'FEAA : Read ICR of FRT2 MOV.W, @H'FEB8, R0 The same considerations apply to access by the DTC. Figure 10-2 shows the data flow when the FRC is accessed. The other registers are accessed in the same way, except that when OCRA or OCRB is read, the upper and lower bytes are both transferred directly to the CPU without using the temporary register.
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Upper byte write
Module data bus CPU writes data H'AA Bus interface
TEMP [H'AA]
FRC H [ ]
FRC L [ ]
Lower byte write
Module data bus CPU writes data H'55 Bus interface
TEMP [H'AA]
FRC H [H'AA]
FRC L [H'55]
Figure 10-2 (a) Write Access to FRC (When CPU Writes H'AA55)
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Upper byte read
Module data bus CPU writes data H'AA Bus interface
TEMP [H'55]
FRC H [H'AA]
FRC L [H'55]
Lower byte read
Module data bus CPU writes data H'55 Bus interface
TEMP [H'55]
FRC H [ ]
FRC L [ ]
Figure 10-2 (b) Read Access to FRC (When FRC Contains H'AA55)
10.4 Operation
10.4.1 FRC Incrementation Timing The FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. If external clock input is selected, the FRC increments on the rising edge of the clock signal. Figure 10-3 shows the increment timing.
164
The pulse width of the external clock signal must be at least 1.5*o clock periods. The counter will not increment correctly if the pulse width is shorter than 1.5*o clock periods.
o
FTCI
Minimum FTCI Pulse Width
o
External clock source
FRC clock pulse
FRC
N
N+1
Figure 10-3 Increment Timing for External Clock Input 10.4.2 Output Compare Timing Setting of Output Compare Flags A and B (OCFA and OCFB): The output compare flags are set to 1 by an internal compare-match signal generated10-3 the FRC value matches the OCRA or when Fig. OCRB value. This compare-match signal is generated at the last state in which the two values match, just before the FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 10-4 shows the timing of the setting of the output compare flags.
165
o
FRC
N
N+1
OCR
N
Internal comparematch signal
OCF
Figure 10-4 Setting of Output Compare Flags Output Timing: When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 10-5 shows the timing of this operation for compare-match A.
o
Internal comparematch A signal OLVLA
Output at comparematch A pin
Figure 10-5 Timing of Output Compare A
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FRC Clear Timing: If the CCLRA bit is set to 1, the FRC is cleared when compare-match A occurs. Figure 10-6 shows the timing of this operation.
o
Internal comparematch A signal
FRC
N
H'0000
Figure 10-6 Clearing of FRC by Compare-Match A 10.4.3 Input Capture Timing Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the input at the input capture pin (FTI), as selected by the IEDG bit in the TCSR. Figure 10-7 shows the usual input capture timing when the rising edge is selected (IEDG = 1).
o
Input at FTI pin
Internal input capture signal
Figure 10-7 Input Capture Timing (Usual Case) But if the upper byte of the ICR is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. Figure 10-8 shows the timing for this case.
167
Read cycle: CPU reads upper byte of ICR T1 T2 T3
o
Input at FTI pin
Internal input capture signal
Figure 10-8 Input Capture Timing (1-State Delay) Timing of Input Capture Flag (ICF) Setting: The input capture flag (ICF) is set to 1 by the internal input capture signal. Figure 10-9 shows the timing of this operation.
o
Internal input capture signal
ICF
FRC
N-1
N
N+1
ICR
N
Figure 10-9 Setting of Input Capture Flag
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10.4.4 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). Figure 10-10 shows the timing of this operation.
o
FRC
H'FFFF
H'0000
Internal overflow signal
OVF
Figure 10-10 Setting of Overflow Flag (OVF)
10.5 CPU Interrupts and DTC Interrupts
Each free-running timer channel can request four types of interrupts: input capture (ICI), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt is requested when the corresponding enable and flag bits are set. Independent signals are sent to the interrupt controller for each type of interrupt. Table 10-3 lists information about these interrupts. Table 10-3 Free-Running Timer Interrupts
Interrupt ICI OCIA OCIB FOVI Description Requested when ICF is set Requested when OCFA is set Requested when OCFB is set Requested when OVF is set DTC Service Available? Yes Yes Yes No Priority High
Low
The ICI, OCIA, and OCIB interrupts can be directed to the data transfer controller (DTC) to have a data transfer performed in place of the usual interrupt-handling routine. When the DTC serves one of these interrupts, it automatically clears the ICF, OCFA, or OCFB flag to 0. See section 6, Data Transfer Controller, for further information on the DTC.
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10.6 Synchronization of Free-Running Timers 1 and 2
10.6.1 Synchronization after a Reset The three free-running timer channels are synchronized at a reset and remained synchronized until: * the clock source is changed; * FRC contents are rewritten; or * an FRC is cleared. After a reset, each free-running counter operates on the o/4 internal clock source. 10.6.2 Synchronization by Writing to FRCs When synchronization of free-running timers 1 and 2 is lost, it can be restored by writing to the free-running counters. Synchronization on Internal Clock Source: When an internal clock is selected, free-running timers 1 and 2 can be synchronized by writing data to their free-running counters as indicated in table 10-4. Table 10-4 Synchronization by Writing to FRCs
Clock Source Write Interval Write Data o/4 4n (states) m (FRC1) o/8 8n (states) m+n (FRC2) o/32 32n (states) m, n: Arbitrary integers Note: When the FRC1 count is m + n, the same value must be written at the timing indicated in table 10-4.
After writing these data, synchronization can be checked by reading the free-running counters at the same interval as the write interval. If the read data have the same relative differences as the write data, the free-running timers are synchronized. Examples of synchronizing programs are shown next. Examples a, b, and c can be executed from a memory area accessed in two states via a 16-bit bus. Examples d, e, and f can be executed from a memory area accessed in three states via an 8-bit bus. These examples assume that no wait states (Tw) are inserted and no NMI input occurs.
170
Example a: o/4 clock source, 12-state write interval (n = 3), 16-bit bus, two-state-access memory LA: LDC.B #H'FE,BR ; Initialize base register for short-format instruction (MOV:S) LDC.W #H'0700,SR ; Raise interrupt mask level to 7 MOV.W #m,R1 ; Data for free-running timer 1 MOV.W #m+3,R2 ; Data for free-running timer 2 (m + n = m + 3) BSR SET4 ; Call write routine .ALIGN 2 SET4:MOV:S.W R1,@H'A2:8 BRN SET4:8 MOV:S.W R2,@H'B2:8 RTS ; Align write instructions (MOV:S) at even address ; Write to FRC 1 (address H'FEA2) 9 states ; 2-Byte dummy instruction 3 states ; Write to FRC 2 (address H'FEB2) Total 12 states
Example b: o/8 clock source, 16-state write interval (n = 2), 16-bit bus, two-state-access memory LB: LDC.B LDC.W MOV.W MOV.W BSR #H'FE,BR #H'0700,SR #m,R1 #m+2,R2 SET8
.ALIGN 2 SET8:MOV:S.W R1,@H'A2:8 BRN SET8:8 XCH R1,R1 MOV:S.W R2,@H'B2:8 RTS
; 9 States ; 3 States ; 4 States
Total 16 states
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Example c: o/32 clock source, 32-state write interval (n = 1), 16-bit bus, two-state-access memory LC: LDC.B #H'FE,BR LDC.W #H'0700,SR MOV.W #m,R1 MOV.W #m+1,R2 BSR SET32 .ALIGN 2 SET32: MOV:S.W R1,@H'A2:8 BSR WAIT:8 MOV:S.W R2,@H'B2:8 RTS .ALIGN 2 NOP XCH R1,R1 RTS ; Align on even address ; 2 Bytes, 9 states ; 2 Bytes, 9 states Total 32 states ; Align on even address ; 2 States ; 4 States ; 8 States
WAIT:
Note: The stack is assumed to be in a memory area accessed in two states via a 16-bit bus. Example d: o/4 clock source, 20-state write interval (n = 5), 8-bit bus, three-state-access memory LD: LDC.B #H'FE,BR LDC.W #H'0700,SR ; Set interrupt mask level to 7 CLR.B @H'F8:8 ; Disable wait states MOV.W #m,R1 MOV.W #m+5,R2 MOV:S.W R1,@H'A2:8 ; 13 States Total 20 states BRN LD:8 ; 2 Bytes, 7 states MOV:S.W R2,@H'B2:8
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Example e: o/8 clock source, 24-state write interval (n = 3), 8-bit bus, three-state-access memory LE: LDC.B #H'FE,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+3,R2 MOV:S.W R1,@H'A2:8 ; 13 States BRN LE:8 ; 2 Bytes, 7 states Total 24 states NOP ; 1 Byte, 4 states MOV:S.W R2,@H'B2:8 Example f: o/32 clock source, 32-state write interval (n = 1), 8-bit bus, three-state-access memory LF: LDC.B #H'FE,BR LDC.W #H'0700,SR CLR.B @H'F8:8 MOV.W #m,R1 MOV.W #m+1,R2 MOV:S.W R1,@H'A2:8 ; 13 states XCH R0,R0 ; 8 states Total 32 states BRN LF:8 ; 2 Bytes, 7 states NOP ; 4 states MOV:S.W R2,@H'B2:8
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Synchronization on External Clock Source: When the external clock source is selected, the free-running timers can be synchronized by halting their external clock inputs, then writing identical values in their free-running counters.
10.7 Sample Application
In the example below, one free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in the TCSR is set to 1. 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in the TCSR.
FRC Clear counter
H'FFFF OCRA OCRB H'0000
FTOA pin
FTOB pin
Figure 10-11 Square-Wave Output (Example)
10.8 Application Notes
Application programmers should note that the following types of contention can occur in the freerunning timers. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the clear signal takes priority and the write is not performed.
174
Figure 10-12 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clear signal
FRC
N
H'0000
Figure 10-12 FRC Write-Clear Contention Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and the FRC is not incremented.
175
Figure 10-13 shows this type of contention.
Write cycle: CPU write to lower byte of FRC T1 T2 T3
o
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M
Write data
Figure 10-13 FRC Write-Increment Contention
176
Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and the compare-match signal is inhibited. Figure 10-14 shows this type of contention.
Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3
o
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
N
M Write data
Compare-match A or B signal Inhibited
Figure 10-14 Contention between OCR Write and Compare-Match Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 10-5. The pulse that increments the FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 10-5, the changeover generates a falling edge that triggers the FRC increment pulse. Switching between an internal and external clock source can also cause the FRC to increment.
177
Table 10-5 Effect of Changing Internal Clock Sources
No. 1 Description Low Low: CKS1 and CKS0 are rewritten while both clock sources are Low. Timing Chart
Old clock source
New clock source FRC clock pulse
FRC
N CKS rewrite
N+1
2
Low High: CKS1 and CKS0 are rewritten while old clock source is Low and new clock source is High.
Old clock source
New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
3
High Low: CKS1 and CKS0 are rewritten while old clock source is High and new clock source is Low.
Old clock source
New clock source * FRC clock pulse
FRC
N
N+1 CKS rewrite
N+2
The switching of clock sources is regarded as a falling edge that increments the FRC.
178
Table 10-5 Effect of Changing Internal Clock Sources (cont)
No. 4 Description High High: CKS1 and CKS0 are rewritten while both clock sources are High. Timing Chart
Old clock source
New clock source FRC clock pulse
FRC
N
N+1
N+2 CKS rewrite
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Section 11 8-Bit Timer
11.1 Overview
The H8/510 chip includes a single 8-bit timer based on an 8-bit counter (TCNT). The timer has two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One application of the 8-bit timer is to generate a rectangular-wave output with an arbitrary duty factor. 11.1.1 Features The features of the 8-bit timer are listed below. * Selection of four clock sources The counter can be driven by an internal clock signal (o/8, o/64, or o/1024) or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counter The counter can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two time constants The single timer output (TMO) is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. * Three types of interrupts Compare-match A and B and overflow interrupts can be requested independently. The compare match interrupts can be served by the data transfer controller (DTC), enabling interrupt-driven data transfer with minimal CPU programming.
181
11.1.2 Block Diagram Figure 11-1 shows a block diagram of 8-bit timer.
External clocks Internal clocks o/8 o/64 TMCI o/1024 Clock
Clock select
TCORA
Compare-match A TMO TMRI Clear Overflow
Comparator A Bus interface Module data bus Internal data bus
TCNT
Control logic
Compare-match B
Comparator B
TCORB
TCSR
TCR CMIA CMIB OVI Interrupt signals TCORA: TCORB: TCNT: TCSR: TCR: Time Constant Register A Time Constant Register B Timer Counter Timer Control/Status Register Timer Control Register
Figure 11-1 Block Diagram of 8-Bit Timer
182
11.1.3 Input and Output Pins Table 11-1 lists the input and output pins of the 8-bit timer. Table 11-1 Input and Output Pins of 8-Bit Timer
Name Timer output Timer clock input Timer reset input Abbreviation TMO TMCI TMRI I/O Output Input Input Function Output controlled by compare-match External clock source for the counter External reset signal for the counter
11.1.4 Register Configuration Table 11-2 lists the registers of the 8-bit timer. Table 11-2 8-Bit Timer Registers
Name Abbreviation R/W Initial Value Address Timer control register TCR R/W H'00 H'FEC0 Timer control/status register TCSR R/(W)* H'10 H'FEC1 Timer constant register A TCORA R/W H'FF H'FEC2 Timer constant register B TCORB R/W H'FF H'FEC3 Timer counter TCNT R/W H'00 H'FEC4 * Software can write a "0" to clear bits 7 to 5, but cannot write a "1" in these bits.
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)--H'FEC4
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from one of four clock sources. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter.
183
The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counter is initialized to H'00 at a reset and in the standby modes. 11.2.2 Time Constant Registers A and B (TCORA and TCORB)--H'FEC2 and H'FEC3
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers. When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal (TMO) is controlled by these compare-match signals as specified by output select bits 1 to 0 (OS1 to OS0) in the timer status/control register (TCSR). TCORA and TCORB are initialized to H'FF at a reset and in the standby modes. 11.2.3 Timer Control Register (TCR)--H'FEC0
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
The TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. The TCR is initialized to H'00 at a reset and in the standby modes.
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Bit 7--Compare-Match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status register (TCSR) is set to 1.
Bit 7 CMIEB 0 1
Description Compare-match interrupt request B (CMIB) is disabled. Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
Bit 6--Compare-Match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer control/status register (TCSR) is set to 1.
Bit 6 CMIEA 0 1
Description Compare-match interrupt request A (CMIA) is disabled. Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1.
Bit 5 OVIE 0 1
Description The timer overflow interrupt request (OVI) is disabled. The timer overflow interrupt request (OVI) is enabled.
(Initial value)
Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input.
Bit 4 CCLR1 0 0 1 1 Bit 3 CCLR0 0 1 0 1
Description Not cleared. (Initial value) Cleared on compare-match A. Cleared on compare-match B. Cleared on rising edge of external reset input signal.
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Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select the internal or external clock source for the timer counter. For the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges.
Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1
Description No clock source (timer stopped). (Initial value) Internal clock source (o/8). Internal clock source (o/64). Internal clock source (o/1024). No clock source (timer stopped). External clock source, counted on the rising edge. External clock source, counted on the falling edge. External clock source, counted on both the rising and falling edges.
11.2.4 Timer Control/Status Register (TCSR)--H'FEC1
Bit 7 CMFB Initial value Read/Write 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
The TCSR is an 8-bit readable and partially writable* register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal (TMO). The TCSR is initialized to H'10 at a reset and in the standby modes. * Software can write a "0" in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB.
186
Bit 7 CMFB 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the CMFB bit after it has been set to 1, then writes a 0 in this bit. 2. Compare-match interrupt B is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORB.
Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA.
Bit 6 CMFA 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the CMFA bit after it has been set to 1, then writes a 0 in this bit. 2. Compare-match interrupt A is served by the data transfer controller (DTC). This bit is set to 1 when TCNT = TCORA.
Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00).
Bit 5 OVF 0 1
Description This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit after it has been set to 1, then writes a 0 in this bit. This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4 --Reserved: This bit cannot be modified and is always read as 1. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. When all four output select bits are cleared to 0 the TMO signal is not output. The TMO output is 0 before the first compare-match.
Bit 3 OS3 0 0 1 1 Bit 2 OS2 0 1 0 1
Description No change when compare-match B occurs. (Initial value) Output changes to 0 when compare-match B occurs. Output changes to 1 when compare-match B occurs. Output inverts (toggles) when compare-match B occurs.
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Bit 1 OS1 0 0 1 1
Bit 0 OS0 0 1 0 1
Description No change when compare-match A occurs. (Initial value) Output changes to 0 when compare-match A occurs. Output changes to 1 when compare-match A occurs. Output inverts (toggles) when compare-match A occurs.
11.3 Operation
11.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. The external clock pulse width must be at least 1.5*o clock periods for incrementation on a single edge, and at least 2.5*o clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values. Figure 11-2 shows the count timing for the case of incrementation on both edges of an external clock input.
o
External clock source
TCNT clock pulse
TCNT
N-1
N
N+1
Figure 11-2 Count Timing for External Clock Input
188
11.3.2 Compare Match Timing Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 11-3 shows the timing of the setting of the compare-match flags.
o
TCNT
N
N+1
TCOR
N
Internal compare-match signal
CMF
Figure 11-3 Setting of Compare-Match Flags
189
Output Timing: When a compare-match event occurs, the timer output (TMO) changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 11-4 shows the timing when the output is set to toggle on compare-match A.
o
Internal compare-match A signal Timer output (TMO)
Figure 11-4 Timing of Timer Output Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 11-5 shows the timing of this operation.
o
Internal compare-match signal
TCNT
N
H'00
Figure 11-5 Timing of Compare-Match Clear 11.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in the TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 11-6 shows the timing of this operation.
190
o
External reset input (TMRI)
Internal clear pulse
TCNT
N-1
N
H'00
Figure 11-6 Timing of External Reset 11.3.4 Setting of TCNT Overflow Flag The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 11-7 shows the timing of this operation.
o
TCNT
H'FF
H'00
Internal overflow signal
OVF
Figure 11-7 Setting of Overflow Flag (OVF)
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11.4 CPU Interrupts and DTC Interrupts
The 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt is requested when the corresponding enable and flag bits are set in the TCR and TCSR. Independent signals are sent to the interrupt controller for each type of interrupt. Table 11-3 lists information about these interrupts. Table 11-3 8-Bit Timer Interrupts
Interrupt CMIA CMIB OVI Description Requested when CMFA is set Requested when CMFB is set Requested when OVF is set DTC Service Available? Yes Yes No Priority High Low
The CMIA and CMIB interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it automatically clears the CMFA or CMFB flag to 0. See section 6, "Data Transfer Controller," for further information on the DTC.
192
11.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. The control bits are set as follows: 1. In the TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. 2. In the TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on comparematch A and to 0 on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required.
H'FF TCORA TCORB H'00
TCNT Clear counter
TMO pin
Figure 11-8 Example of Pulse Output
193
11.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit timer. Contention between TCNT Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 11-9 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal address bus
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 11-9 TCNT Write-Clear Contention
194
Contention between TCNT Write and Increment: If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 11-10 shows this type of contention.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Internal address bus
TCNT address
Internal write signal
TCNT clock pulse
TCNT
N
M Write data
Figure 11-10 TCNT Write-Increment Contention
195
Contention between TCOR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the comparematch signal is inhibited. Figure 11-11 shows this type of contention.
Write cycle: CPU writes to TCORA or TCORB T1 T2 T3
o
Internal address bus
TCOR address
Internal write signal
TCNT
N
N+1
TCORA or TCORB
N
M TCOR write data
Compare-match A or B signal Inhibited
Figure 11-11 Contention between TCOR Write and Compare-Match Contention between Compare-Match A and Compare-Match B: If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 11-4.
196
Table 11-4 Priority Order of Timer Output
Output Selection Toggle 1 Output 0 Output No change Priority High
Low
Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS2 to CKS0) are rewritten, as shown in table 11-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is High and the new source is Low, as in case No. 3 in table 11-5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. Table 11-5 Effect of Changing Internal Clock Sources
No. 1 Description Low Low*1: CKS1 and CKS0 are rewritten while both clock sources are Low. Timing Chart
Old clock source
New clock source
TCNT clock pulse
TCNT
N CKS rewrite
N+1
Note: *1 Including a transition from Low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to Low.
197
Table 11-5 Effect of Changing Internal Clock Sources (cont)
No. 2 Description Timing Chart *1: Low High Old clock CKS1 and CKS0 are source rewritten while old clock source is Low and New clock new clock source is High. source
TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
3
High Low*2: CKS1 and CKS0 are rewritten while old clock source is High and new clock source is Low.
Old clock source
New clock source *3 TCNT clock pulse
TCNT
N
N+1 CKS rewrite
N+2
Notes: *1 Including a transition from the stopped state to High. *2 Including a transition from High to the stopped state. *3 The switching of clock sources is regarded as a falling edge that increments the TCNT.
198
Table 11-5 Effect of Changing Internal Clock Sources (cont)
No. 4 Description High High: CKS1 and CKS0 are rewritten while both clock sources are High. Timing Chart
Old clock source
New clock source
TCNT clock pulse
TCNT
N
N+1
N+2 CKS rewrite
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Section 12 Refresh Controller
12.1 Overview
To simplify interfacing to dynamic RAM, the H8/510 has an on-chip refresh control circuit. Insertion of refresh cycles can be inhibited in systems not using dynamic RAM. 12.1.1 Features The refresh controller has the following features: * Programmable refresh interval Eight refresh intervals can be selected (from 32 to 256 states) * 12-Bit refresh addresses * Refresh cycle length: 2 to 5 states (selectable) * Precharge states (TP) can be inserted 12.1.2 Block Diagram Figure 12-1 is a block diagram of the refresh controller.
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Refresh control register (RFSHCR) RFSHE ASWC ARFSH RWC1 RWC0 CYC2 CYC1 CYC0
TP insert Interval counter
o
RFSH output Control circuit
Refresh address counter
Address bus
Figure 12-1 Refresh Controller Block Diagram 12.1.3 Register Configuration The refresh controller has one control register, described in table 12-1. Table 12-1 Refresh Control Register
Name Refresh control register Abbreviation RFSHCR Read/Write R/W Initial Value H'D8 Address H'FED8
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12.2 Refresh Control Register (RFSHCR)--H'FED8
Bit 7 RFSHE Initial value Read/Write 1 R/W 6 ASWC 1 R/W 5 ARFSH 0 R/W 4 RWC1 1 R/W 3 RWC0 1 R/W 2 CYC2 0 R/W 1 CYC1 0 R/W 0 CYC0 0 R/W
The refresh control register (RFSHCR) is an 8-bit register that controls the operating modes of the refresh controller. The refresh control register is initialized to H'D8 at a reset and in the hardware standby mode. It is not initialized in the software standby mode. Bit 7--Refresh Enable (RFSHE): Specifies whether or not to insert refresh cycles.
Bit 7 RFSHE 0 1
Description Refresh cycles are not inserted. Refresh cycles are inserted.
(Initial value)
Bit 6--As Wait Control (ASWC): Specifies whether or not to insert a precharge (TP) state immediately before the T1 state of a three-state-access bus cycle.
Bit 6 ASWC 0 1
Description No TP state is inserted. TP state is inserted.
(Initial value)
Bit 5--Auto-Refresh (ARFSH): Specifies whether or not to generate an auto-refresh pulse for pseudo-static RAM.
Bit 5 ARFSH Description 0 RD is always 1 during refresh cycles. 1 RD is output as an auto-refresh pulse for pseudo-static RAM.
(Initial value)
203
Bits 4 and 3--Refresh Wait Cycle (RWC1 and RWC0): Specify the number of wait states inserted in a refresh bus cycle.
Bit 4 RWC1 0 0 1 1 Bit 3 RWC0 0 1 0 1 Description Wait States Refresh States 0 2 1 3 2 4 3 5
(Initial value)
Bits 2 to 0--Refresh Cycle 2 to 0 (CYC2 to CYC0):
Refresh Request Interval (States) 32 64 96 128 160 192 224 256 Time Interval (Examples) for Typical Frequencies of System Clock (o) 10 MHz 8 MHz 6 MHz 3.2 s 4.0 s 5.3 s 6.4 s 8.0 s 10.6 s 9.6 s 12.0 s 16.0 s 12.8 s 16.0 s 21.3 s 16.0 s 20.0 s 26.6 s 19.2 s 24.0 s 32.0 s 22.4 s 28.0 s 37.3 s 25.6 s 32.0 s 42.6 s
Bit 2 CYC2 0 0 0 0 1 1 1 1
Bit 1 CYC1 0 0 1 1 0 0 1 1
Bit 0 CYC0 0 1 0 1 0 1 0 1
(Initial value)
Dynamic RAM that requires 128 refresh cycles over a 2-ms period (or 256 refresh cycles over a 4-ms period) has a refresh interval of: 2 ms/128 = 4 ms/256 = 15.625 s If the H8/510 is operating at 10 MHz, the refresh cycle can be set to 128 states (12.8 s). Refresh cycles are inserted at the ends of other bus cycles, so the actual interval between refresh cycles may differ slightly from the interval selected with CYC2 to CYC0. When wait states are inserted, the interval may also differ for the same reason.
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12.3 Operation
The refresh controller sends the CPU a refresh request signal at fixed intervals. When it receives this signal, the CPU waits for the end of the current bus cycle, then executes a refresh cycle. Figure 12-2 shows an example of the timing of a refresh cycle. During a refresh cycle the RFSH signal goes Low to identify the cycle as a refresh cycle, and a refresh address is output. The number of bits in the refresh address varies depending on the MCU mode as shown in table 12-2. The refresh operation is not executed while the bus is released, or during wait states.
CPU cycle T3 o TR1 Refresh cycle TRW* TR2 CPU cycle T1
Address
AS
RFSH
RD (ARFSH="0")
RD (ARFSH="1")
* In this example the RWC1 and RWC0 bits specify insertion of one wait state in the refresh cycle.
Figure 12-2 Refresh Timing Table 12-2 MCU Modes and Refresh Addresses
MCU Mode Modes 1 and 3 (8-bit bus) Modes 2 and 4 (16-bit bus) Refresh Address Output on A0 to A11; A12 to A23 are all 0 Output on A1 to A12; A0 and A13 to A23 are all 0
205
If the ARFSH bit in the refresh control register (RFSHCR) is set to 1, a pseudo-static RAM autorefresh cycle is executed. In the auto-refresh cycle, the RFSH signal sits Low while a Low pulse is output on the RD signal line. Refresh addresses are output even though they are not needed in an auto-refresh. 12.3.1 Wait State Insertion One or more TRW states can be inserted in a refresh cycle before the TR2 state, depending on the RWC1 and RWC0 bits. TRW states can also be inserted by WAIT input. When the WMS1 bit in the wait control register (WCR) is set to 1, if one or more programmable wait states are inserted by RWC1 and RWC0, the WAIT signal is sampled on the falling edge of the state before TR2. If the WAIT signal is Low at this time, a TRW state is inserted. The WAIT signal is sampled again on the falling edge of each TRW state. Figure 12-3 shows the timing.
Refresh cycle TR1 o TRW *1 TRW *2 TR2 CPU cycle T1
Address
AS
RFSH
WAIT
Notes: * 1 Programmable wait state * 2 Wait state inserted by WAIT
Figure 12-3 Insertion of Wait State by WAIT
206
12.3.2 TP Insertion A TP state can be inserted to satisfy the RAS precharge requirements of dynamic RAM. When the ASWC bit in the refresh control register (RFSHCR) is set to 1, a TP state is inserted before the T1 state in CPU bus cycles and before the TR1 state in refresh bus cycles. Figure 12-4 shows the insertion of a TP state in a refresh bus cycle.
CPU cycle T3 o TP Auto refresh cycle TR1 TRW TR2
Address
AS
RFSH * RD
* When ARFSH=0, RD remains High.
Figure 12-4 Refresh Timing when TP States are Inserted (Three-State Refresh)
207
TP state can be inserted in three-state-access bus cycles and in refresh cycles with three states or more. They cannot be inserted in two-state-access bus cycles and two-state refresh cycles. Figure 12-5 shows the insertion of a TP state in a CPU bus cycle.
Read cycle TP o T1 T2 T3 TP
Write cycle T1 T2 T3
Address
AS
RD
LWR, HWR
Figure 12-5 CUP Bus Cycle Timing when TP States are Inserted
208
12.4 Operation in Power-Down State
The refresh controller continues to operate in sleep mode. The refresh controller halts in the standby modes. In software standby mode the refresh control register (RFSHCR) is not initialized; it retains the values set before the standby began. If the chip recovers from software standby mode by an NMI interrupt, however, the refresh address is modified unpredictably.
12.5 Operation in Reset State
The refresh controller halts during the reset state. The refresh control register (RFSHCR) is initialized to H'D8 (enabling refresh operations). The refresh address is initialized to H'000.
12.6 Application Notes
The following points require attention when the refresh controller is used. 1. Refresh cycles are not executed when the CPU released the bus, in the software standby mode, in the hardware standby mode, and during wait states. If any of these conditions continues for a long time, memory must be refreshed by other means. 2. If refresh requests are generated internally while the bus is released, one request is held pending, causing one refresh cycle to be executed after the CPU regains control of the bus. Figure 12-6 shows an example of bus cycles in this case. 3. If a refresh request is generated internally during a wait state, the request is held until the next refresh request is generated, and a refresh cycle is executed at the first opportunity after the wait state is released. 4. If refresh cycles are not executed for a long time because the chip is in the bus-released state or a long wait state, when this state ends the refresh address output in the next refresh cycle is still the next refresh address after the preceding refresh address.
209
Bus-released state
Refresh cycle TR1 TR2
CPU cycle T1 T2
Refresh cycle
o
RFSH Request is held pending Refresh request (internal signal)
BACK
Figure 12-6 Refresh Request Generated while Bus is Released
210
Section 13 Serial Communication Interface
13.1 Overview
The H8/510 chip includes two serial communication interface channels (SCI1 and SCI2) for transferring serial data to and from other chips. Both channels are identical. Each channel supports both synchronous and asynchronous data transfer. Communication control functions are provided by eight internal registers. 13.1.1 Features The features of the on-chip serial communication interface channels are: * Selection of asynchronous or synchronous mode -- Asynchronous mode The H8/510 can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. Eight data formats are available. -- Data length: 7 or 8 bits -- Stop bit length: 1 or 2 bits -- Parity: Even, odd, or none -- Error detection: Parity, overrun, and framing errors -- Synchronous mode The H8/510 can communicate with chips able to synchronize data transfers with clock pulses. -- Data length: 8 bits -- Error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so each SCI can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. * Built-in baud rate generator Any specified bit rate can be generated. * Internal or external clock source The baud rate generator can operate on an internal clock source, or an external clock signal input at the SCK pin. * Three interrupts Transmit-end, receive-end, and receive-error interrupts are requested independently. The transmit-end and receive-end interrupts can be served by the on-chip data transfer controller (DTC), providing a convenient way to transfer data with minimal CPU programming.
211
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the serial communication interface for one channel.
Bus interface SSR SCR SMR BRR Baud-rate generator Clock TXI RXI ERI
Module data bus
Internal data bus
RDR
TDR
Internal clock source o o/4 o/16 o/64
RXD TXD
RSR
TSR Communication control Parity generator Parity check
External clock
SCK
RDR: Receive Data Register RSR: Receive Shift Register TDR: Transmit Data Register TSR: Transmit Shift Register SSR: Serial Status Register SCR: Serial Control Register SMR: Serial Mode Register BRR: Bit Rate Register
Interrupt signals
Figure 13-1 Block Diagram of Serial Communication Interface
212
13.1.3 Input and Output Pins Table 13-1 lists the input and output pins used by each SCI channel. Table 13-1 SCI Input/Output Pins
Name Serial clock Receive data Transmit data Abbreviation SCK RXD TXD I/O Input/output Input Output Function Serial clock input and output Receive data input Transmit data output
13.1.4 Register Configuration Table 13-2 lists the SCI registers. Table 13-2 SCI Registers
Name Abbreviation R/W Initial Value Receive shift register RSR -- -- Receive data register RDR R H'00 Transmit shift register TSR -- -- Transmit data register TDR R/W H'FF Serial mode register SMR R/W H'04 Serial control register SCR R/W H'0C Serial status register SSR R/(W)* H'87 Bit rate register BRR R/W H'FF 2 Receive shift register RSR -- -- Receive data register RDR R H'00 Transmit shift register TSR -- -- Transmit data register TDR R/W H'FF Serial mode register SMR R/W H'04 Serial control register SCR R/W H'0C Serial status register SSR R/(W)* H'87 Bit rate register BRR R/W H'FF * Software can write a 0 to clear the status flag bits, but cannot write a 1. Channel 1 Address -- H'FECD -- H'FECB H'FEC8 H'FECA H'FECC H'FEC9 -- H'FED5 -- H'FED3 H'FED0 H'FED2 H'FED4 H'FED1
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13.2 Register Descriptions
13.2.1 Receive Shift Register (RSR)
Bit 7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
The RSR receives incoming data bits. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write the RSR directly. 13.2.2 Receive Data Register (RDR)--H'FECD and H'FED5
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
The RDR stores received data. As each character is received, it is transferred from the RSR to the RDR, enabling the RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. The CPU can read but not write the RDR. The RDR is initialized to H'00 at a reset and in the standby modes. 13.2.3 Transmit Shift Register (TSR)
Bit 7 6 5 4 3 2 1 0
Read/Write
--
--
--
--
--
--
--
--
The TSR holds the character currently being transmitted. When transmission of this character is completed, the next character is moved from the transmit data register (TDR) to the TSR and transmission of that character begins. If the TDR does not contain valid data, the SCI stops transmitting. The CPU cannot read or write the TSR directly.
214
13.2.4 Transmit Data Register (TDR)--H'FECB and H'FED3
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted. When the TSR becomes empty, the character written in the TDR is transferred to the TSR. Continuous data transmission is possible by writing the next byte in the TDR while the current byte is being transmitted from the TSR. The TDR is initialized to H'FF at a reset and in the standby modes. 13.2.5 Serial Mode Register (SMR)--H'FEC8 and H'FED0
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 -- 1 -- 1 CKS1 0 R/W 0 CKS0 0 R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. It is initialized to H'04 at a reset and in the standby modes. Bit 7--Communication Mode (C/A): This bit selects the asynchronous or synchronous communication mode.
Bit 7 C/A 0 1
Description Asynchronous communication. (Initial value) Communication is synchronized with the serial clock.
Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode.
Bit 6 CHR 0 1
Description 8 Bits per character. 7 Bits per character.
(Initial value)
215
Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode.
Bit 5 PE 0 1
Description Transmit: No parity bit is added. Receive: Parity is not checked. Transmit: A parity bit is added. Receive: Parity is checked.
(Initial value)
Bit 4--Parity Mode (O/E): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0 and in the synchronous mode.
Bit 4 O/E 0 1
Description Even parity. Odd parity.
(Initial value)
Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in the synchronous mode.
Bit 3 STOP 0 1
Description 1 Stop bit. 2 Stop bits.
(Initial value)
Bit 2--Reserved: This bit cannot be modified and is always read as 1.
216
Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock source when the baud rate generator is clocked from within the H8/510 chip.
Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1
Description o clock o/4 clock o/16 clock o/64 clock
(Initial value)
13.2.6 Serial Control Register (SCR)--H'FECA and H'FED2
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 -- 1 -- 2 -- 1 -- 1 CKE1 0 R/W 0 CKE0 0 R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'0C at a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1.
Bit 7 TIE 0 1
Description The transmit-end interrupt request (TXI) is disabled. The transmit-end interrupt request (TXI) is enabled.
(Initial value)
Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1. It also enables and disables the receive-error interrupt (ERI) request.
Bit 6 RIE 0 1
Description The receive-end interrupt (RXI) and receive-error interrupt (ERI) (Initial value) requests are disabled. The receive-end interrupt (RXI) and receive-error interrupt (ERI) requests are enabled.
217
Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TXD pin is automatically used for output. When the transmit function is disabled, the TXD pin can be used as a general-purpose I/O port.
Bit 5 TE 0 1
Description The transmit function is disabled. The TXD pin can be used as a general-purpose I/O port. The transmit function is enabled. The TXD pin is used for output.
(Initial value)
Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RXD pin is automatically used for input. When the receive function is disabled, the RXD pin is available as a general-purpose I/O port.
Bit 4 RE 0 1
Description The receive function is disabled. The RXD pin can be used as a general-purpose I/O port. The receive function is enabled. The RXD pin is used for input.
(Initial value)
Bits 3 and 2--Reserved: These bits cannot be modified and are always read as 1. Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal.
Bit 1 CKE1 0 1
Description Internal clock source. External clock source. (The SCK pin is used for input.)
(Initial value)
Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in synchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when the asynchronous mode is selected. For further information on the communication format and clock source selection, see tables 13-5 and 13-6 in section 13.3, "Operation."
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Bit 0 CKE0 0 1
Description The SCK pin is not used by the SCI (and is available as a general-purpose I/O port). The SCK pin is used for serial clock output.
(Initial value)
13.2.7 Serial Status Register (SSR)--H'FECC and H'FED4
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
* Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'87 at a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7 TDRE 0
1
Description This bit is cleared from 1 to 0 when: 1. The CPU reads the TDRE bit after it has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) writes data in the TDR. This bit is set to 1 at the following times: (Initial value) 1. The chip is reset or enters a standby mode. 2. When TDR contents are transferred to the TSR. 3. When TDRE = 0 and the TE bit is cleared to 0.
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Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to the RDR.
Bit 6 RDRF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the RDRF bit after it has been set to 1, then writes a 0 in this bit. 2. The data transfer controller (DTC) reads the RDR. 3. The chip is reset or enters a standby mode. This bit is set to 1 when one character is received without error and transferred from the RSR to the RDR.
Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5 ORER 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the ORER bit after it has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1).
Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in the synchronous mode. It has no meaning in the asynchronous mode.
Bit 4 FER 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the FER bit after it has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 if a framing error occurs (stop bit = 0).
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Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used.
Bit 3 PER 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The CPU reads the PER bit after it has been set to 1, then writes a 0 in this bit. 2. The chip is reset or enters a standby mode. This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the bit in the SMR).
Bits 2 to 0--Reserved: These bits cannot be modified and are always read as 1.
13.2.8 Bit Rate Register (BRR)--H'FEC9 and H'FED1
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines the bit rate output by the baud rate generator. The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes. Tables 13-3 and 13-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
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Table 13-3 Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz) 2.4576 4 Error N (%) n N 86 +0.31 1 141 255 0 1 103 127 0 0 207 63 0 0 103 31 0 0 51 15 0 0 25 7 0 0 12 3 0 ---- 1 0 ---- -- -- 0 1 0 0 ----
2 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 -- -- -- -- -- N 70 207 103 51 25 12 -- -- -- -- -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- -- -- -- n 1 0 0 0 0 0 0 0 0 -- 0
Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 --
n 1 1 0 0 0 0 0 -- -- -- --
4.194304 Error N (%) 148 -0.04 108 +0.21 217 +0.21 108 +0.21 54 -0.70 26 +1.14 13 -2.48 -- -- -- -- -- -- -- --
Table 13-3 Examples of BRR Settings in Asynchronous Mode (2)
XTAL Frequency (MHz) 6 7.3728 Error Error N (%) n N (%) 52 +0.50 2 64 +0.70 155 +0.16 1 191 0 77 +0.16 1 95 0 155 +0.16 0 191 0 77 +0.16 0 95 0 38 +0.16 0 47 0 19 -2.34 0 23 0 -- -- 0 11 0 -- -- 0 5 0 2 0 ---- -- -- -- 0 2 0
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 1 1 0 0 0 0 0 0 0 -- 0
4.9152 Error N (%) 174 -0.26 127 0 255 0 127 0 63 0 31 0 15 0 7 0 3 0 -- -- 1 0
8 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 --
n 2 1 1 0 0 0 0 -- -- 0 --
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Table 13-3 Examples of BRR Settings in Asynchronous Mode (3)
XTAL Frequency (MHz) 10 12 Error N (%) n N 88 -0.25 2 106 64 +0.16 2 77 129 +0.16 1 155 64 +0.16 1 77 129 +0.16 0 155 64 +0.16 0 77 32 -1.36 0 38 15 +1.73 0 19 7 +1.73 ---- 4 0 0 5 3 +1.73 ----
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 2 1 1 0 0 0 0 0 0 0 0
9.8304 Error N (%) 86 +0.31 255 0 127 0 255 0 127 0 63 0 31 0 15 0 7 0 4 -1.70 3 0
n 2 2 1 1 0 0 0 0 0 0 0
Error (%) -0.44 0 0 0 +0.16 +0.16 +0.16 -2.34 -- 0 --
n 2 2 1 1 0 0 0 0 0 0 0
12.288 Error N (%) 108 +0.08 79 0 159 0 79 0 159 0 79 0 39 0 19 0 9 0 5 +2.40 4 0
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Table 13-3 Examples of BRR Settings in Asynchronous Mode (4)
XTAL Frequency (MHz) 16 19.6608 Error Error N (%) n N (%) 141 +0.03 2 174 -0.26 103 +0.16 2 127 0 207 +0.16 1 255 0 103 +0.16 1 127 0 207 +0.16 0 255 0 103 +0.16 0 127 0 51 +0.16 0 63 0 25 +0.16 0 31 0 12 +0.16 0 15 0 7 0 0 9 -1.70 -- -- 0 7 0
Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400
n 2 2 1 1 0 0 0 0 0 -- 0
14.7456 Error N (%) 130 -0.07 95 0 191 0 95 0 191 0 95 0 47 0 23 0 11 0 -- -- 5 0
20 n 3 2 2 1 1 0 0 0 0 0 0 N 43 129 64 129 64 129 64 32 15 9 7 Error (%) +0.88 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 0 +1.73
n 2 2 1 1 0 0 0 0 0 0 --
B = OSC x 106/[64 x 22n x (N + 1)] B: N: OSC : n: Bit rate BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o o/4 o/16 o/64
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Table 13-4 Examples of BRR Settings in Synchronous Mode
XTAL Frequency (MHz) 8 10 n N n N -- -- -- -- 2 249 -- -- 2 124 -- -- 1 249 -- -- 1 99 1 124 0 199 0 249 0 99 0 124 0 39 0 49 0 19 0 24 0 9 -- -- 0 3 0 4 0 1 -- -- 0 0 -- --
Bit Rate 100 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M
2 n -- 1 1 0 0 0 0 0 0 -- 0 N -- 249 124 249 99 49 24 9 4 -- 0 n -- 2 1 1 0 0 0 0 0 0 0 0
4 N -- 124 249 124 199 99 49 19 9 4 1 0
16 n -- 3 2 2 1 1 0 0 0 0 0 0 0 N -- 124 249 124 199 99 199 79 39 19 7 3 1 n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0
20 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0
Notes: Blank: No setting is available. --: A setting is available, but the bit rate is inaccurate.
B = OSC/[8 x 22n x (N + 1)] B: N: OSC : n: Bit rate BRR value (0 N 255) Crystal oscillator frequency in MHz Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o o/4 o/16 o/64
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13.3 Operation
13.3.1 Overview The SCI supports serial data transfer in both asynchronous and synchronous modes. The communication format depends on settings in the SMR as indicated in table 13-5. The clock source and usage of the SCK pin depend on settings in the SMR and SCR as indicated in table 13-6. Table 13-5 Communication Formats Used by SCI
SMR CHR PE 0 0 1 1 0 1 1 -- -- Stop Bit Length 1 2 1 2 1 2 1 2 --
C/A 0
STOP 0 1 0 1 0 1 0 1 --
Mode Asynchronous
Format 8-Bit data
Parity None Yes
7-Bit data
None Yes
Synchronous
8-Bit data
--
Table 13-6 SCI Clock Source Selection
SCR Clock CKE1 CKE0 Source 0 0 Internal 1 1 0 External 1 1 0 0 Internal (Sync 1 mode) 1 0 External 1 * Cannot be used by the SCI. SMR C/A 0 (Async mode)
SCK Pin I/O port* Clock output at same frequency as baud rate Clock input at 16 times the baud rate frequency Serial clock output Serial clock input
Transmitting and receiving operations in the two modes are described next.
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13.3.2 Asynchronous Mode In asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 13-2 shows the general format of one character sent or received in the asynchronous mode. The communication channel is normally held in the mark state (High). Character transmission or reception starts with a transition to the space state (Low). The first bit transmitted or received is the start bit (Low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit, if present, then the stop bit or bits (High) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
Idle state Start bit D0 D1 Dn Parity bit Stop bit
1 bit
7 or 8 bits
0 or 1 bit
1 or 2 bits
One character
Figure 13-2 Data Format in Asynchronous Mode 1. Data Format Table 13-7 lists the data formats that can be sent and received in asynchronous mode. Eight formats can be selected by bits in the SMR.
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Table 13-7 Data Formats in Asynchronous Mode
SMR Bits CHR 0 0 0 0 1 1 1 1 PE 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 1 0 1 Data Format START START START START START START START START 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data STOP STOP P P STOP STOP STOP STOP STOP STOP P P STOP STOP STOP STOP
Note: START: Start bit STOP: Stop bit P: Parity bit
2. Clock In the asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the SCK pin. Refer to table 13-6. If an external clock is input at the SCK pin, its frequency should be 16 times the desired baud rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse rises at the center of the transmit data bits. Figure 13-3 shows the phase relationship between the output clock and transmit data.
Output clock
Transmit data
Start bit
D0
D1
D2
Figure 13-3 Phase Relationship between Clock Output and Transmit Data
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3. Data Transmission and Reception SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0, then execute the following procedure. 1. Set the desired communication format in the SMR. 2. Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) 3. Select the clock and enable desired interrupts in the SCR. 4. Set the TE and/or RE bit in the SCR to 1. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least the transfer time for 1 bit at the selected baud rate, to make sure the SCI is initialized. If an external clock is used, the clock must not be stopped. When clearing the TDRE bit during data transmission, to assure transfer of the correct data, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. Data Transmission: The procedure for transmitting data is as follows. 1. Set up the desired transmitting conditions in the SMR, SCR, and BRR. 2. Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output and one frame* of all 1's will be transmitted, after which the SCI is ready to transmit data. 3. Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. 4. The first byte of transmit data is transferred from the TDR to the TSR and sent in the designated format as follows. i) Start bit (one 0 bit) ii) Transmit data (seven or eight bits, starting from bit 0) iii) Parity bit (odd or even parity bit, or no parity bit) iv) Stop bit (one or two consecutive 1 bits) 5. Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. When the transmit function is enabled but the TDR is empty (TDRE = 1), the output at the TXD pin is held at 1 until the TDRE bit is cleared to 0. * A frame is the data for one character, including the start bit and stop bit(s).
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Data Reception: The procedure for receiving data is as follows. 1. Set up the desired receiving conditions in the SMR, SCR, and BRR. 2. Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. 3. The SCI synchronizes with the incoming data by detecting the start bit, and places the received bits in the RSR. At the end of the data, the SCI checks that the stop bit is 1. If the stop bit length is 2 bits, the SCI checks that both bits are 1. 4. When a complete frame has been received, the SCI transfers the received data to the RDR so that it can be read. If the character length is 7 bits, the most significant bit of the RDR is cleared to 0. At the same time, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. 5. The RDRF bit is cleared to 0 when the CPU reads the SSR, then writes a 0 in the RDRF bit, or when the RDR is read by the data transfer controller (DTC). The RDR is then ready to receive the next character from the RSR. When a frame is not received correctly, a receive error occurs. There are three types of receive errors, listed in table 13-8. If a receive error occurs, the RDRF bit in the SSR is not set to 1. The corresponding error flag is set to 1 instead. If the RIE bit in the SCR is set to 1, a receive-error interrupt (ERI) is requested. When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun error occurs, however, the RSR contents are not transferred to the RDR. If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1. To clear a receive-error flag (ORER, FER, or PER), software must read the SSR, then write a 0 in the flag bit. Table 13-8 Receive Errors
Name Overrun error Abbreviation ORER Description Reception of the next frame ends while the RDRF bit is still set to 1. The RSR contents are not transferred to the RDR. A stop bit is 0. The RSR contents are transferred to the RDR. The parity of a frame does not match the value selected by the bit in the SMR. The RSR contents are transferred to the RDR.
Framing error Parity error
FER PER
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13.3.3 Synchronous Mode The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is synchronized with a serial clock pulse. Continuous data transfer is enabled by the double buffering employed in both the transmit and receive sections of the SCI. Full duplex communication is possible because the transmit and receive sections are independent. 1. Data Format Figure 13-4 shows the communication format used in the synchronous mode. The data length is 8 bits for both the transmit and receive directions. The least significant bit (LSB) is sent and received first. Each bit of transmit data is output from the falling edge of the serial clock pulse to the next falling edge. Received bits are latched on the rising edge of the serial clock pulse.
Transmission direction
Serial clock
Data
Bit 0 Don't-care
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Don't-care
Figure 13-4 Data Format in Synchronous Mode 2. Clock Either the internal serial clock created by the on-chip baud rate generator or an external clock input at the SCK pin can be selected in the synchronous mode. See table 13-6 for details.
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3. Data Transmission and Reception SCI Initialization: Before data can be transmitted or received, the SCI must be initialized by software. To initialize the SCI, software must clear the TE and RE bits to 0 to disable both the transmit and receive functions, then execute the following procedure. 1. Write the value corresponding to the desired bit rate in the BRR. (This step is not necessary if an external clock is used.) 2. Select the clock in the SCR. 3. Select the synchronous mode in the SMR*. 4. Set the TE and/or RE bit to 1, and enable desired interrupts in the SCR. The TE and RE bits must both be cleared to 0 whenever the operating mode or data format is changed. After changing the operating mode or data format, before setting the TE and RE bits to 1 software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the SCI is initialized. * The SCK pin is used for input or output according to the C/A bit in the serial mode register (SMR) and the CKE0 and CKE1 bits in the serial control register (SCR). (See table 13-6.) To prevent unwanted output at the SCK pin, pay attention to the order in which you set SMR and SCR. When clearing the TDRE bit during data transmission, to assure correct data transfer, do not clear the TDRE bit until after writing data in the TDR. Similarly, in receiving data, do not clear the RDRF bit until after reading data from the RDR. Data Transmission: The procedure for transmitting data is as follows. 1. Set up the desired transmitting conditions in the SMR, BRR, and SCR. 2. Set the TE bit in the SCR to 1. The TXD pin will automatically be switched to output, after which the SCI is ready to transmit data. 3. Check that the TDRE bit is set to 1, then write the first byte of transmit data in the TDR. Next clear the TDRE bit to 0. 4. The first byte of transmit data is transferred from the TDR to the TSR and sent, each bit synchronized with a clock pulse. Bit 0 is sent first. Transfer of the transmit data from the TDR to the TSR makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. The TDR and TSR function as a double buffer. Continuous data transmission can be achieved by writing the next transmit data in the TDR and clearing the TDRE bit to 0 while the SCI is transmitting the current data from the TSR.
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If an internal clock source is selected, after transferring the transmit data from the TDR to the TSR, while transmitting the data from the TSR the SCI also outputs a serial clock signal at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1), serial clock output is suspended until the next data byte is written in the TDR and the TDRE bit is cleared to 0. During this interval the TXD pin is held at the value of the last bit transmitted. If the external clock source is selected, data transmission is synchronized with the clock signal input at the SCK pin. When all data bits in the TSR have been transmitted, if the TDR is empty (TDRE = 1) but external clock pulses continue to arrive, the TXD pin outputs a string of bits equal to the last bit transmitted. Data Reception: The procedure for receiving data is as follows. 1. Set up the desired receiving conditions in the SMR, BRR, and SCR. 2. Set the RE bit in the SCR to 1. The RXD pin will automatically be switched to input and the SCI is ready to receive data. 3. Incoming data bits are latched in the RSR on eight clock pulses. When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to 1. If the RIE bit is set to 1, a receive-end interrupt (RXI) is requested. 4. The SCI transfers the received data byte to the RDR so that it can be read. The RDRF bit is cleared when the program reads the RDRF bit in the SSR, then writes a 0 in the RDRF bit, or when the data transfer controller (DTC) reads the RDR. The RDR and RSR function as a double buffer. Data can be received continuously by reading each byte of data from the RDR and clearing the RDRF bit to 0 before the last bit of the next byte is received. In general, an external clock source should be used for receiving data. If an internal clock source is selected, the SCI starts receiving data as soon as the RE bit is set to 1. The serial clock is also output at the SCK pin. The SCI continues receiving until the RE bit is cleared to 0. If the last bit of the next data byte is received while the RDRF bit is still set to 1, an overrun error occurs and the ORER bit is set to 1. If the RIE bit is set to 1, a receive-error interrupt (ERI) is requested. The data received in the RSR are not transferred to the RDR when an overrun error occurs. After an overrun error, reception of the next data is enabled when the ORER bit is cleared to 0.
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Simultaneous Transmit and Receive: The procedure for transmitting and receiving simultaneously is as follows: 1. Set up the desired communication conditions in the SMR, BRR, and SCR. 2. Set the TE and RE bits in the SCR to 1. The TXD and RXD pins are automatically switched to output and input, respectively, and the SCI is ready to transmit and receive data. 3. Data transmitting and receiving start when the TDRE bit in the SSR is cleared to 0. 4. Data are sent and received in synchronization with eight clock pulses. 5. First, the transmit data are transferred from the TDR to the TSR. This makes the TDR empty, so the TDRE bit is set to 1. If the TIE bit is set to 1, a transmit-end interrupt (TXI) is requested. If continuous data transmission is desired, the CPU must read the TDRE bit in the SSR, write the next transmit data in the TDR, then clear the TDRE bit to 0. Alternatively, the DTC can write the next transmit data in the TDR, in which case the TDRE bit is cleared automatically. If the TDRE bit is not cleared to 0 by the time the SCI finishes sending the current byte from the TSR, the TXD pin continues to output the last bit in the TSR. 6. In the receiving section, when 8 bits of data have been received they are transferred from the RSR to the RDR and the RDRF bit in the SSR is set to 1. If the RIE bit is set to 1, a receiveend interrupt (RXI) is requested. 7. To clear the RDRF bit, software read the RDRF bit in the SSR, read the data in the RDR, then write a 0 in the RDRF bit. Alternatively, the DTC can read the RDR, in which case the RDRF bit is cleared automatically. For continuous data reception, the RDRF bit must be cleared to 0 before the last bit of the next byte of data is received. If the last bit of the next byte is received while the RDRF bit is still set to 1, an overrun error occurs. The error is handled as described under "Data Reception" above. The overrun error does not affect the transmit section of the SCI, which continues to transmit normally.
13.4 CPU Interrupts and DTC Interrupts
The SCI can request three types of interrupts: transmit-end (TXI), receive-end (RXI), and receive-error (ERI). Interrupt requests are enabled or disabled by the TIE and RIE bits in the SCR. Independent signals are sent to the interrupt controller for each type of interrupt. The transmit-end and receive-end interrupt request signals are obtained from the TDRE and RDRF flags. The receive-error interrupt request signal is the logical OR of the three error flags: overrun error (ORER), framing error (FER), and parity error (PER). Table 13-9 lists information about these interrupts.
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Table 13-9 SCI Interrupts
DTC Service Available? No Yes Yes Low
Interrupt ERI RXI TXI
Description Receive-error interrupt, requested when ORER, FER, or PER is set. Receive-end interrupt, requested when RDRF is set. Transmit-end interrupt, requested when TDRE is set.
Priority High
The TXI and RXI interrupts can be served by the data transfer controller (DTC) to have a data transfer performed. When the DTC serves one of these interrupts, it clears the TDRE or RDRF bit to 0 under the following conditions, which differ between the two bits. When invoked by a TXI request, if the DTC writes to the TDR, it automatically clears the TDRE bit to 0. When invoked by an RXI request, if the DTC reads from the RDR, it automatically clears the RDRF bit to 0. See section 6, "Data Transfer Controller" for further information on the DTC.
13.5 Application Notes
Application programmers should note the following features of the SCI. TDR Write: The TDRE bit in the SSR is simply a flag that indicates that the TDR contents have been transferred to the TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in the TDR while the TDRE bit is 0, before the old TDR contents have been moved into the TSR, the old byte will be lost. Normally, software should check that the TDRE bit is set to 1 before writing to the TDR. Multiple Receive Errors: Table 13-10 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to the RDR.
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Table 13-10 SSR Bit States and Data Transfer When Multiple Receive Errors Occur
SSR Bits Receive Error RDRF ORER FER PER Overrun error 1*1 1 0 0 Framing error 0 0 1 0 Parity error 0 0 0 1 *1 Overrun + framing errors 1 1 1 0 Overrun + parity errors 1*1 1 0 1 Framing + parity errors 0 0 1 1 Overrun + framing + parity errors 1*1 1 1 1 Notes: *1 Set to 1 before the overrun error occurs. *2 Yes: The RSR contents are transferred to the RDR. No: The RSR contents are not transferred to the RDR.
RSR to RDR*2 No Yes Yes No No Yes No
Line Break Detection: When the RXD pin receives a continuous stream of 0's in the asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from the RSR to the RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in the RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RXD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 13-5. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.
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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1
Sync sampling
Data sampling
Figure 13-5 Sampling Timing (Asynchronous Mode) M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)F} x 100 [%] M: N: D: L: F: (1)
Receive margin Ratio of basic clock to bit rate (16) Duty factor of clock--ratio of High pulse width to Low width (0.5 to 1.0) Frame length (9 to 12) Absolute clock frequency deviation
When D = 0.5 and F = 0 M = (0.5 -1/2 x 16) x 100 [%] = 46.875% (2)
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Section 14 A/D Converter
14.1 Overview
The H8/510 chip includes an analog-to-digital converter module which can be programmed for input of analog signal on up to four channels. A/D conversion is performed by the successive approximations method with 10-bit resolution. 14.1.1 Features The features of the on-chip A/D module are: * * * * * Four analog input channels Sample and hold circuit 10-Bit resolution Rapid conversion Conversion time is 13.4 s per channel (at o = 10 MHz) Single and scan modes -- Single mode: A/D conversion is performed once. -- Scan mode: A/D conversion is performed in a repeated cycle on one to four channels. Four 16-bit data registers These registers store A/D conversion results for up to four channels. A CPU interrupt (ADI) can be requested at the completion of each A/D conversion cycle. This interrupt can also be served by the on-chip data transfer controller (DTC), providing a convenient way to move results into memory. The start of A/D conversion can be externally triggered.
* *
*
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14.1.2 Block Diagram Figure 14-1 shows a block diagram of A/D converter.
Module data bus
AVCC 10-Bit D/A AVSS
Successive approximations register
ADDRC
ADDRD
ADDRA
ADDRB
ADCSR
AN0 AN1 AN2 AN3 Analog multiplexor + o/8 - Control circuit o/16 ADTRG External trigger signal
Sample & hold circuit
ADCR
Bus interface
Internal data bus
ADI Interrupt signal ADDRA: ADDRB: ADDRC: ADDRD: ADCSR: ADCR: A/D Data Register A A/D Data Register B A/D Data Register C A/D Data Register D A/D Control/Status Register A/D Control Register
Figure 14-1 Block Diagram of A/D Converter
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14.1.3 Input Pins Table 14-1 lists the input pins used by the A/D converter module. Table 14-1 A/D Input Pins
Name Analog supply voltage Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 A/D trigger Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 ADTRG I/O Input Input Input Input Input Input Input Function Power supply and reference voltage for the analog circuits. Ground and reference voltage for the analog circuits. Analog input pins
Trigger input for start of A/D conversion
14.1.4 Register Configuration Table 14-2 lists the registers of the A/D converter module. Table 14-2 A/D Registers
Name Abbreviation R/W Initial Value A/D data register A (High) ADDRA (H) R H'00 A/D data register A (Low) ADDRA (L) R H'00 A/D data register B (High) ADDRB (H) R H'00 A/D data register B (Low) ADDRB (L) R H'00 A/D data register C (High) ADDRC (H) R H'00 A/D data register C (Low) ADDRC (L) R H'00 A/D data register D (High) ADDRD (H) R H'00 A/D data register D (Low) ADDRD (L) R H'00 A/D control/status register ADCSR R/(W)* H'00 A/D control register ADCR R/W H'7F * Software can write 0 to clear the status flag bits but cannot write 1. Address H'FE90 H'FE91 H'FE92 H'FE93 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99
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14.2 Register Descriptions
14.2.1 A/D Data Registers (ADDR)--H'FE90 to H'FE97
Bit ADDRn H Initial value Read/Write 7 AD9 0 R 6 AD8 0 R 5 AD7 0 R 4 AD6 0 R 3 AD5 0 R 2 AD4 0 R 1 AD3 0 R (n = A to D) Bit ADDRn L Initial value Read/Write 7 AD1 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R (n = A to D) 0 -- 0 R 0 AD2 0 R
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. Each result consist of 10 bits. The first 8 bits are stored in the upper byte of the data register corresponding to the selected channel. The last two bits are stored in the lower data register byte. The data registers are assigned to analog input channels as indicated in table 14-3. The A/D data registers are always readable by the CPU. The upper byte can be read directly. The lower byte is read via a temporary register. See section 14-3, "CPU Interface" for details. The unused bits (bits 5 to 0) of the lower data register byte are always read as 0. The A/D data registers are initialized to H'0000 at a reset and in the standby modes. Table 14-3 Assignment of Data Registers to Analog Input Channels
Analog Input Channel AN0 AN1 AN2 AN3 A/D Data Register ADDRA ADDRB ADDRC ADDRD
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14.2.2 A/D Control/Status Register (ADCSR)--H'FE98
Bit 7 ADF Initial value Read/Write Notes: *1 *2 0 R/(W)*1 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2*2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. The CH2 bit should always be cleared to 0.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the operation of the A/D converter module. The ADCSR is initialized to H'00 at a reset and in the standby modes. Bit 7--A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7 ADF 0
1
Description This bit is cleared from 1 to 0 when: (Initial value) 1. The chip is reset or placed in a standby mode. 2. The CPU reads the ADF bit after it has been set to 1, then writes a 0 in this bit. 3. An A/D interrupt is served by the data transfer controller (DTC). This bit is set to 1 at the following times: 1. Single mode: when one A/D conversion is completed. 2. Scan mode: when inputs on all selected channels have been converted.
Bit 6--A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt (ADI) when A/D conversion is completed.
Bit 6 ADIE 0 1
Description The A/D interrupt request (ADI) is disabled. The A/D interrupt request (ADI) is enabled.
(Initial value)
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Bit 5--A/D Start (ADST): The A/D converter operates while this bit is set to 1. In the single mode, this bit is automatically cleared to 0 at the end of each A/D conversion.
Bit 5 ADST 0 1
Description A/D conversion is halted. (Initial value) 1. Single mode: One A/D conversion is performed. The ADST bit is automatically cleared to 0 at the end of the conversion. 2. Scan mode: A/D conversion starts and continues cyclically on the selected channels until the ADST bit is cleared to 0.
Bit 4--Scan Mode (SCAN): This bit selects the scan mode or single mode of operation. See section 14.4, "Operation" for descriptions of these modes. The mode should be changed only when the ADST bit is cleared to 0.
Bit 4 SCAN 0 1
Description Single mode Scan mode
(Initial value)
Bit 3--Clock Select (CKS): This bit controls the A/D conversion time. The conversion time should be changed only when the ADST bit is cleared to 0.
Bit 3 CKS 0 1
Description Conversion time = 266 states Conversion time = 134 states
(Initial value)
Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit combine to select one or more analog input channels. The channel selection should be changed only when the ADST bit is cleared to 0.
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Group Select CH2 0
CH1 0 0 1 1
Channel Select CH0 0 1 0 1
Selected Channels Single Mode Scan Mode AN0 AN0 AN1 AN0 and AN1 AN2 AN0 to AN2 AN3 AN0 to AN3
14.2.3 A/D Control Register (ADCR)--H'FE99
Bit 7 TRGE Initial value Read/Write 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The A/D control register (ADCR) is an 8-bit readable/writable register that enables or disables the A/D external trigger signal. The ADCR is initialized to H'7F at a reset and in the standby modes. Bit 7--Trigger Enable (TRGE): The bit enables the ADTRG (A/D external trigger) signal. A High-to-Low transition of ADTRG sets the ADST bit, starting A/D conversion.
Bit 7 TRGE 0 1
Description A/D external trigger is disabled. ADTRG does not set the ADST bit. (Initial value) A/D external trigger is enabled. A High-to-Low transition of ADTRG sets the ADST bit. Pin P40 is set to input and used for ADTRG input.
Bit 6 to 0--Reserved: These bits cannot be modified and are always read as 1. 14.2.4 External Triggering of A/D Conversion External trigger input is enabled at the ADTRG pin when the TRGE bit in the ADCR is set to 1. One and one-half system clock cycles after the ADTRG input goes Low, the ADST bit in the ADCSR is set to 1 and A/D conversion commences. The timing of external triggering is shown in figure 14-2.
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o
1.5 Cycles ADTRG
ADST
A/D conversion
Figure 14-2 External Trigger Input Timing
14.3 CPU Interface
The A/D data registers (ADDRA to ADDRD) are 16-bit registers. The upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (TEMP). When the CPU or DTC reads the upper byte of an A/D data register, at the same time as the upper byte is placed on the internal data bus, the lower byte is transferred to TEMP. When the lower byte is accessed, the value in TEMP is placed on the internal data bus. A program that requires all 10 bits of an A/D result should perform word access, or should read first the upper byte, then the lower byte of the A/D data register. Either way, it is assured of obtaining consistent data. Consistent data are not assured if the program reads the lower byte first. A program that requires only 8-bit A/D accuracy should perform byte access to the upper byte of the A/D data register. The value in TEMP can be left unread. Figure 14-3 shows the data flow when the CPU (or DTC) reads an A/D data register.
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< Upper byte read >
Module data bus CPU receives data H'AA Bus interface
TEMP [H'40]
ADDRn H [H'AA]
ADDRn L [H'40] (n = A to D)
< Lower byte read >
Module data bus CPU receives data H'40 Bus interface
TEMP [H'40]
ADDRn H [H'AA]
ADDRn L [H'40] (n = A to D)
Figure 14-3 Read Access to A/D Data Register (When Register Contains H'AA40)
14.4 Operation
The A/D converter performs 10 successive approximations to obtain a result ranging from H'0000 (corresponding to AVSS) to H'FFC0 (corresponding to AVCC). Only the first 10 bits of the result are significant. The A/D converter module can be programmed to operate in single mode or scan mode as explained below.
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14.4.1 Single Mode The single mode is suitable for obtaining a single data value from a single channel. A/D conversion starts when the ADST bit is set to 1. During the conversion process the ADST bit remains set to 1. When conversion is completed, the ADST bit is automatically cleared to 0. When the conversion is completed, the ADF bit is set to 1. If the interrupt enable bit (ADIE) is also set to 1, an A/D conversion end interrupt (ADI) is requested, so that the converted data can be processed by an interrupt-handling routine. Alternatively, the interrupt can be served by the data transfer controller (DTC). When an A/D interrupt is served by the DTC, the DTC automatically clears the ADF bit to 0. When an A/D interrupt is served by the CPU, however, the ADF bit remains set until the CPU reads the ADCSR, then writes a 0 in the ADF bit. Before selecting the single mode, clock, and analog input channel, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process in single mode when channel 1 (AN1) is selected. Figure 14-4 shows the corresponding timing chart. 1. Software clears the ADST bit to 0, then selects the single mode (SCAN = 0) and channel 1 (CH2 to CH0 = "001"), enables the A/D interrupt request (ADIE = 1), and sets the ADST bit to 1 to start A/D conversion. (Selection of mode, clock channel and setting the ADST bit can be done at same time.) Coding Example: (when using the slow clock, CKS = 0) BCLR #5, @H'FE98 MOV.B #H'61, @H'FE98 2. The A/D converter samples the AN1 input and converts the voltage level to a digital value. At the end of the conversion process the A/D converter transfers the result to register ADDRB, sets the ADF bit is set to 1, clears the ADST bit to 0, and halts. 3. ADF = 1 and ADIE = 1, so an A/D interrupt is requested. 4. The user-coded A/D interrupt-handling routine is started. 5. The interrupt-handling routine reads the ADCSR value, then writes a 0 in the ADF bit to clear this bit to 0. 6. The interrupt-handling routine reads and processes the A/D conversion result. 7. The routine ends.
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Steps 2 to 7 can now be repeated by setting the ADST bit to 1 again. If the data transfer enable (DTE) bit is set to 1, the interrupt is served by the data transfer controller (DTC). Steps 4 to 7 then change as follows. 4'. 5'. 6'. 7'. The DTC is started. The DTC automatically clears the ADF bit to 0. The DTC transfers the A/D conversion result from ADDRB to a specified destination address. The DTC ends.
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Interrupt (ADI)
Figure 14-4 A/D Operation in Single Mode (When Channel 1 is Selected)
Set* ADIE A/D conversion starts ADST Clear * ADF Clear * Set* Set*
Channel 0 (AN 0)
Waiting
Channel 1 (AN 1)
Waiting
A/D conversion
Waiting
A/D conversion
Waiting
Channel 2 (AN 2)
Waiting
Channel 3 (AN 3)
Waiting
ADDRA Read result A/D conversion result Read result A/D conversion result
ADDRB
ADDRC
ADDRD * indicates execution of a software instruction.
14.4.2 Scan Mode The scan mode can be used to monitor analog inputs on one or more channels. When the ADST bit is set to 1, A/D conversion starts from the first channel (AN0). If the scan group includes more than one channel (i.e. if bit CH1 or CH0 is set), conversion of the next channel begins as soon as conversion of the first channel ends. Conversion of the selected channels continues cyclically until the ADST bit is cleared to 0. The conversion results are placed in the data registers corresponding to the selected channels. Before selecting the scan mode, clock, and analog input channels, software should clear the ADST bit to 0 to make sure the A/D converter is stopped. Changing the mode, clock, or channel selection while A/D conversion is in progress can lead to conversion errors. The following example explains the A/D conversion process when three channels are selected (AN0, AN1, and AN2). Figure 14-5 shows the corresponding timing chart. 1. Software clears the ADST bit to 0, then selects the scan mode (SCAN = 1), scan group 0 (CH2 = 0), and analog input channels AN0 to AN2 (CH1 and CH0 = 0) and sets the ADST bit to 1 to start A/D conversion. Coding Example: (with slow clock and ADI interrupt enabled) BCLR #5, @H'FE98 MOV.B #H'72, @FE98 2. The A/D converter samples the input at AN0, converts the voltage level to a digital value, and transfers the result to register ADDRA. 3. Next the A/D converter samples and converts AN1 and transfers the result to ADDRB. Then it samples and converts AN2 and transfers the result to ADDRC. 4. After all selected channels (AN0 to AN2) have been converted, the AD converter sets the ADF bit to 1. If the ADIE bit is set to 1, an A/D interrupt (ADI) is requested. Then the A/D converter begins converting AN0 again. 5. Steps 2 to 4 are repeated cyclically as long as the ADST bit remains set to 1. To stop the A/D converter, software must clear the ADST bit to 0. Regardless of which channel is being converted when the ADST bit is cleared to 0, when the ADST bit is set to 1 again, conversion begins from the first selected channel (AN0).
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Figure 14-5 A/D Operation in Scan Mode (When Channels 0 to 2 are Selected)
Continuous A/D conversion Set* ADST Clear * ADF A/D conversion time Waiting A/D conversion Waiting Waiting A/D conversion Waiting A/D conversion Waiting Clear *
Channel 0 (AN 0)
Channel 1 (AN 1)
A/D conversion Waiting A/D conversion Waiting Transfer
Waiting
Channel 2 (AN 2)
Waiting
Channel 3 (AN 3)
ADDRA
A/D conversion
A/D conversion
ADDRB
A/D conversion
ADDRC
A/D conversion
ADDRD *
indicates execution of a software instruction.
14.5 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a time tD after the ADST bit is set to 1. The sampling process lasts for a time tSPL. The actual A/D conversion begins after sampling is completed. Figure 14-6 shows the timing of these steps, and table 14-4 lists the total conversion times (tCONV) for the single mode. The total conversion time includes tD and tSPL. The purpose of tD is to synchronize the ADCSR write time with the A/D conversion process, so the length of tD is variable. The total conversion time therefore varies within the minimum to maximum ranges indicated in table 14-4. In the scan mode, the ranges given in table 14-4 apply to the first conversion. The length of the second and subsequent conversion processes is fixed at 256 states (when CKS = 0) or 128 states (when CKS = 1).
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(1) o
Internal address bus
(2)
Write signal
Input sampling timing
ADF tD tSPL tCONV
(1) (2) tD t SPL t CONV
: : : : :
ADCSR write cycle ADCSR address Synchronization delay Input sampling time Total A/D conversion time
Figure 14-6 A/D Conversion Timing Table 14-4 A/D Conversion Time (Single Mode)
CKS = 0 Item Symbol Min Typ Synchronization delay tD 10 -- Input sampling time tSPL -- 80 Total A/D conversion time tCONV 259 -- Note: Values in the table are numbers of states. CKS = 1 Typ -- 40 --
Max 17 -- 266
Min 6 -- 131
Max 9 -- 134
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14.6 Interrupts and the Data Transfer Controller
The ADI interrupt request is enabled or disabled by the ADIE bit in the ADCSR. When the ADI bit in data transfer enable register DTED (bit 0 at address H'FF0B) is set to 1, the ADI interrupt is served by the data transfer controller. The DTC can be used to transfer A/D results to a buffer in memory, or to an I/O port. The DTC automatically clears the ADF bit to 0. Note: In scan mode, the DTC can transfer data for only one channel per interrupt, even if two or more channels are selected.
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Section 15 Bus Controller
15.1 Overview
The H8/510 has an on-chip bus controller that enables the bus width and bus cycle length to be altered dynamically. When a 16-bit bus width is selected by the inputs at the mode pins, part of the address space can be reserved for access via an 8-bit bus (byte-access area). The bus controller can also switch an area between 8-bit and 16-bit access, and shorten the bus cycle from three states to two states for high-speed access. 15.1.1 Features The bus controller has the following features: * Setting of 8-bit data bus access area (in modes 2 and 4) Addresses greater than the address set in the byte area top register (ARBT) are designated for 8-bit access. (This area does not include the address set in ARBT, which is the boundary address of the word area.) When an address greater than the address set in ARBT is accessed, only the upper data bus lines (D15 to D8) are used, so the access is carried out with an 8-bit bus width. The bus width of the internal and external I/O areas, however, is not changed by the ARBT setting. * Setting of two-state access area Addresses equal to or greater than the address set in the three-state area top register (AR3T) are designated for three-state access. (This area includes the address set in AR3T, which is the boundary of the three-state area.) When an address less than the address set in AR3T is accessed, it is accessed using a two-state bus cycle. Wait states cannot be inserted into two-state access cycles. The bus cycle length of the internal and external I/O areas is not changed by the AR3T setting. * The boundaries of the word and three-state areas are set to multiples of 4 kbytes in minimum mode, and multiples of 64 kbytes in maximum mode.
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15.1.2 Block Diagram Figure 15-1 is a block diagram of the bus controller.
On-chip address bus (A 23 to A 20) On-chip address bus (A 19 to A 16) On-chip address bus (A 15 to A 12)
On-chip data bus (D15 to D 8 )
Multiplexer
ARBT
AR3T
Multiplexer
Lower 4 bits Upper 4 bits Upper 4 bits
Lower 4 bits
Comparator
Comparator
Comparator
Comparator
ARBT = Addr ARBT < Addr MAX ARBT > Addr
AR3T = Addr AR3T > Addr AR3T < Addr -
I/O access Mode 1 or 3
8-Bit access request Legend ARBT:Byte Area Top Register AR3T:Three-State Area Top Register
3-State access request
Figure 15-1 Block Diagram of Bus Controller
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15.1.3 Register Configuration Table 15-1 describes the bus controller registers. The Bus Controller Has Two 8-Bit Registers: A byte area top register (ARBT) that designates the boundary of the word area, and a three-state area top register (AR3T) that designates the boundary of the three-state area. Table 15-1 Bus Controller Registers
Name Byte area top register Three-state area top register Abbreviation ARBT AR3T R/W R/W R/W Initial Value H'FF H'00 Address H'FF16 H'FF17
15.2 Register Descriptions
15.2.1 Byte Area Top Register (ARBT)--H'FF16 The ARBT register designates the boundary between addresses that are accessed via a 16-bit data bus and addresses that are accessed using only the upper 8 bits of the 16-bit bus. The address set in ARBT is the last address accessed via a 16-bit-wide bus. This address is referred to as the word area boundary.
Bit: 7 6 5 4 3 2 1 0
Initial value: Read/Write:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The bus controller controls the CPU so that external addresses greater than the ARBT value are accessed via a 8-bit-wide bus. In the expanded maximum modes the value in ARBT is used as the upper eight bits (A23 to A16) of the word area boundary address. The word area boundary address is therefore settable to a multiple of 64 kbytes. Note that in the expanded maximum modes addresses H'000000 to H'00FE7F are always located in the word access area. In the expanded minimum modes only the four lowest ARBT bits are valid. They designate the upper four bits (A15 to A12) of the word area boundary address. The boundary address is therefore settable to a multiple of 4 kbytes. In the expanded minimum modes addresses H'0000 to H'0FFF are always located in the word access area.
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The ARBT setting affects only the external address space. It does not alter the bus width of the internal and external I/O areas. In modes 1 and 3 the entire address space is accessed via an 8-bit data bus, so the ARBT setting is ignored. ARBT is initialized to H'FF by a reset and in the hardware standby mode. It is not initialized in the software standby mode. 15.2.2 Three-State Area Top Register (AR3T)--H'FF17 The AR3T register designates the boundary between the two-state access area and the three-state access area. The value set in AR3T, referred to as the three-state area boundary, is the first address to be accessed in three states.
Bit: 7 6 5 4 3 2 1 0
Initial value: Read/Write:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The bus controller controls the CPU so that external addresses equal to or greater than the AR3T value are accessed in three states. Wait states cannot be inserted in two-state access. In the expanded maximum modes the AR3T value designates the upper eight bits (A23 to A16) of the three-state area boundary address. The three-state area boundary address is therefore settable as a multiple of 64 kbytes. Note that in the expanded maximum modes addresses H'F00000 to H'FFFFFF are always accessed in three states. In the expanded minimum modes only the four lowest AR3T bits are valid. They designate the upper four bits (A15 to A12) of the three-state area boundary address. The three-state area boundary address is therefore settable as a multiple of 4 kbytes. In the expanded minimum modes addresses H'F000 to H'FFFF are always accessed in three states. The AR3T setting affects only the external address space. It does not alter the bus cycle length of the external and internal I/O areas. AR3T is initialized to H'00 by a reset and in the hardware standby mode. It is not initialized in the software standby mode.
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15.3 Operation
1. Operation in Each Mode after a Reset: See figure 15-2. Mode 1: The bus is 8 bits wide. Addresses H'0000 to H'FFFF are all accessed at 8 bits per three states.
8 bits H'0000 External bus area 8 bits, 3 states H'FE7F H'FE80 H'FF7F H'FF80 H'FFFF
Internal I/O area 8 bits, 3 states External I/O area 8 bits, 3 states
Figure 15-2 Bus Width and Cycle Length after Reset (Mode 1) Mode 2: The bus is 16 bits wide. Addresses H'0000 to H'FE7F are accessed in three states via the 16-bit bus. Addresses H'FE80 to H'FF7F are the internal I/O area, accessed at 8 bits per three states. Addresses H'FF80 to H'FFFF are the external I/O area, also accessed at 8 bits per three states.
16 bits H'0000 External bus area 16 bits, 3 states H'FE7F H'FE80 H'FF7F H'FF80 H'FFFF
Fig. 15-2 (1
Internal I/O area 8 bits, 3 states External I/O area 8 bits, 3 states
Figure 15-2 Bus Width and Cycle Length after Reset (Mode 2)
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Mode 3: The bus is 8 bits wide. Addresses H'000000 to H'FFFFFF are all accessed at 8 bits per three states.
8 bits H'000000 External bus area 8 bits, 3 states H'00FE7F H'00FE80 H'00FF7F H'00FF80 H'00FFFF H'100000
Internal I/O area 8 bits, 3 states External I/O area 8 bits, 3 states
External bus area 8 bits, 3 states H'FFFFFF
Figure 15-2 Bus Width and Cycle Length after Reset (Mode 3)
Fig. 15-2 (3)
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Mode 4: The bus is 16 bits wide. Addresses H'000000 to H'00FE7F and H'010000 to H'FEFFFF are accessed in three states via the 16-bit bus. Addresses H'00FE80 to H'00FF7F are the internal I/O area, accessed at 8 bits per three states. Addresses H'00FF80 to H'00FFFF are the external I/O area, also accessed at 8 bits per three states.
16 bits H'000000 External bus area 16 bits, 3 states H'00FE7F H'00FE80 H'00FF7F H'00FF80 H'00FFFF H'010000 H'FEFFFF H'FF0000 H'FFFFFF
Internal I/O area 8 bits, 3 states External I/O area 8 bits, 3 states External bus area 16 bits, 3 states External bus area 8 bits, 3 states
Figure 15-2 Bus Width and Cycle Length after Reset (Mode 4)
Fig. 15-2 (4
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2. Timing of Changes in Bus Parameters: Changes in the bus width or bus cycle length take effect starting in the next bus cycle after the ARBT or AR3T write cycle.
T1
T2
T3
o
A 23 to A 0
ARBT or AR3T address
Internal write signal
Internal data bus
New value
Bus parameters
Old setting
New setting
Figure 15-3 Time at which Bus Controller Setting Takes Effect (Byte Write)
Fig. 15-3
264
T1
T2
T3
T1
T2
T3
o
A23 to A0
ARBT address
AR3T address
Internal write signal
Internal data bus
New value
New value
Bus parameters
Old setting
Transient setting
New setting
Invalid bus setting
Figure 15-4 Time at which Bus Controller Setting Takes Effect (Word Write)
Fig. 1
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15.4 Notes and Precautions
When using the bus controller, note the following points. Rewriting ARBT and AR3T: When ARBT and AR3T are rewritten, the bus parameters may become temporarily invalid, preventing normal program execution. This situation should be prevented as follows. Solution: Place a branch instruction after any instruction that rewrites ARBT or AR3T. The branch instruction clears the instruction fetch performed using the temporarily invalid bus parameters, thereby preventing incorrect operation.
. . . MOV R2,@ARBT BRA L1 L1:
This branch instruction avoids incorrect operation Branch destination is next instruction
Example: branch instruction placed after rewrite instruction
Figure 15-5 Example of Program that Rewrites ARBT or AR3T
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Data Bus and Control Signals for Different Types of Access: The data bus and control signals vary depending on the type of access as indicated in table 15-2. Table 15-2 Data Bus and Control Signals for Different Types of Access
Data Bus Access Type 8-bit bus CPU external address (write) 8-bit bus CPU external address (read) 16-bit bus Word area access CPU external address (write) 16-bit bus Word area access CPU external address (read) 16-bit bus Byte area access CPU external address (write) 16-bit bus Byte area access CPU external address (read) A0 0 1 0 1 0 1 0 1 0 1 0 1 D15 to D8 MSB LSB MSB LSB MSB -- MSB -- MSB LSB MSB LSB D7 to D0 Not used (I/O port) Not used (I/O port) LSB -- LSB -- Hi-Z Hi-Z Don't care Don't care Control Signals RD H H L L H -- L -- H H L L HWR L L H H L -- H -- L L H H LWR H H H H L -- H -- H H H H
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Figures 15-6 and 15-7 show examples of bus controller settings made in mode 4. 1. AR3T ARBT + 1
16 bits Bus cycle H'000000 External bus area H'00FE7F H'00FE80 Internal I/O area H'00FF7F H'00FF80 External I/O area H'00FFFF H'010000 2 states 3 states 8 bits 3 states 8 bits 2 states 16 bits Bus width
AR3T
16 bits
External bus area 3 states ARBT
8 bits
H'FFFFFF Mode 4
Figure 15-6 Example of Bus Controller Usage (Mode 4)
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2. AR3T > ARBT + 1
16 bits Bus cycle H'000000 External bus area H'00FE7F H'00FE80 Internal I/O area H'00FF7F H'00FF80 External I/O area H'00FFFF H'010000 16 bits ARBT 2 states 3 states 8 bits 3 states 8 bits 2 states 16 bits Bus width
External bus area 8 bits AR3T 3 states H'FFFFFF Mode 4
Figure 15-7 Example of Bus Controller Usage (Mode 4)
Fig. 15-7
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Section 16 Watchdog Timer
16.1 Overview
The H8/510 has an on-chip watchdog timer (WDT) module. This module can monitor system operation by generating a signal that resets the H8/510 chip if a system crash allows the timer count to overflow. When this watchdog function is not needed, the WDT module can be used as an interval timer. In the interval timer mode, an IRQ0 interrupt is requested at each counter overflow. The WDT module is also used in recovering from the software standby mode. 16.1.1 Features The basic features of the watchdog timer module are summarized as follows: * Selection of eight clock sources * Selection of two modes: watchdog timer mode and interval timer mode * Counter overflow generates a reset signal or interrupt request Reset signal in the watchdog timer mode; IRQ0 request in the interval timer mode. * External output of reset signal The reset signal generated when the watchdog timer overflows resets the entire H8/510 chip. Depending on a reset output enable bit, the reset signal can also be output from the RES pin to reset devices controlled by the H8/510.
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16.1.2 Block Diagram Figure 16-1 is a block diagram of the watchdog timer.
Interrupt signal IRQ 0 (Interval timer mode) Interrupt control Overflow TCNT Read/ write control Internal data bus
TCSR
Internal clock sources o/2 RSTCSR Reset signal (internal, external) Reset control Clock Clock select o/32 o/64 o/128 o/256 o/512 o/2048 o/4096
TCNT : Timer Counter TCSR : Timer Control/Status Register RSTCSR : Reset Control/Status Register
Figure 16-1 Block Diagram of Timer Counter 16.1.3 Register Configuration Table 16-1 lists information on the watchdog timer registers. Table 16-1 Register Configuration
Initial Value H'18 H'00 H'3F Addresses Write Read H'FF10 H'FF10 H'FF10 H'FF11 H'FF1E H'FF1F
Name Timer control/status register Timer counter Reset control/status register
Abbreviation TCSR TCNT RSTCSR
R/W R/(W)* R/W R/(W)*
* Software can write a 0 to clear bit 7, but cannot write a 1.
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16.2 Register Descriptions
16.2.1 Timer Counter TCNT--H'FF10 (Write), H'FF11 (Read)
Bit 7 6 5 4 3 2 1 0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The watchdog timer counter (TCNT) is a readable/writable* 8-bit up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in the TCSR. When the count overflows (changes from H'FF to H'00), the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The watchdog timer counter is initialized to H'00 at a reset and when the TME bit is cleared to 0. * TCNT is write-protected by a password. See section 16.2.4, "Notes on Register Access" for details. 16.2.2 Timer Control/Status Register (TCSR)--H'FF10
Bit
7 OVF
6 WT/IT 0 R/W
5 TME 0 R/W
4 -- 1 --
3 -- 1 --
2 CKS2 0 R/W
1 CKS1 0 R/W
0 CKS0 0 R/W
Initial value Read/Write
0 R/(W)*1
The watchdog timer control/status register (TCSR) is an 8-bit selects the timer mode and clock source and performs other functions.
readable/writable*2
register that
Bits 7 to 5 are initialized to 0 at a reset and in the standby modes. Bits 2 to 0 are initialized to 0 at a reset, but retain their values in the software standby mode. Notes: *1 Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. *2 The TCSR is write-protected by a password. See section 16.2.4, "Notes on Register Access" for details.
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Bit 7--Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed.
Bit 7 OVF 0
Description This bit is cleared from 1 to 0 when the CPU reads (Initial value) the OVF bit after it has been set to 1, then writes a 0 in this bit. 1 This bit is set to 1 when TCNT changes from H'FF to H'00. * The OVF bit is not set in the watchdog timer mode.
Bit 6--Timer Mode Select (WT/IT): This bit selects whether to operate in the watchdog timer mode or interval timer mode. If the watchdog timer mode is selected, a watchdog timer overflow resets the chip. If the interval timer mode is selected, a watchdog timer overflow generates an IRQ0 interrupt request.
Bit 6 WT/IT 0 1
Description Interval timer mode (IRQ0 request) Watchdog timer mode (Reset)
(Initial value)
Bit 5--Timer Enable (TME): This bit enables or disables the timer.
Bit 5 TME 0 1
Description TCNT is initialized to H'00 and stopped. (Initial value) TCNT runs. A reset or interrupt is requested when the count overflows.
Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval listed in the table below is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In the interval timer mode, IRQ0 interrupts are requested at this interval.
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Bit 2 CKS2 0 0 0 0 1 1 1 1
Bit 1 CKS1 0 0 1 1 0 0 1 1
Bit 0 CKS0 0 1 0 1 0 1 0 1
Clock Source o/2 o/32 o/64 o/128 o/256 o/512 o/2048 o/4096
Description Overflow Interval (o = 10 MHz) 51.2 s (Initial value) 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms
16.2.3 Reset Control/Status Register (RSTCSR)--H'FF1F (Read), H'FF1E (Write)
Bit 7 WRST Initial value Read/Write 0 R/(W)*1 6 RSTOE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The reset control/status register (RSTCSR) is an 8-bit readable/writable*2 register that indicates when a reset has been caused by a watchdog timer overflow, and controls external output of the reset signal. Bit 6 is not initialized by the reset caused by the watchdog timer overflow. It is initialized, however, by a reset caused by input at the RES pin. Notes: *1 Software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. *2 RSTCSR is write-protected by a password. See section 16.2.4, "Notes on Register Access" for details. Bit 7--Watchdog Timer Reset (WRST): This bit indicates that a reset signal has been generated by a watchdog timer overflow in the watchdog timer mode. The reset signal generated by the overflow resets the entire H8/510 chip. In addition, if the reset output enable (RSTOE) bit is set to 1, a reset signal (Low) is output at the RES pin to reset devices connected to the H8/510. The WRST bit can be cleared by software by writing a 0. It is also cleared when a reset signal from an external device is received at the RES pin.
Bit 7 WRST 0 1 Description This bit is cleared to 0 by a reset signal input from the RES pin, or (Initial state) when software reads the WRST bit after it has been set to 1, then writes a 0 in this bit. This bit is set to 1 when the watchdog timer overflows in the watchdog timer mode and an internal reset signal is generated. 275
Bit 6--Reset Output Enable (RSTOE): This bit selects whether the reset signal generated by a watchdog timer overflow in the watchdog timer mode is output from the RES pin.
Bit 6 RSTOE 0 1
Description The reset signal generated by a watchdog timer overflow is not (Initial state) output to external devices. The reset signal generated by a watchdog timer overflow is output to external devices.
Bit 5 to 0--Reserved: These bits cannot be modified and are always read as 1. 16.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by word access. Programs cannot write to them by byte access. The word must contain the write data and a password. The watchdog timer's TCNT and TCSR registers both have the same write address. The write data must be contained in the lower byte of the word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 16-2. The result of the access depicted in figure 16-2 is to transfer the write data from the lower byte to TCNT or TCSR.
Write to TCNT 15 Address H'FF10 H'5A 8 7 Write data 0
Write to TCSR 15 Address H'FF10 H'A5 8 7 Write data 0
Figure 16-2 Writing to TCNT and TCSR
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Writing to RSTCSR: RSTCSR must be written by moving word data to address H'FF1E. It cannot be written by byte access. The upper byte of the word must contain a password. Separate passwords are used for clearing the WRST bit and for writing a 1 or 0 to the RSTOE bit. To clear the WRST bit, the word written at address H'FFFE must contain the password H'A5 in the upper byte and the data H'00 in the lower byte. This clears the WRST bit to 0 without affecting other bits. To set or clear the RSTOE bit, the word written at address H'FF1E must contain the password H'5A in the upper byte and the write data in the lower byte. This writes the desired data in the RSTOE bit without affecting other bits. These write operations are illustrated in figure 16-3.
To write 0 to the WRST bit 15 Address H'FF1E H'A5 8 7 H'00 0
To write to the RSTOE bit 15 Address H'FF1E H'5A 8 7 0
Write data (H'00 or H'FF)
Figure 16-3 Writing to RSTCSR
Reading TCNT, TCSR, and RSTCSR: The read addresses are H'FF10 for TCSR, H'FF11 for TCNT, and H'FF1F for RSTCSR as indicated in table 16-2. These three registers are read like other registers. Byte access instructions can be used. Table 16-2 Read Addresses of TCNT and TCSR
Read Address H'FF10 H'FF11 H'FF1F Register TCSR TCNT RSTCSR
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16.3 Operation
16.3.1 Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in the timer control/status register (TCSR). Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the watchdog timer generates a reset as shown in figure 16-4. The reset signal from the watchdog timer can also be output from the RES pin to reset external devices. This reset output signal is a Low pulse with a duration of 132 system clock cycles. The reset signal is output only if the RSTOE bit in the timer control/status register is set to 1. The reset generated by the watchdog timer has the same vector as a reset generated by Low input at the RES pin. Software should check the WRST bit in the reset control/status register (RSTCSR) to determine the source of the reset. If a watchdog timer overflow occurs at the same time as a Low input at the RES pin, priority is given to one type of reset or the other depending on the value of the RSTOE bit in the reset control/status register. If the RSTOE bit is set to 1 when both types of reset occur simultaneously, the watchdog timer's reset signal takes precedence. The internal state of the H8/510 chip is reset, the RSTOE bit remains set to 1, the WRST bit is also set to 1, and the RES pin is held Low for 132 system clock cycles. If at the end of 520 system clock cycles there is still an external Low input to the RES pin, the external reset takes effect, clearing the WRST and RSTOE bits to 0. Note that if the external reset occurs before the watchdog timer overflows, it takes effect immediately and clears the RSTOE bit. If the RSTOE bit is cleared to 0 when both types of reset occur simultaneously, the reset signal input form the RES pin takes precedence and the WRST bit is cleared to 0.
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H'FF
Watchdog timer overflow
TCNT count
H'00 OVF = 1 Start H'00 written to TCNT Reset Start H'00 written to TCNT
Internal reset signal External reset signal (RES)
*
* The external reset signal is output for 132 system clock cycles. The internal reset signal remains asserted for 520 system clock cycles.
Figure 16-4 Operation in Watchdog Timer Mode 16.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In the interval timer mode, an IRQ0 request is generated each time the timer count overflows. This function can be used to generate IRQ0 requests at regular intervals. See figure 16-5. IRQ0 requests from the watchdog timer module have a different vector as IRQ0 requests from the IRQ0 pin, so the IRQ0 interrupt-handling routine does not have to determine the source of the interrupt (which it could do by checking the OVF bit).
H'FF
TCNT count
Time t H'00
WT/IT = 0 TME = 1
IRQ 0 request
IRQ 0 request
IRQ 0 request
IRQ 0 request
IRQ 0 request
Figure 16-5 Operation in Interval Timer Mode
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16.3.3 Operation in Software Standby Mode The watchdog timer has a special function in the software standby mode. Specific watchdog timer settings are required when the software standby mode is used. Before Transition to the Software Standby Mode: The TME bit must be cleared to 0 to stop the watchdog timer counter before a transition to the software standby mode. The chip cannot enter the software standby mode while the TME bit is set to 1. Before entering the software standby mode, software should also set the clock select bits (CKS2 to CKS0) to a value that makes the timer overflow interval equal to or greater than the settling time of the clock oscillator. Recovery from the Software Standby Mode: Recovery from the software standby mode can be triggered by an NMI request. In this case the recovery proceeds as follows: When an NMI request signal is received, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by the clock select bits before the software standby mode was entered. When the count overflows from H'FF to H'00, the system clock is presumed to be stable and usable, clock signals are supplied to all modules on the chip, and the NMI interrupthandling routine starts executing. 16.3.4 Setting of Overflow Flag The OVF bit is set to 1 when the timer count overflows in interval timer mode. Simultaneously, the WDT module requests an IRQ0 interrupt. The timing is shown in figure 16-6.
o
TCNT
H'FF
H'00
Internal overflow signal
OVF
Figure 16-6 Setting of OVF Bit
280
16.3.5 Setting of Watchdog Timer Reset (WRST) Bit The WRST bit is valid when WT/IT = 1 and TME = 1. The WRST bit is set to 1 when the timer count overflows. An internal reset signal is simultaneously generated for the entire H8/510 chip. The timing is shown in fugure 16-7.
o
TCNT
H'FF
H'00
Internal overflow signal
WRST
Internal reset signal
Figure 16-7 Setting of WRST Bit and Internal Reset Signal
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16.4 Application Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 16-8.
Write cycle: CPU writes to TCNT T1 T2 T3
o
Address
TCNT address
Internal write signal
TCNT clock pulse
TCNT
N
M Write data
Figure 16-8 TCNT Write-Increment Contention Changing the Clock Select Bits (CKS2 to CKS0): Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly.
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4.7 k H8/510 74LS05 RES External reset signal 60 pF *
2SC2618 or equivalent
100 k Reset switch 74HC14 1.0 k 1.0 F
* Maximum value of wiring capacitance
Figure 16-9 Reset Circuit (Example)
283
Section 17 Power-Down State
17.1 Overview
The H8/510 has a power-down state that greatly reduces power consumption by stopping the CPU functions. The power-down state includes three modes: 1. Sleep mode 2. Software standby mode 3. Hardware standby mode The sleep mode and software standby mode are entered from the program execution state by executing the SLEEP instruction under the conditions given in table 17-1. The hardware standby mode is entered from any other state by a Low input at the STBY pin. Table 17-1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc., in each power-down mode. Table 17-1 Power-Down State
Entering Procedure Execute SLEEP instruction Set SSBY bit in SBYCR to 1, then execute SLEEP instruction* Set STBY pin to Low level CPU Reg's. Held Sup. Mod's. Run I/O Ports Held Exiting Methods * Interrupt * RES Low * STBY Low * NMI * RES Low * STBY Low
Mode Sleep mode Software standby mode
Clock Run
CPU Halt
Halt
Halt
Held
Halt and partly initialized Halt and initialized
Held
HardHalt Halt ware standby mode * The watchdog timer must also be stopped.
Not held
High impedance state
* STBY High, then RES Low High
Notes: SBYCR: Software standby control register SSBY: Software standby bit
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17.2 Sleep Mode
17.2.1 Transition to Sleep Mode Execution of the SLEEP instruction causes a transition from the program execution state to the sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The functions of the on-chip supporting modules do not stop in the sleep mode. 17.2.2 Exit from Sleep Mode The chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a Low input at the RES or STBY pin. Wake-Up by Interrupt: An interrupt releases the sleep mode and starts either the CPU's interrupt-handling sequence or the data transfer controller (DTC). If the interrupt is served by the DTC, after the data transfer is completed the CPU executes the instruction following the SLEEP instruction, unless the count in the data transfer count register (DTCR) is 0. If an interrupt on a level equal to or less than the mask level in the CPU's status register (SR) is requested, the interrupt is left pending and the sleep mode continues. Also, if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Wake-Up by RES Pin: When the RES pin goes Low, the chip exits from the sleep mode to the reset state. Wake-Up by STBY Pin: When the STBY pin goes Low, the chip exits from the sleep mode to the hardware standby mode.
17.3 Software Standby Mode
17.3.1 Transition to Software Standby Mode A program enters the software standby mode by setting the standby bit (SSBY) in the software standby control register (SBYCR) to 1, then executing the SLEEP instruction. Table 17-2 lists the attributes of the software standby control register.
286
Table 17-2 Software Standby Control Register
Name Software standby control register Abbreviation SBYCR R/W R/W Initial Value H'7F Address H'FF1A
In the software standby mode, the CPU, clock, and the on-chip supporting module functions all stop, reducing power consumption to an extremely low level. The on-chip supporting modules and their registers are reset to their initial state, but as long as a minimum necessary voltage supply is maintained (at least 2 V), the contents of the CPU registers remain unchanged. The I/O ports also remain in their current states. 17.3.2 Software Standby Control Register (SBYCR)
Bit 7 SSBY Initial value Read/Write 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
The software standby control register (SBYCR) is an 8-bit register that controls the action of the SLEEP instruction. Bit 7--Software Standby (SSBY): This bit enables or disables the transition to the software standby mode.
Bit 7 SSBY 0 1
Description The SLEEP instruction causes a transition to the sleep mode. (Initial value) The SLEEP instruction causes a transition to the software standby mode.
The watchdog timer must be stopped before the chip can enter the software standby mode. To stop the watchdog timer, clear the timer enable bit (TME) in the watchdog timer's timer control/status register (TCSR) to 0. The SSBY bit cannot be set to 1 while the TME bit is set to 1. When the chip is recovered from the software standby mode by a nonmaskable interrupt (NMI), the SSBY bit is automatically cleared to 0. It is also cleared to 0 by a reset or transition to the hardware standby mode. Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1.
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17.3.3 Exit from Software Standby Mode The chip can be brought out of the software standby mode by an input at one of three pins: the NMI pin, RES pin, or STBY pin. Recovery by NMI Pin: When an NMI request signal is received, the clock oscillator begins operating but clock pulses are supplied only to the watchdog timer (WDT). The watchdog timer begins counting from H'00 at the rate determined by the clock select bits (CKS2 to CKS0) in its timer status/control register (TCSR). This rate should be set slow enough to allow the clock oscillator to stabilize before the count reaches H'FF. When the count overflows from H'FF to H'00, clock pulses are supplied to the whole chip, the software standby mode ends, and execution of the NMI interrupt-handling sequence begins. The clock select bits (CKS2 to CKS0) should be set as follows. * Crystal Oscillator: Set CKS2 to CKS0 to a value that makes the watchdog timer interval equal to or greater than 10ms, which is the clock stabilization time. * External Clock Input: CKS2 to CKS0 can be set to any value. The minimum value (CKS2 = CKS1 = CKS0 = 0) is recommended. Recovery by RES Pin: When the RES pin goes Low, the clock oscillator starts. Next, when the RES pin goes High, the CPU begins executing the reset sequence. When the chip recovers from the software standby mode by a reset, clock pulses are supplied to the entire chip at once. Be sure to hold the RES pin Low long enough for the clock to stabilize. Recovery by STBY Pin: When STBY the pin goes Low, the chip exits from the software standby mode to the hardware standby mode. 17.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode on the falling edge of the NMI input and recovers from the software standby mode on the rising edge of NMI. Figure 17-1 shows a timing chart of the transitions. The nonmaskable interrupt edge bit (NMIEG) in the NMI control register (NMICR) is originally cleared to 0, selecting the falling edge as the NMI trigger. After accepting an NMI interrupt in this condition, software changes the NMIEG bit to 1, sets the SSBY bit to 1, and executes the SLEEP instruction to enter the software standby mode. The chip recovers from the software standby mode on the next rising edge at the NMI pin.
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Oscillator
o
NMI
NMIEG
SSBY Clock setting time
NMI interrupt handling NMIEG = 1 SSBY = 1 SLEEP instruction
Software standby mode (Power-down state)
NMI interrupt handling WDT interval (tOSC2 )
Clock start-up time
WDT overflow
Figure 17-1 NMI Timing of Software Standby Mode (Application Example) 17.3.5 Application Notes The I/O ports remain in their current states in the software standby mode. If a port is in the High output state, the output current is not reduced in the software standby mode.
17.4 Hardware Standby Mode
17.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters the hardware standby mode whenever the STBY pin goes Low. The hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The on-chip supporting modules go into the reset state. Note: Do not change the inputs at the mode pins (MD2, MD1, MD0) during hardware standby mode. Be particularly careful not to let all three mode inputs go Low, since that would cause increased current dissipation.
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17.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes High, the clock oscillator begins running. The RES pin should be Low at this time and should be held Low long enough for the clock to stabilize. When the RES pin changes from Low to High, the reset sequence is executed and the chip returns to the program execution state. 17.4.3 Timing Sequence of Hardware Standby Mode Figure 17-2 shows the usual sequence for entering and leaving the hardware standby mode. First the RES pin goes Low, placing the chip in the reset state. Then the STBY pin goes Low, placing the chip in the hardware standby mode and stopping the clock. In the recovery sequence first the STBY pin goes High; then after the clock stabilizes, the RES pin is returned to the High level.
Oscillator
RES
STBY
Clock setting time
Figure 17-2 Hardware Standby Sequence
Restart
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Section 18 E Clock Interface
18.1 Overview
For interfacing to E clock based peripheral devices, the H8/510 can generate an E clock output. Special instructions (MOVTPE, MOVFPE) perform data transfers synchronized with the E clock. The E clock is created by dividing the system clock (o) by 8. When the CPU executes an instruction that synchronizes with the E clock, the address is output on the address bus as usual, but the data bus and the RD and HWR signal lines do not become active until the falling edge of the E clock is detected. The length of the access cycle for an instruction synchronized with the E clock is accordingly variable. Figures 18-1 and 18-2 show the timing in the cases of maximum and minimum synchronization delay. The wait state controller (WSC) does not insert any wait states (Tw) during the execution of an instruction synchronized with the E clock.
291
Figure 18-1 Execution Cycle of Instruction Synchronized with E Clock (Maximum Synchronization Delay)
Last state o
T1
T2
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
TE
T3
E
A 23 to A0
AS, RD (Read access)
HWR (Write access)
D15 to D 8 (Read access)
D15 to D 8 (Write access)
Last state o
T1
T2
TE
TE
TE
TE
TE
TE
TE
T3
E
A 23 to A0
AS, RD (Read access)
HWR (Write access)
D15 to D 8 (Read access)
D15 to D 8 (Write access)
Figure 18-2 Execution Cycle of Instruction Synchronized with E Clock (Minimum Synchronization Delay)
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Section 19 Electrical Specifications
19.1 Absolute Maximum Ratings
Table 19-1 lists the absolute maximum ratings. Table 19-1 Absolute Maximum Ratings
Item Supply voltage Input voltage (except port 7) (port 7) Analog supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin AVCC VAN Topr Tstg Rating -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 -55 to +125 Unit V V V V V C C C
Note: Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recomended operating conditions.
19.2 Electrical Characteristics
19.2.1 DC Characteristics Table 19-2 lists the DC characteristics.
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Table 19-2 DC Characteristics Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%*1, VSS = AVSS = 0 V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
Symbol VIH Measurement Unit Conditions V V V V V V V V V A A
Item Input High voltage RES, STBY, EXTAL Port 7 Other input pins (except port 4) Input Low voltage RES, STBY, MD2, MD1, MD0 Other input pins (except port 4) Schmitt trigger Port 4 input voltage Input leakage current
Min VCC - 0.7 VCC x 0.7 2.2 2.2 -0.3 -0.3
Typ - - - - - - - - - - -
Max VCC + 0.3 VCC + 0.3 AVCC + 0.3 VCC + 0.3 0.5 0.8 2.5 3.5 - 10.0 1.0
VIL
Leakage current in 3-state (off state) Output High voltage Output Low voltage Input copacitance
RES STBY, NMI, MD2, MD1, MD0, port 7 Port 8, | ITSI | ports 6 to 1 All output pins VOH
VTVT+ VT+-VT| Iin |
1.0 2.0 0.4 - -
Vin = 0.5 to VCC - 0.5 V
-
-
1.0
A
Vin = 0.5 to VCC - 0.5 V
IOH = -200 A IOH = -1 mA All output pins VOL IOL = 1.6 mA RES IOL = 2.6 mA All input pins Cin Vin = 0 V f = 1 MHz Ta = 25C Note: *1 AVCC must be connected to the power supply even when the A/D converter is not used.
VCC - 0.5 3.5 - - -
- - - - -
- - 0.4 0.4 20
V V V V pF
296
Table 19-2 DC Characteristics (cont)
Symbol ICC Measurement Conditions f = 6 MHz f = 8 MHz f = 10 MHz f = 6 MHz f = 8 MHz f = 10 MHz Ta 50C Ta > 50C
Item Current dissipation*1 Normal operation
Sleep mode
Standby Analog supply current
During A/D AICC conversion While waiting - 0.01 5.0 A Note: *1 Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V and all output pins are in the no-load state.
Min - - - - - - - - -
Typ 15 20 25 9 12 15 0.01 - 1.0
Max 30 40 50 20 25 30 5.0 20.0 2.0
Unit mA mA mA mA mA mA A A mA
Conditions: VCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to +75C (Regular Specifications) AVCC = 5.0 V 10%*1
Symbol VIH Measurement Max Unit Conditions VCC + 0.3 V VCC + 0.3 V AVCC + 0.3 V VCC + 0.3 V
Item Min Typ Input High voltage RES, STBY, VCC x 0.9 - EXTAL VCC x 0.9 - Port 7 VCC x 0.7 - Other input pins VCC x 0.7 - (except port 4) Input Low voltage RES, STBY, VIL -0.3 - VCC x 0.1 V MD2, MD1, MD0 Other input pins -0.3 - VCC x 0.15 V (except port 4) Schmitt trigger Port 4 VTVCC x 0.2 - VCC x 0.6 V input voltage VT+ VCC x 0.4 - VCC x 0.7 V +-VT- VCC x 0.07 - VT - V Input leakage RES | Iin | - - 10.0 A Vin = 0.5 to current STBY, NMI, - - 1.0 A VCC - 0.5 V MD2, MD1, MD0, port 7 Note: *1 AVCC must be connected to the power supply even when the A/D converter is not used.
297
Table 19-2 DC Characteristics (cont)
Symbol | ITSI | Measurement Unit Conditions A Vin = 0.5 to VCC - 0.5 V V V V V pF IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 2.6 mA Vin = 0 V f = 1 MHz Ta = 25C f = 5 MHz f = 5 MHz Ta 50C Ta > 50C
Item Leakage current in 3-state (off state) Output High voltage Output Low voltage Input copacitance
Port 8, ports 6 to 1 All output pins All output pins RES All input pins
Min -
Typ -
Max 1.0
VOH VOL Cin
VCC - 0.4 VCC - 0.9 - - -
- - - - -
- - 0.4 0.4 20
Current dissipation*1
Normal operation Sleep mode Standby
ICC
Analog supply current
During A/D AICC conversion While waiting - 0.01 5.0 A Note: *1 Current dissipation values assume that VIH min = VCC x 0.9 V, VIL max = 0.3 V and all output pins are in the no-load state. I CC (mA) Normal operation 20 Sleep mode
- - - - -
20 12 0.01 - 1.0
28 18 5.0 20.0 2.0
mA mA A A mA
15
10
5
0 2 3 4 5 6 VCC (V)
Figure 19-1 Relation between ICC and VCC
298
Table 19-3 Allowable Output Current Sink Values Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
Item Symbol Min Typ Max Unit Allowable output Low Per output pin IOL - - 2.0 mA current sink (per pin) Allowable output Low Total of all IOL - - 80 mA current sink (total) output pins Allowable output High All output pins -IOH - - 2.0 mA current sink (per pin) Allowable output High Total of all output -IOH - - 25 mA current sink (total) pins Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 19-3. In particular, when driving a Darlington transistor pair directly, be sure to insert a current-limiting resistor in the output path. See figure 19-2.
H8/510
2 k Port Darlington pair
Figure 19-2 Example of Circuit for Driving a Darlington Transistor Pair 19.2.2 AC Characteristics The AC characteristics of the H8/510 chip are listed in three tables. Bus timing parameters are given in table 20-4, control signal timing parameters in table 20-5, and timing parameters of the on-chip supporting modules in table 20-6.
299
Table 19-4 Bus Timing Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6 MHz Min Max 166.7 2000 65 - 65 - - 15 - 15 - 50 30 - - 50 - 50 110 - 110 - - 50 - 50 - 50 150 - 200 - 25 - 25 - 105 - 40 - 0 - - 160 - 300 - 81.7 - 230 - 70 30 - 30 - 40 - 10 - 40 - - 70 - 70 - tBACD1 300 8 MHz 10 MHz Min Max Min Max Unit 125 2000 100 2000 ns 45 - 40 - ns 45 - 40 - ns - 15 - 10 ns - 15 - 10 ns - 40 - 30 ns 25 - 15 - ns - 40 - 30 ns - 40 - 40 ns 85 - 70 - ns 85 - 70 - ns - 40 - 30 ns - 40 - 30 ns - 40 - 30 ns 110 - 90 - ns 150 - 120 - ns 20 - 15 - ns 20 - 15 - ns 80 - 65 - ns 30 - 20 - ns 0 - 0 - ns - 125 - 100 ns - 230 - 180 ns - 60 - 55 ns - 165 - 135 ns - 60 - 50 ns 15 - 10 - ns 25 - 20 - ns 40 - 40 - ns 10 - 10 - ns 40 - 40 - ns - 60 - 50 ns - 60 - 50 ns - tBACD1 - tBACD1 ns Measurement Conditions See figures 19-4 and 19-5
Item Clock cycle time Clock pulse width Low Clock pulse width High Clock rise time Clock fall time Address delay time Address hold time Read strobe delay time 1 Read strobe delay time 2 Read strobe width High 1 Read strobe width High 2 Write strobe delay time 1 Write strobe delay time 2 Write strobe delay time 3 Write data strobe pulse width1 Write data strobe pulse width2 Address setup time 1 Address setup time 2 Address setup time 3 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Write data delay time Write data setup time Write data hold time Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus floating delay time
Symbol tcyc tCL tCH tCr tCf tAD tAH1 tRDD1 tRDD2 tASH1 tASH2 tWRD1 tWRD2 tWRD3 tWRW1 tWRW2 tAS1 tAS2 tAS3 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tWDD tWDS tWDH tWTS tWTH tBRQS tBACD1 tBACD2 tBZD
See figure 19-6 See figure 19-11
Table 19-4 Bus Timing (cont)
6 MHz Symbol Min Max tED - 20 tER - 15 tEF - 15 tRDHE 0 - tWDHE 50 - 8 MHz Min Max - 15 - 15 - 15 0 - 40 - 10 MHz Min Max - 15 - 15 - 15 0 - 30 - Measurement Unit Conditions ns See figure 19-12 ns ns ns See figure 19-7 ns
Item E clock delay time E clock rise time E clock fall time Read data hold time (E clock sync) Write data hold time (E clock sync)
Conditions: VCC = 3.0 V to 5.5 V, o = 0.5 to 5.0 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications)
5 MHz Max 2000 - - 25 25 80 - - 80 120 80 80 80 - - - - - - - 180 350 120 - - Measurement Conditions See figures 19-4 and 19-5
Item Clock cycle time Clock pulse width Low Clock pulse width High Clock rise time Clock fall time Address delay time Address hold time (read) Address hold time (write) Read strobe delay time 1 Read strobe delay time 2 Write strobe delay time 1 Write strobe delay time 2 Write strobe delay time 3 Write data strobe pulse width1 Write data strobe pulse width2 Address setup time 1 Address setup time 2 Address setup time 3 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Write data delay time Write data setup time Write data hold time
Symbol tcyc tCL tCH tCr tCf tAD tAH1 tAH2 tRDD1 tRDD2 tWRD1 tWRD2 tWRD3 tWRW1 tWRW2 tAS1 tAS2 tAS3 tRDS tRDH tACC1 tACC2 tWDD tWDS tWDH
Min 200 60 60 - - - 5 20 - - - - - 150 220 30 30 130 50 0 - - - 10 40 301
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 19-4 Bus Timing (cont)
5 MHz Min Max 60 - 20 - 80 - - 80 - 80 - tBACD1 - 50 - 25 - 25 30 - 40 - Measurement Conditions See figure 19-6 See figure 19-11
Item Wait setup time Wait hold time Bus request setup time Bus acknowledge delay time 1 Bus acknowledge delay time 2 Bus floating delay time E clock delay time E clock rise time E clock fall time Read data hold time (E clock sync) Write data hold time (E clock sync)
Symbol tWTS tWTH tBRQS tBACD1 tBACD2 tBZD tED tER tEF tRDHE tWDHE
Unit ns ns ns ns ns ns ns ns ns ns ns
See figure 19-12
See figure 19-7
Table 19-5 Control Signal Timing Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6 MHz Min Max 200 - 6.0 - - 100 132 - 150 - 10 - 50 - 50 - 10 - 200 - 8 MHz Min Max 200 - 6.0 - - 100 132 - 150 - 10 - 50 - 50 - 10 - 200 - 10 MHz Min Max 200 - 6.0 - - 100 132 - 150 - 10 - 50 - 50 - 10 - 200 - Measurement Conditions See figure 19-8 See figure 19-8 See figure 19-10
Item RES setup time RES pulse width RES output delay time RES output pulse width NMI setup time NMI hold time IRQ0 setup time IRQ1 setup time IRQ1 hold time NMI pulse width (for recovery from software standby mode) Crystal oscillator settling time (reset) Crystal oscillator settling time (software standby)
Symbol tRESS tRESW tRESD tRESOW tNMIS tNMIH tIRQ0S tIRQ1S tIRQ1H tNMIW
Unit ns tcyc ns tcyc ns ns ns ns ns ns
tOSC1 tOSC2
20 10
- -
20 10
- -
20 10
- -
ms ms
See figure 19-11 See figure 18-1
302
Table 19-5 Control Signal Timing (cont) Conditions: VCC = 3.0 V to 5.5 V, o = 0.5 to 5.0 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications)
5 MHz Max - - 150 - - - - - - - Measurement Conditions See figure 19-8 See figure 19-8 See figure 19-10
Item RES setup time RES pulse width RES output delay time RES output pulse width NMI setup time NMI hold time IRQ0 setup time IRQ1 setup time IRQ1 hold time NMI pulse width (for recovery from software standby mode) Crystal oscillator settling time (reset) Crystal oscillator settling time (software standby)
Symbol tRESS tRESW tRESD tRESOW tNMIS tNMIH tIRQ0S tIRQ1S tIRQ1H tNMIW
Min 300 6.0 - 132 300 10 100 100 10 200
Unit ns tcyc ns tcyc ns ns ns ns ns ns
tOSC1 tOSC2
20 10
- -
ms ms
See figure 19-13 See figure 18-1
303
Table 19-6 Timing Conditions of On-Chip Supporting Modules Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, o = 0.5 to 10 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6 MHz Item FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer clock input setup time Timer clock pulse width Timer reset input setup time SCI Input clock cycle Input clock pulse width Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time Port Output data delay time Input data setup time Input data hold time RFSH Refresh output delay time 1 Refresh output delay time 2 (Sync) (Async) (Sync) tSCKW tTXD tRXS tRXH tPWD tPRS tPRH tRFD1 tRFD2 Symbol Min Max tFTOD tFTIS tFTCS tFTCW tTMOD tTMCS tTMCW tTMRS tScyc - 50 50 1.5 - 50 1.5 50 2 4 0.4 - 100 100 - 50 50 - - 100 - - - 100 - - - - - 0.6 100 - - 100 - - 50 50 - 50 50 1.5 - 50 1.5 50 2 4 0.4 - 100 100 - 50 50 - - 8 MHz Min Max 100 - - - 100 - - - - - 0.6 100 - - 100 - - 45 45 10 MHz - 50 50 1.5 - 50 1.5 50 2 4 0.4 - 100 - - - 100 - - - - - 0.6 100 ns ns ns tcyc ns ns tcyc ns tcyc tcyc tScyc ns ns ns ns ns ns ns ns See figure 19-22 See figure 19-14 See figure 19-21 See figure 19-19 See figure 19-20 See figure 19-17 See figure 19-18 See figure 19-16 Measurement See figure 19-15
Min Max Unit Conditions
100 - 100 - - 50 50 - - 100 - - 40 40
304
Table 19-6 Timing Conditions of On-Chip Supporting Modules (cont) Conditions: VCC = 3.0 V to 5.5 V, o = 0.5 to 5.0 MHz, VSS = 0 V Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
5 MHz Min Max - 150 80 - 80 - 1.5 - - 150 80 - 1.5 - 80 - 2 - 4 - 0.4 0.6 - 200 150 - 150 - - 150 80 - 80 - - 80 - 80 Measurement Conditions See figure 19-15 See figure 19-16 See figure 19-17 See figure 19-18 See figure 19-19 See figure 19-20
Item FRT
Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer clock input setup time Timer clock pulse width Timer reset input setup time SCI Input clock cycle (Async) (Sync) Input clock pulse width Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time (Sync) Port Output data delay time Input data setup time Input data hold time RFSH Refresh output delay time 1 Refresh output delay time 2
Symbol tFTOD tFTIS tFTCS tFTCW tTMOD tTMCS tTMCW tTMRS tScyc tSCKW tTXD tRXS tRXH tPWD tPRS tPRH tRFD1 tRFD2
Unit ns ns ns tcyc ns ns tcyc ns tcyc tcyc tScyc ns ns ns ns ns ns ns ns
See figure 19-21
See figure 19-14
See figure 19-22
* Measurement Conditions for AC Characteristics
5V
RL H8/510 output pin
C
RH
C = 90 pF: P1, P2, o, E, AS, RD, HWR, LWR, RFSH, A15 to A0 , D15 to D8 , = 30 pF: P3, P4, P5, P6, P7, P8 R L = 2.4 k R H = 12 k Input/output timing reference levels Low: 0.8 V High: 2.0 V
Figure 19-3 Output Load Circuit
305
19.2.3 A/D Converter Characteristics Table 19-7 lists the characteristics of the on-chip A/D converter. Table 19-7 A/D Converter Characteristics Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, Ta = -20 to +75C (Regular Specifications) Ta = -40 to +85C (Wide-Range Specifications)
6 MHz Typ 10 -- -- -- -- -- -- -- -- 8 MHz Typ 10 -- -- -- -- -- -- -- -- 10 MHz Min Typ Max 10 10 10 -- -- 13.4 -- -- 20 -- -- 10 -- -- 3 -- -- 2 -- -- 2 -- -- 1/2 -- -- 4
Item Resolution Conversion time Analog input capacitance Allowable signal-source impedance Nonlinearity error Offset error Full-scale error Quantizing error Absolute accuracy
Min 10 -- -- -- -- -- -- -- --
Max 10 22.33 20 10 3 2 2 1/2 4
Min 10 -- -- -- -- -- -- -- --
Max 10 16.75 20 10 3 2 2 1/2 4
Unit Bits s pF k LSB LSB LSB LSB LSB
Conditions: VCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to +75C (Regular Specifications) AVCC = 5.0 V 10%
5 MHz Typ 10 -- -- -- -- -- -- -- --
Item Resolution Conversion time Analog input capacitance Allowable signal-source impedance Nonlinearity error Offset error Full-scale error Quantizing error Absolute accuracy
Min 10 -- -- -- -- -- -- -- --
Max 10 26.8 20 10 3 2 2 1/2 4
Unit Bits s pF k LSB LSB LSB LSB LSB
306
19.3 MCU Operational Timing
This section provides the following timing charts: 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 Bus timing Control Signal Timing Clock Timing I/O Port Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing Serial Communication Interface Timing Refresh Timing Figures 19-4 to 19-7 Figures 19-8 to 19-11 Figures 19-12 and 19-13 Figure 19-14 Figures 19-15 and 19-16 Figures 19-17 to 19-19 Figures 19-20 and 19-21 Figures 19-22 and 19-23
19.3.1 Bus Timing 1. Basic Bus Cycle (Two-State Mode)
T1 tcyc tCH o tcf t AD A 23 to A0 t RDD2 t RDD1 AS, RD (Read) t AS1 t ACC3 tRDS tACC1 D15 to D0 (Read) tRDH t AH t ASH1 tcr tCL T2
tWRD1 tWRW1
tWRD2 tAH
HWR, LWR (Write)
tAS2 tWDD tWDH
D15 to D0 (Write)
Figure 19-4 Basic Bus Cycle (Two-State Mode)
307
2. Basic Bus Cycle (Three-State Mode)
T1 T2 T3
o
A 23 to A0
AS, RD (Read) tACC4 tACC2 D15 to D0 (Read) tAS3 HWR, LWR (Write) tWRD3 tWRW2
tASH2
tWDS
D15 to D0 (Write)
Figure 19-5 Basic Bus Cycle (Three-State Mode)
308
3. Basic Bus Cycle (Three-State Mode with One Wait State)
T1
T2
TW
T3
o
A 23 to A0
AS, RD (Read)
D15 to D0 (Read)
HWR, LWR (Write)
D15 to D0 (Write) tWTS tWTH tWTS tWTH
WAIT
Figure 19-6 Basic Bus Cycle (Three-State Mode with One Wait State)
309
4. Bus Cycle Synchronized with E Clock
o tED E
A 23 to A0 tRDD2 tAH AS, RD (Read)
tRDS tRDHE
D15 to D8 (Read) tWRD2 AS, HWR (Write) tWDHE D15 to D8 (Write) tAH
Figure 19-7 Bus Cycle Synchronized with E Clock
310
19.3.2 Control Signal Timing 1. Reset Input Timing
o tRESS RES tRESW tRESS
Figure 19-8 Reset Input Timing 2. Reset Output Timing
o tRESD tRESD
RES tRESDW
Figure 19-9 Reset Output Timing 3. Interrupt Input Timing
o tNMIS NMI tIRQIS IRQ 1 to IRQ 3 tIRQ0S IRQ0 tIRQIH tNMIH
Figure 19-10 Interrupt Input Timing
311
4. Bus Release State Timing
o BREQ (Input)
tBRQS
tBRQS
tBACD1 BACK (Output) tBZD A 23 to A0 , RD, HWR, LWR
tBACD2
tAD
Figure 19-11 Bus Release State Timing 19.3.3 Clock Timing 1. E Clock Timing
o tED E tEF tER tED
Figure 19-12 E Clock Timing
312
2. Clock Oscillator Stabilization Timing
STBY
tOSC1
tOSC1
Figure 19-13 Clock Oscillator Stabilization Timing
313
RES
VCC
o
19.3.4 I/O Port Timing
Port read/write cycle T1 T2 T3
o tPRS Port 1 to (Input) port 8 Port 1 * to (Output) port 8 * Except P77 to P70 tPRH
tPWD
Figure 19-14 I/O Port Input/Output Timing 19.3.5 16-Bit Free-Running Timer Timing 1. Free-Running Timer Input/Output Timing
o
Free-running timer counter
Compare-match tFTOD
FTOA 1 , FTOB 1 , FTOA 2 , FTOB 2 , tFTIS
FTI 1, FTI 2
Figure 19-15 Free-Running Timer Input/Output Timing
314
2. External Clock Input Timing for Free-Running Timers
o tFTCS FTCI1 FTCI2 tFTCWL tFTCWH
Figure 19-16 External Clock Input Timing for Free-Running Timers 19.3.6 8-Bit Timer Timing 1. 8-Bit Timer Output Timing
o
Timer counter
Compare-match tTMOD
TMO
Figure 19-17 8-Bit Timer Output Timing 2. 8-Bit Timer Clock Input Timing
o tTMCS TMCI tTMCWL tTMCWH tTMCS
Figure 19-18 8-Bit Timer Clock Input Timing
315
3. 8-Bit Timer Reset Input Timing
o tTMRS TMRI
Timer counter
n
H'00
Figure 19-19 8-Bit Timer Reset Input Timing 19.3.7 Serial Communication Interface Timing
tSCKW
tScyc
Figure 19-20 SCI Input Clock Timing
tScyc Serial clock tTXD Transmit data tRXS Receive data tRXH
Figure 19-21 SCI Input/Output Timing (Synchronous Mode)
316
19.3.8 Refresh Timing 1. Basic Refresh Bus Cycle
o
A 23 to A0
AS tRFD1 RFSH tRFD2
Figure 19-22 Basic Refresh Bus Cycle 2. Refresh Timing (Wait Cycle)
TR1 o
TRW
TRW
TR2
tWTS WAIT
tWTH
tWTS
tWTH
Figure 19-23 Refresh Timing (Wait Cycle)
317
Appendix A Instructions
A.1 Instruction Set
Operation Notation Rd Rs Rn (EAd) (EAs) CCR N Z V C CR PC CP SP General register (destination operand) General register (source operand) General register Destination operand Source operand Condition code register N (Negative) flag in CCR Z (Zero) flag in CCR V (Overflow) flag in CCR C (Carry) flag in CCR Control register Program counter Code page register Stack pointer FP #IMM disp + - x / Frame pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Move Swap Logical NOT
Condition Code Notation 0 1 -- Changed after instruction execution Cleared to 0 Set to 1 Value before opration is retained Changed depending on condition
319
Mnemonic Data MOV: G transfer
Arithmetic operations
Operation (EAs) Rd Rs (EAd) #IMM (EAd) MOV: E #IMM Rd (short format) MOV: F @ (d: 8, FP) Rd Rs @ (d: 8, FP)(short format) MOV: I #IMM Rd (short format) MOV: L (@aa: 8) Rd (short format) MOV: S Rs (@aa: 8) (short format) LDM @ SP + Rn (register list) STM Rn (register list) @ - SP XCH Rs Rd SWAP Rd (upper byte) Rd (lower byte) MOVTPE Rs (EAd) Synchronized with E clock MOVFPE (EAs) Rd Synchronized with E clock ADD: G Rd + (EAs) Rd ADD: Q (EAd) + #IMM (EAd) (#IMM = 1, 2) (short format) ADDS Rd + (EAs) Rd (Rd is always word size) ADDX Rd + (EAs) + C Rd DADD (Rd)10 + (Rs)10 + C (Rd)10 SUB Rd - (EAs) Rd SUBS Rd - (EAs) Rd SUBX Rd - (EAs) - C Rd DSUB (Rd)10 - (Rs)10 - C (Rd)10 MULXU Rd x (EAs) Rd 8 x 8 (Unsigned)16 x 16 DIVXU Rd / (EAs) Rd 16 / 8 (Unsigned)32 / 16 CMP: G Rd - (EAs), Set CCR (EAd) - #IMM, Set CCR CMP: E Rd - #IMM, Set CCR (short format) CMP: I Rd - #IMM, Set CCR (short format)
Size CCR Bits B/W N Z V C B/W 0--
B B/W W B/W B/W W W W B B B B/W B/W -- -- -- -- --
-- -- -- -- --
0 0 0 0 0 -- -- -- 0 -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- 0 0
B/W -- B/W B B/W B/W B/W B B/W -- -- --
---- -- -- -- -- 0
B/W B/W B W
320
Mnemonic ArithEXTS metic opera- EXTU tions TST NEG CLR TAS Shift operations SHAL
Operation (< Bit 7 > of < Rd >) (< Bit 15 to 8 > of < Rd >) 0 ( of < Rd >) (EAd) - 0, Set CCR 0 - (EAd) (EAd) 0 (EAd) (EAd) - 0, Set CCR (1)2 (< Bit 7 > of < EAd >)
MSB C LSB 0 MSB LSB C
Size CCR Bits B/W N Z V B 0 B B/W B/W B/W B 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- --
C 0 0 0 0 0 -- -- -- -- -- -- -- --
B/W B/W B/W
0
SHAR SHLL
C
MSB
LSB
SHLR
0
MSB
LSB C
B/W 0 B/W B/W
C
ROTL
C
MSB
LSB
ROTR ROTXL
C
MSB
LSB
MSB
LSB
B/W B/W
C
ROTXR Logic operations AND OR XOR NOT BSET
MSB
LSB
Bit manipulations BCLR BTST BNOT
Rd (EAs) Rd Rd (EAs) Rd Rd (EAs) Rd (EAd) (EAd) (< Bit number > of < EAd >) Z 1 (< Bit number > of < EAd >) (< Bit number > of < EAd >) Z 0 (< Bit number > of < EAd >) (< Bit number > of < EAd >) Z (< Bit number > of < EAd >) Z (< Bit number > of < EAd >)
B/W B/W B/W B/W B/W
--
B/W -- B/W -- B/W --
321
Mnemonic Branch- Bcc ing instructions
Operation If condition is true then PC + disp PC else next;
Mnemonic BRA BRN BHI BLS Bcc BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE (BT) (BF) Description Always (True) Never (False) HIgh Low or Same Carry Clear (High or Same) Carry Set (LOw) Not Equal EQual oVerflow Clear oVerflow Set PLus MInus Greater or Equal Less Than Greater Than Less or Equal
Size CCR Bits B/W N Z V C -- --------
(BHS) (BLO)
Condition True False CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1
Effective address PC Effective address CP, PC PC @ - SP PC + disp PC JSR PC @ - SP Effective address PC PJSR PC @ - SP CP @ - SP Effective address CP, PC RTS @ SP + PC PRTS @ SP + CP @ SP + PC RTD @ SP + PC SP + #IMM SP PRTD @ SP + CP @ SP + PC SP + #IMM SP SCB If condition is true then next; SCB/F else Rn - 1 Rn; SCB/NE If Rn = -1 then next; SCB/EQ else PC + disp PC; JMP PJMP BSR
Mnemonic SCB/F SCB/NE SCB/EQ Description Not Equal Equal Condition False Z=0 Z=1
-- -- -- -- --
---- ---- ---- -- -- -- --
---- ---- ---- -- -- -- --
-- -- -- --
---- ---- -- -- -- --
---- ---- -- -- -- --
--
--
--
--
--
322
Mnemonic System TRAPA control
Operation PC @ - SP (If MAX MODE CP @ - SP) SR @ - SP (If MAX MODE < vector > CP) < vector > PC TRAP/VS If V bit = 1 then TRAP else next; RTE @ SP + SR (If MAX MODE @ SP + CP) @ SP + PC LINK FP (R6) @ - SP SP FP (R6) SP + #IMM SP UNLK FP (R6) SP @SP + FP SLEEP Normal running mode power-down state LDC (EAs) CR STC CR (EAd) ANDC CR #IMM CR ORC CR #IMM CR XORC CR #IMM CR NOP PC + 1 PC
Size B/W --
N --
CCR Bits ZVC ------
-- --
--
--
--
--
--
--
--
--
--
--
--
--
-- -- --
-- -- --
-- ---- B/W* B/W* -- -- B/W* B/W* B/W* -- ----
--
--
* Depends on the CR.
323
A.2 Instruction Codes
Table A-1 shows the machine-language coding of each instruction. * How to Read Table A-1 (a) to (d) The general operand format consists of an effective address (EA) field and operation-code (OP) field specified in the following order.
EA field OP field
1
2
3
4
5
6
Bytes 2, 3, 5, 6 are not present in all instructions.
324
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
disp (L)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
3
@Rn
Instruction Rn MOV:G.B , R d Instruction MOV:G.W , R d MOV:G.B R s , MOV:G.W R s , 2 2
#xx:8
Operation code (OP) 4 1 0 0 0 0 rd r d rd 5 6
2 2 2 2
3 3 3 3
4 4 4 4
2 2 2 2
2 2 2 2
3 3 3 3
4 4 4 4
3
4 1 0 0 0 0 rd r d rd 1 0 0 1 0 rs r s rs 1 0 0 1 0 rs r s rs Shading indicates addressing modes not available for this instruction.
Byte length of instruction
Some instructions have a special format in which the operation code comes first.
Some instructions have a special format in which the operation code comes first.
The following notation is used in the tables.
The following notation is used in the tables.
* Sz: Operand size (byte or word) Byte: Sz = 0 size (byte or word) * Sz: Operand Word: Sz ==1 Byte: Sz 0
Word: Sz = 1
325
* rrr : General register number field
rrr 15 000 001 010 011 100 101 110 111 Not used Not used Not used Not used Not used Not used Not used Not used Sz = 0 (Byte) 87 R0 R1 R2 R3 R4 R5 R6 R7 0 15 R0 R1 R2 R3 R4 R5 R6 R7 Sz = 1 (Word) 0
* ccc : Control register number field
ccc 000 15 001 010 011 100 101 110 111 Not used Sz = 0 (Byte) (Not allowed*) 87 CCR (Not allowed) Not used Not used Not used (Not allowed) Not used TP BR EP DP 0 15 SR (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed) (Not allowed) Sz = 1 (Word) 0
* "Not allowed" means that this combination of bits must not be specified. Specifying a disallowed combination may cause abnormal results.
326
* d: Transfer direction Load when d = 0 Store when d = 1 * register list: A byte in which bits indicate general registers as follows
Bit 7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0
* #VEC: Four bits designating a vector number from 0 to 15. The vector numbers correspond to addresses of entries in the exception vector table as follows:
Vector Address Minimum Mode Maximum Mode H'0020 - H'0021 H'0040 - H'0043 H'0022 - H'0023 H'0044 - H'0047 H'0024 - H'0025 H'0048 - H'004B H'0026 - H'0027 H'004C - H'004F H'0028 - H'0029 H'0050 - H'0053 H'002A - H'002B H'0054 - H'0057 H'002C - H'002D H'0058 - H'005B H'002E - H'002F H'005C - H'005F Vector Address Minimum Mode Maximum Mode H'0030 - H'0031 H'0060 - H'0063 H'0032 - H'0033 H'0064 - H'0067 H'0034 - H'0035 H'0068 - H'006B H'0036 - H'0037 H'006C - H'006F H'0038 - H'0039 H'0070 - H'0073 H'003A - H'003B H'0074 - H'0077 H'003C - H'003D H'0078 - H'007B H'003E - H'003F H'007C - H'007F
#VEC 0 1 2 3 4 5 6 7
#VEC 8 9 A B C D E F
* Example of machine-language coding Example 1: ADD:G.B @R0, R1
Table A-1 (a) Machine code EA Field OP Field 11 0 1 S z r r r 00100rrr 11 0 1 0 0 0 0 0 0 1 0 0 001 H'D021
Sz = 0 (Byte) Rs = R0, Rd = R1
Example 2: ADD:G.W @H'11:8, R1
Table A-1 (a) Machine code EA Field 0000Sz101 00010001 0 0 0 0 11 0 1 00010001 H'0D1121 OP Field 00100rrr 0 0 1 0 0 001
327
Table A-1 (a) Machine Language Coding [General Format]
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn MOV:G.B , Rd MOV:G.W , Rd MOV:G.B Rs , Data transfer instruction MOV:G.W Rs , MOV:G.B #xx:8, MOV:G.W #xx:8, MOV:G.W #xx:16, LDM.W @SP+, STM.W XCH.W Rs ,Rd SWAP.B Rd MOVTPE.B Rs , MOVFPE.B , Rd ADD:G.B , Rd ADD:G.W , Rd Arithmetic operation instruction ADD:Q.B #1, * ADD:Q.W #1, * ADD:Q.B #2, * ADD:Q.W #2, * ADD:Q.B #-1, * ADD:Q.W #-1, * ADD:Q.B #-2, * ADD:Q.W #-2, * ADDS.B , Rd ADDS.W , Rd ADDX.B , Rd ADDX.W , Rd * Short format instruction 2 2 2 2 2 2 2 2 2 2 2 2 2 2
,@-SP
#xx:8
Operation code (OP) 4 1 0 0 0 0 rd rd rd 5 6
2 2
2 2 2 2 3 3 4
3 3 3 3 4 4 5
4 4 4 4 5 5 6
2 2 2 2 3 3 4 2
2 2 2 2 3 3 4 2
3 3 3 3 4 4 5
4 4 4 4 5 5 6
3
4 1 0 0 0 0 rd rd rd 1 0 0 1 0 rs rs rs 1 0 0 1 0 rs rs rs 0 0 0 0 0 1 1 0 data 0 0 0 0 0 1 1 0 data 0 0 0 0 0 1 1 1 data (H) 0 0 0 0 0 0 1 0 register list 0 0 0 1 0 0 1 0 register list 1 0 0 1 0 rd rd rd 00010000 data (L)
2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3
0 0 0 0 0 0 0 0 1 0 0 1 0 rs rs rs 0 0 0 0 0 0 0 0 1 0 0 0 0 rd rd rd 0 0 1 0 0 rd rd rd 4 0 0 1 0 0 rd rd rd 00001000 00001000 00001001 00001001 00001100 00001100 00001101 00001101 0 0 1 0 1 rd rd rd 4 0 0 1 0 1 rd rd rd 1 0 1 0 0 rd rd rd 4 1 0 1 0 0 rd rd rd
328
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn DADD.B Rs ,Rd SUB.B , R d SUB.W , R d SUBS.B , R d SUBS.W ,Rd SUBX.B , Rd SUBX.W , R d DSUB.B R s , R d Arithmetic operation instruction MULXU.B , R d MULXU.W , Rd DIVXU.B , Rd DIVXU.W , R d CMP:G.B , Rd CMP:G.W , R d CMP:G.B #xx, CMP:G.W #xx, EXTS.B Rd EXTU.B Rd TST.B TST.W NEG.B NEG.W CLR.B CLR.W TAS.B 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 3 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 0 0 1 1 0 rd rd rd 5 6
0 0 0 0 0 0 0 0 1 0 1 0 0 rd rd rd 2 2 2 2 2 2 2 2 2 2 2 2 3 4 3 3 3 3 3 3 3 3 3 3 3 3 4 5 4 4 4 4 4 4 4 4 4 4 4 4 5 6 2 2 2 2 2 2 2 2 2 2 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 3 4 3 3 3 3 3 3 3 3 3 3 3 3 4 5 4 4 4 4 4 4 4 4 4 4 4 4 5 6 3 3 3 3 3 3 4 0 0 1 1 0 rd rd rd 0 0 1 1 1 rd rd rd 4 0 0 1 1 1 rd rd rd 1 0 1 1 0 rd rd rd 4 1 0 1 1 0 rd rd rd 0 0 0 0 0 0 0 0 1 0 1 1 0 rd rd rd 1 0 1 0 1 rd rd rd 4 1 0 1 0 1 rd rd rd 1 0 1 1 1 rd rd rd 4 1 0 1 1 1 rd rd rd 0 1 1 1 0 rd rd rd 4 0 1 1 1 0 rd rd rd 0 0 0 0 0 1 0 0 data 0 0 0 0 0 1 0 1 data (H) 00010001 00010010 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 4 4 4 4 4 4 4 00010110 00010110 00010100 00010100 00010011 00010011 00010111 data (L)
329
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn SHAL.B SHAL.W SHAR.B SHAR.W SHLL.B SHLL.W Shift instruction SHLR.B SHLR.W ROTL.B ROTL.W ROTR.B ROTR.W ROTXL.B ROTXL.W ROTXR.B ROTXR.W Logic operation instruction AND.B , Rd AND.W , Rd OR.B , Rd OR.W , Rd XOR.B , Rd XOR.W , Rd NOT.B NOT.W 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 00011000 00011000 00011001 00011001 00011010 00011010 00011011 00011011 00011100 00011100 00011101 00011101 00011110 00011110 00011111 00011111 5 6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3
0 1 0 1 0 rd rd rd 4 0 1 0 1 0 rd rd rd 0 1 0 0 0 rd rd rd 4 0 1 0 0 0 rd rd rd 0 1 1 0 0 rd rd rd 4 0 1 1 0 0 rd rd rd 00010101 00010101
330
Table A-1 (a) Machine Language Coding [General Format] (cont)
address (L) address (H) 0 0 0 1 Sz 1 0 1 @aa:16 address 0 0 0 0 Sz 1 0 1 0000 0 100 data 1 0 1 1 Sz r r r 1 1 0 0 Sz r r r @aa:8 @Rn+ @-Rn
Operation code (EA)
Addressing mode
@(d:16, Rn)
@(d:8, Rn)
#xx:16
0000 1 100
1 0 1 0 Sz r r r
1 1 0 1 Sz r r r
1 1 1 0 Sz r r r
1 1 1 1 Sz r r r
1
data (H)
disp (H)
2
disp
data (L)
disp (L)
3
@Rn
Instruction Rn BSET.B #xx, BSET.W #xx, BSET.B R s , BSET.W Rs , Bit manipulate instruction BCLR.B #xx, BCLR.W #xx, BCLR.B Rs , BCLR.W Rs , BTST.B #xx, BTST.W #xx, BTST.B Rs , BTST.W Rs , BNOT.B #xx, BNOT.W #xx, BNOT.B R s , BNOT.W Rs , LDC.B , CR System control instruction LDC.W , CR STC.B CR, STC.W CR, ANDC.B #xx:8, CR ANDC.W #xx:16, CR ORC.B #xx:8, CR ORC.W #xx:16, CR XORC.B #xx:8, CR XORC.W #xx:16, CR 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
#xx:8
Operation code (OP) 4 1 1 0 0 (data) 1 1 0 0 (data) 0 1 0 0 1 rs rs rs 0 1 0 0 1 rs rs rs 1 1 0 1 (data) 1 1 0 1 (data) 0 1 0 1 1 rs rs rs 0 1 0 1 1 rs rs rs 1 1 1 1 (data) 1 1 1 1 (data) 0 1 1 1 1 rs rs rs 0 1 1 1 1 rs rs rs 1 1 1 0 (data) 1 1 1 0 (data) 0 1 1 0 1 rs rs rs 0 1 1 0 1 rs rs rs 5 6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3
10001ccc 4 10001ccc 10011ccc 10011ccc 01011ccc 4 01011ccc 01001ccc 4 01001ccc 01101ccc 4 01101ccc
331
Table A-1 (b) Machine Language Coding [Special Format: Short Format]
Instrunction MOV:E.B #xx:8,Rd MOV:I.W #xx:16,Rd MOV:L.B @aa:8,Rd MOV:L.W @aa:8,Rd MOV:S.B Rs,@aa:8 MOV:S.W Rs,@aa:8 MOV:F.B @(d:8,R6),Rd MOV:F.W @(d:8,R6),Rd MOV:F.B Rs, @(d:8,R6) MOV:F.W Rs,@(d:8,R6) CMP:E #xx:8,Rd CMP:I #xx:16,Rd Byte 2 3 2 2 2 2 2 2 2 2 2 3 Operation code 2 3 data data (H) address (L) address (L) address (L) address (L) disp disp disp disp data data (H) data (L)
1 01010rdrdrd 01011rdrdrd 01100rdrdrd 01101rdrdrd 01110rsrsrs 01111rsrsrs 10000rdrdrd 10001rdrdrd 10010rsrsrs 10011rsrsrs 01000rdrdrd 01001rdrdrd
4
data (L)
332
Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction]
Instrunction Bcc d:8 BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Byte 2 Operation code 2 3 disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) disp (H) 11010rrr address (H)
Bcc d:16
3
JMP @Rn JMP @aa:16
2 3
1 00100000 00100001 00100010 00100011 00100100 00100101 00100110 00100111 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 00110101 00110110 00110111 00111000 00111001 00111010 00111011 00111100 00111101 00111110 00111111 00010001 00010000
4
disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) disp (L) address (L)
333
Table A-1 (c) Machine Language Coding [Special Format: Branch Instruction]
Instrunction JMP @(d:8,Rn) JMP @(d:16,Rn) BSR d:8 BSR d:16 JSR @Rn JSR @aa:16 JSR @(d:8,Rn) JSR @(d:16,Rn) RTS RTD #xx:8 RTD #xx:16 SCB/cc Rn,disp SCB/F SCB/NE SCB/EQ PJMP @aa:24 PJMP @Rn PJSR @aa:24 PJSR @Rn PRTS PRTD #xx:8 PRTD #xx:16 Byte 3 4 2 3 2 3 3 4 1 2 3 3 Operation code 2 3 11100rrr disp 11110rrr disp (H) disp disp (H) disp (L) 11011rrr address (H) address (L) 11101rrr disp 11111rrr disp (H) data data (H) 10111rrr 10111rrr 10111rrr page 11000rrr page 11001rrr 00011001 00010100 00011100
4 2 4 2 2 3 4
1 00010001 00010001 00001110 00011110 00010001 00011000 00010001 00010001 00011001 00010100 00011100 00000001 00000110 00000111 00010011 00010001 00000011 00010001 00010001 00010001 00010001
4 disp (L)
disp (L)
data (L) disp disp disp address (H) address (H)
address (L) address (L)
data data (H)
data (L)
Table A-1 (d) Machine Language Coding [Special Format: System Control Instructions]
Instrunction TRAPA #xx TRAP/VS RTE LINK FP,#xx:8 LINK FP,#xx:16 UNLK FP SLEEP NOP Byte 2 1 1 2 3 1 1 1 Operation code 2 3 0001 #VEC
1 00001000 00001001 00001010 00010111 00011111 00001111 00011010 00000000
4
data data (H)
data (L)
334
A.3 Operation Code Map
Tables A-2 through A-6 are maps of the operation codes. Table A-2 shows the meaning of the first byte of the instruction code, indicating both operation codes and addressing modes. Tables A-2 through A-6 indicate the meanings of operation codes in the second and third bytes. Table A-2 Operation Code in Byte 1
LO HI 0 0 NOP 1 SCB/F See Tbl. A-6 See Tbl. A-6 * BRN BRN 2 LDM 3 PJSR @aa:24 4 #xx:8 See Tbl. A-5 RTD #xx:8 5 #aa:8.B See Tbl. A-4
@aa:16.B
6 SCB/NE See Tbl. A-6
JMP 1
STM
PJMP @aa:24
2 3
BRA d:8 BRA d:16 R0
BHI BHI
BLS BLS
Bcc Bcc
See Tbl. A-4 BCS BCS
7 8 SCB/EQ TRAPA See Tbl. A-6 LINK JSR #xx:8
9 TRAP/V S
A RTE
B
RTS
SLEEP
C #xx:16 See Tbl. A-5 RTD #xx:16
D
@aa:8.W
See Tbl. A-4
@aa:16.W
E BSR d:8
F UNLK
BNE BNE
BEQ BEQ
BVC BVC
BVS BVS
BPL BPL
BMI BMI
BGE BGE
See Tbl. A-4 BLT BLT
BSR d:16
LINK #xx:16
BGT BGT
BLE BLE
4 5 6 7 8 9 A B C D E F
R1
CMP:E #xx:8, Rn R2 R3 R4 MOV:E #xx:8, Rn MOV:L.B @aa:8, Rn MOV:S.B Rn, @aa:8 MOV:F.B @ (d:8, R6), Rn MOV:F.B Rn, @ (d:8, R6) Rn @-Rn @Rn+ @Rn @(d:8,Rn) @(d:16,Rn)
R5
R6
R7
R0
R1
(Byte) (Byte) (Byte) (Byte) (Byte) (Byte)
See table A-3 See table A-4 See table A-4 See table A-4 See table A-4 See table A-4
CMP:I #xx:16, Rn R2 R3 R4 R5 MOV:I #xx:16, Rn MOV:L.W @aa:8, Rn MOV:S.W Rn, @aa:8 MOV:F.W @ (d:8, R6), Rn MOV:F.W Rn, @ (d:8,R6) (Word) Rn (Word) @-Rn (Word) @Rn+ (Word) @Rn (Word) @(d:8,Rn) (Word) @(d:16,Rn)
R6
R7
See table A-3 See table A-4 See table A-4 See table A-4 See table A-4 See table A-4
Notes: References to tables A-3 through A-6 indicate that the instruction code has one or more additional bytes, described in those tables. * H'11 is the first operation code byte of the following instructions: JMP,JSR, PJSR (register indirect addressing mode) JMP,JSR (register indirect addressing mode with displacement) PRTS, PRTD (all addressing modes)
Table A-3 Operation Code in Byte 2 (Axxx)
LO HI 0 1 2 R0 3 4 5 6 7 8 9 A B C D E F Note: * The operation code is in byte 3, given in table A-6. b0 b1 b2 R1 R2 0 See Tbl. A-6* SWAP 1 2 3 4 5 6 7 8 ADD:Q #1 EXTS EXTU CLR ADD R3 SUB OR AND XOR CMP MOV XCH ADDX SUBX NEG R4 NOT R5 TST R6 TAS R7 SHAL R0 9 ADD:Q #2 SHAR R1 SHLL ADDS R2 SUBS BSET (Register indirect specification of bit number) BCLR (Register indirect specification of bit number) BNOT (Register indirect specification of bit number) BTST (Register indirect specification of bit number) LDC STC MULXU DIVXU BSET (Immediate specification of bit number) b6 b7 b8 b9 b10 BCLR (Immediate specification of bit number) BNOT (Immediate specification of bit number) BTST (Immediate specification of bit number) SHLR R3 A B C ADD:Q #-1 ROTL R4 D ADD:Q #-2 ROTR R5 ROTXL R6 ROTXR R7 E F
b3
b4
b5
b11
b12
b13
b14
b15
Table A-4 Operation Code in Byte 2 (05xx, 15xx, 0Dxx, 1Dxx, Bxxx, Cxxx, Dxxx, Exxx, Fxxx)
LO HI 0 1 2 3 4 5 6 7 8 9 A B C b0 D E F b1 b2 b3 b4 b5 R0 R1 R2 0 See Tbl. A-6* 1 2 3 4 CMP #xx:8 CLR ADD R3 SUB OR AND XOR CMP MOV MOV ADDX SUBX (load) (store) NEG R4 5 CMP #xx:16 NOT R5 6 MOV #xx:8 TST R6 7 MOV #xx:16 TAS R7 8 ADD:Q #1 SHAL R0 9 ADD:Q #2 SHAR SHLL SHLR R3 A B C ADD:Q #-1 ROTL R4 D ADD:Q #-2 ROTR R5 ROTXL R6 ROTXR R7 E F
ADDS R1 R2 SUBS
BSET (Register indirect specification of bit number) BCLR (Register indirect specification of bit number) BNOT (Register indirect specification of bit number) BTST (Register indirect specification of bit number) LDC STC MULXU DIVXU BSET (Immediate specification of bit number) b6 b7 b8 b9 b10 BCLR (Immediate specification of bit number) BNOT (Immediate specification of bit number) BTST (Immediate specification of bit number) b11 b12 b13 b14 b15
Note: * The operation code is in byte 3, given in table A-6.
Table A-5 Operation Code in Byte 2 (04xx, 0Cxx)
LO HI 0 1 2 3 4 5 6 7 8 9 A B C D E F ADDX SUBX MULXU DIVXU R0 R1 R2 ADD R3 SUB OR AND XOR CMP MOV LDC R4 R5 R6 R7 R0 R1 R2 ADDS R3 SUBS ORC ANDC XORC R4 R5 R6 R7 0 1 2 3 4 5 6 7 8 9 A B C D E F
Table A-6 Operation Code in Byte 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx)
LO HI 0 1 2 3 4 5 6 7 8 9 A B C D E F MOVFPE R3 MOVTPE DADD DSUB PJMP @Rn JMP @Rn JMP @(d:8,Rn) JMP @(d:16,Rn) R0 R1 SCB R2 R3 R4 R5 R6 R7 PRTD #xx:8 PRTS PRTD #xx:16 0 1 2 3 4 5 6 7 8 9 A B C D E F
R0
R1
R2
R4
R5
R6
R7
PJSR @Rn JSR @Rn JSR @(d:8,Rn) JSR @(d:16,Rn)
A.4 Instruction Execution Cycles
Tables A-7 (1) through (6) list the number of cycles required by the CPU to execute each instruction in each addressing mode. The meaning of the symbols in the tables is explained below. The values of I, J, and K are used to calculate the number of execution cycles needed to fetch an instruction or read or write an operand that is not located in the memory area accessed in two states via a 16-bit bus. The formulas for these calculations are given next. * Calculation on Instruction Execution States One state is one cycle of the system clock (o). When o = 10 MHz, one state is 100 ns.
Instruction Fetch 16-Bit bus, 2-state-access memory area
Operand Read/Write 16-Bit bus, 2-state-access memory area or general register 16-Bit bus, 3-state-access memory area
8-Bit bus, 2-state-access memory area
8-Bit bus, 3-state-access memory area or on-chip supporting module
Number of States (Value in table A-7) + (Value in table A-8) Byte (Value in table A-7) + (Value in table A-8) + I Word (Value in table A-7) + (Value in table A-8) + I/2 Byte (Value in table A-7) + (Value in table A-8) Word ((Value in table A-7) + (Value in table A-8) + I Byte (Value in table A-7) + (Value in table A-8) + I Word (Value in table A-7) + (Value in table A-8) + 2I
340
Instruction Fetch 16-Bit bus, 3-state-access memory area
Operand Read/Write 16-Bit bus, 2-state-access memory area or general register 16-Bit bus, 3-state-access memory area
8-Bit bus, 2-state-access memory area
8-Bit bus, 3-state-access memory area or on-chip supporting module
8-Bit bus, 2-state-access memory area
16-Bit bus, 2-state-access memory area or general register 16-Bit bus, 3-state-access memory area
Number of States (Value in table A-7) + (Value in table A-8) + (J + K) / 2 Byte (Value in table A-7) + (Value in table A-8) + I + (J + K) / 2 Word (Value in table A-7) + (Value in table A-8) + (I + J + K) / 2 Byte (Value in table A-7) + (Value in table A-8) + (J + K) / 2 Word (Value in table A-7) + (Value in table A-8) + I + (J + K) / 2 Byte (Value in table A-7) + (Value in table A-8) + I + (J + K) / 2 Word (Value in table A-7) + (Value in table A-8) + 2I + (J + K) / 2 (Value in table A-7) + J + K Byte Word (Value in table A-7) + I+J+K (Value in table A-7) + I/2 + J + K (Value in table A-7) + J+K (Value in table A-7) + I+J+K (Value in table A-7) + I+J+K (Value in table A-7) + 2I + J + K
8-Bit bus, 2-state-access memory area
Byte Word
8-Bit bus, 3-state-access memory area or on-chip supporting module
Byte Word
341
Instruction Fetch 8-Bit bus, 3-state-access memory area
Operand Read/Write 16-Bit bus, 2-state-access memory area or general register 16-Bit bus, 3-state-access memory area
Number of States (Value in table A-7) + 2(J + K) Byte Word (Value in table A-7) + I + 2(J + K) (Value in table A-7) + I/2 + 2(J + K) (Value in table A-7) + 2(J + K) (Value in table A-7) + I + 2(J + K) (Value in table A-7) + I + 2(J + K) (Value in table A-7) + 2(I + J + K)
8-Bit bus, 2-state-access memory area
Byte Word
8-Bit bus, 3-state-access memory area or on-chip supporting module
Byte Word
Notes: 1. When an instruction is fetched via a 16-bit bus, the number of execution states vairies by 1 or 2 depending on whether the instruction is stored at an even or odd address. This difference must be noted when software is used for timing, and in other cases in which the exact number of states is important. 2. If wait states or TP states are inserted in access to the three-state-access memory area, add the necessary number of states. 3. When an instruction is fetched from a memory area that is accessed via a 16-bit bus in three states, fractions in the term (J + K)/2 should be rounded down.
342
* Tables of Instruction Execution Cycles Tables A-7 (1) through (6) should be read as shown below:
J + K: Number of instruction fetch cycles. Addressing mode @(d:16, Rn) @(d:8, Rn) I: Total number of bytes written and read when operand is in memory. Rn
@aa:16
@aa:8
Instruction ADD.B ADD.W ADD:Q.B ADD:Q.W DADD
I 1 2 2 4
J 1 1 1 1 2
K
1 2 2 2 2 4
1 5 5 7 7
2 5 5 7 7
3 6 6 8 8
1 5 5 7 7
1 6 6 8 8
2 5 5 7 7
3 6 6 8 8
2 3
Shading in the I column means the operand cannot be in memory.
Shading indicates addressing modes that cannot be used with this instruction.
343
#xx:16 3 4
@Rn+
@-Rn
#xx:8
@Rn
* Examples of Calculation of Number of States Required for Execution Example 1: Instruction fetch from memory area accessed via 16-bit bus in 2 states
Operand Read/Write 16-Bit bus, 2-state access memory area or general register Start Assembler Notation Addr. Address Code Mnemonic Even H'0100 H'D821 ADD @R0, R1 Odd H'0101 H'D821 ADD @R0, R1 Table A-7 + Table A-8 5+1 5+0 Number of States 6 5
Example 2: Instruction fetch from memory area accessed via 16-bit bus in 2 states when stack is in area accessed via 8-bit bus in 3 states
Operand Read/Write On-chip supporting module or 8-bit bus, 3-state-access memory area (word) Start Addr. Even Odd Assembler Notation Address Code Mnemonic H'FC00 H'11D8 JSR @R0 H'FC01 H'11D8 JSR @R0 Table A-7 + Table A-8 + 2I 9+0+2x2 9+1+2x2 Number of States 13 14
Example 3: Instruction fetch from memory area accessed via 8-bit bus in 3 states
Operand Read/Write 16-Bit bus, 2-state-access memory area or general register Assembler Notation Address Code Mnemonic H'9002 H'D821 ADD @R0, R1 Table A-7 + 2(J + K) 5 + 2 x (1 + 1) Number of States 9
Example 4: Instruction fetch from memory area accessed via 16-bit bus in 3 states
Table A-7 + Table A-8 + (J + K)/2 5 + 1 + (1 + 1)/2 5 + 0 + (1 + 1)/2
Operand Read/Write 16-Bit bus, 2-state access memory area or general register
Start Addr. Even Odd
Assembler Notation Address Code Mnemonic H'0100 H'D821 ADD @R0, R1 H'0101 H'D821 ADD @R0, R1
Number of States 7 6
344
Table A-7 Instruction Execution Cycles (1)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction ADD:G.B , Rd ADD:G.W , Rd ADD:Q.B #xx, ADD:Q.W #xx, ADDS.B , Rd ADDS.W , Rd ADDX.B , Rd ADDX.W , Rd AND.B , Rd AND.W , Rd ANDC #xx, CR BCLR.B #xx, BCLR.W #xx, BNOT.B #xx, BNOT.W #xx, BSET.B #xx, BSET.W #xx, BTST.B #xx, BTST.W #xx, CLR.B CLR.W CMP:G.B , Rd CMP:G.W , Rd CMP:G.B #XX:8, CMP:G.B #XX:16, * Rs can also be coded as the source operand. * * * * * * * *
I 1 2 2 4 1 2 1 2 1 2
J 1 1 1 1 1 1 1 1 1 1 1
K
1 2 2 2 2 3 3 2 2 2 2
1 5 5 7 7 5 5 5 5 5 5
2 5 5 7 7 5 5 5 5 5 5
3 6 6 8 8 6 6 6 6 6 6
1 5 5 7 7 5 5 5 5 5 5
1 6 6 8 8 6 6 6 6 6 6
2 5 5 7 7 5 5 5 5 5 5
3 6 6 8 8 6 6 6 6 6 6
2 3
3 4 3 4 3 4 5 9
2 4 2 4 2 4 1 2 1 2 1 2 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 3
4 4 4 4 4 4 3 3 2 2 2 2
7 7 7 7 7 7 5 5 5 5 5 5 6 7
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8
7 7 7 7 7 7 5 5 5 5 5 5 6 7
8 8 8 8 8 8 6 6 6 6 6 6 7 8 3 4
345
#xx:16 3 4
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (2)
Addressing mode @(d:16,Rn) @(d:16, Rn) @(d:8,Rn) @(d:8, Rn)
@aa:16 @aa:16
Instruction Instruction CMP:E #xx:8, CMP:E #xx:8,RdRd CMP:I #xx:16, CMP:I #xx:16,RdRd DADD DADD Rs, Rd DIVXU.B DIVXU.B , Rd DIVXU.W DIVXU.W , Rd DSUB DSUB Rs, Rd EXTS EXTS Rd EXTU EXTU Rd LDC.B LDC.B , CR LDC.W LDC.W , CR MOV:G.B MOV.B MOV:G.W MOV.W MOV.G.B #xx:8, MOV.B #xx:8, MOV.G.W #xx:16, MOV.W #xx:16, MOV:E #xx:8, MOV:E #xx:8,RdRd MOV:I #xx:16, Rd MOV:I #xx:16,Rd MOV:L.B @aa:8, MOV:L.B @aa:8,RdRd MOV:L.W @aa:8, MOV:L.W @aa:8,RdRd MOV:S.B Rs ,@aa:8 MOV:S.B Rs,@aa:8 MOV:S.W Rs ,@aa:8 MOV:S.W Rs,@aa:8 MOV:F.B @(d:8, R6), Rd MOV:F.B @(d:8, R6), Rd MOV:F.W @(d:8, R6), Rd MOV:F.W @(d:8, R6), Rd MOV:F.B Rs, @(d:8, R6) MOV:F.B Rs , @(d:8, R6) MOV:F.W Rs, @(d:8, R6) MOV:F.W Rs , @(d:8, R6)
II
J J 0 0 2 2
K
1 1
1 1
2 2
3 3
1 1
1 1
22
3 3
#xx:8 #xx:8 2 2 2 2 4 4 3 3 2 2
@Rn @Rn
4 4 20 20 26 26 4 4 3 3 3 3 3 3 4 4 2 2 2 2 6 6 7 7 5 5 5 5 7 7 8 8 6 6 7 7 5 5 5 5 7 7 8 8 7 8 8 6 6 6 8 9 6 6 7 7 5 5 5 5 7 7 8 8 7 7 8 8 6 6 6 6 8 8 9 9 6 6 7 7 5 5 5 5 7 7 8 8 7 7 8 8 6 6 6 6 8 8 9 9 23 23 24 23 24 23 23 24 23 24 29 29 30 29 30 29 29 30 29 30 23 23 29 29 24 21 24 21 30 30 28 28
1 1 2 2
1 1 1 1 2 2 1 1
1 1 2 2 1 1 2 2 1 1 2 2
1 1 1 1 1 1 2 3 0 0 0
1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2
0 0 0 0 0 0 0 0 0 0 5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
346
#xx:16 #xx:16 3 3 3 3 6 6 4 4 3 3
@aa:8 @aa:8
@Rn+ @Rn+
@-Rn @-Rn
Rn Rn
Table A-7 Instruction Execution Cycles (3)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction MOVFPE * , RD
I 0
J 2
K
1
1 13 | 20 13 | 20
2 13 | 20 13 | 20 19 25 7 7 7 7 5 5
3 14 | 21 14 | 21 20 26 8 8 8 8 6 6
1 13 | 20
1 14 | 21
2 13 | 20 13 | 20 19 25 7 7 7 7 5 5
3 14 | 21 14 | 21 20 26 8 8 8 8 6 6
2
MOVTPE * , RD
0
2
13 14 | | 20 21 19 20 25 26 7 7 7 7 5 5 8 8 8 8 6 6
MULXU.B , RD MULXU.W , RD NEG.B NEG.W NOT.B NOT.W OR.B , Rd OR.W , Rd ORC #xx, CR ROTL.B ROTL.W ROTR.B ROTR.W ROTXL.B ROTXL.W ROTXR.B ROTXR.W SHAL.B SHAL.W SHAR.B SHAR.W SHLL.B SHLL.W
1 2 2 4 2 4 1 2
1 1 1 1 1 1 1 1 1
16 23 2 2 2 2 2 2
19 25 7 7 7 7 5 5
18 25
3 4 5 9
2 4 2 4 2 4 2 4 2 4 2 4 2 4
1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2
7 7 7 7 7 7 7 7 7 7 7 7 7 7
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
7 7 7 7 7 7 7 7 7 7 7 7 7 7
8 8 8 8 8 8 8 8 8 8 8 8 8 8
* MOVFPE and MOVTPE are executed synchronous with the E-clock, so the number of execution states will change depending on the timing of execution.
347
#xx:16 3
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (4)
Addressing mode @(d:16, Rn) @(d:8, Rn)
@aa:16
@aa:8
Instruction SHLR.B SHLR.W STC.B CR, STC.W CR, SUB.B , Rd SUB.W , Rd SUBS.B , Rd SUBS.W , Rd SUBX.B , Rd SUBX.W , Rd SWAP Rd TAS TST.B TST.W XCH Rs, Rd XOR.B , Rd XOR.W , Rd XORC #xx, CR * DIVXU.B DIVXU.B DIVXU.W DIVXU.W DIVXU.B DIVXU.W * Zero divide, minimum mode Zero divide, maximum mode Zero divide, minimum mode Zero divide, maximum mode Overflow Overflow
I 2 4 1 2 1 2 1 2 1 2
J 1 1 1 1 1 1 1 1 1 1 1
K
1 2 2 4 4 2 2 3 3 2 2 3 4 2 2 4 2 2
1 7 7 7 7 5 5 5 5 5 5
2 7 7 7 7 5 5 5 5 5 5
3 8 8 8 8 6 6 6 6 6 6
1 7 7 7 7 5 5 5 5 5 5
1 8 8 8 8 6 6 6 6 6 6
2 7 7 7 7 5 5 5 5 5 5
3 8 8 8 8 6 6 6 6 6 6
2
3 4 3 4 3 4
2 1 2
1 1 1 1
7 5 5
7 5 5
8 6 6
7 5 5
8 6 6
7 5 5
8 6 6
1 2
1 1 1
5 5
6 6
5 5
5 5
6 6
5 5
6 6
3 4 5 9
7 10 11 6 8 10 12 1 2
6
1 1 1 1 1 1
20 25 20 25 8 8
23 28 23 28 11 11
23 28 23 28 11 11
24 29 24 29 12 12
23 24 28 29 23 24 28 29 11 12 11 12
23 28 23 28 11 11
24 29 24 29 12 12
21 21 27 27 9 10
For register and immediate operands For memory operand
348
#xx:16 3
@Rn+
@-Rn
#xx:8
@Rn
Rn
Table A-7 Instruction Execution Cycles (5)
Instruction Bcc d:8 Bcc d:16 BSR JMP (Condition) Condition false, branch not taken Condition true, branch taken Condition false, branch not taken Condition true, branch taken d:8 d:16 @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) JSR @aa:16 @Rn @(d:8, Rn) @(d:16, Rn) LDM LINK NOP RTD RTE RTS SCB Condition false, branch not taken Count = -1, branch not taken Other than the above, branch taken SLEEP STM * n is the number of registers specified in the register list. Cycles preceding transition to powerdown mode 6 + 3n* 2n 2 #xx:8 #xx:16 Minimum mode Maximum mode #xx:8 #xx:16 Execution Cycles 3 7 3 7 9 9 7 6 7 8 9 9 9 10 6 + 4n* 6 7 2 9 9 13 15 8 3 4 8 2 2 2 4 6 2 2 2 2 2 2n 2 2 2 2 I J+K 2 5 3 6 4 5 5 5 5 6 5 5 5 6 2 2 3 1 4 5 4 4 4 3 3 6 0
349
Table A-7 Instruction Execution Cycles (6)
Instruction TRAPA TRAP/VS
(Condition) Minimum mode Maximum mode V = 0, trap not taken V = 1, trap taken, minimum mode V = 1, trap taken, maximum mode
Execution Cycles 17 22 3 18 23 5 9 8 15 13 12 13 13
I 6 10 6 10 2
J+K 4 4 1 4 4 1 6 5
UNLK PJMP PJSR PRTS PRTD #xx:8 #xx:16 @aa:24 @Rn @aa:24 @Rn
4 4 4 4 4
6 5 5 5 6
Table A-8 (a) Adjustment Value (Branch Instruction)
Instruction BSR, JMP, JSR, RTS, RTD, RTE TRAPA, PJMP, PJSR, PRTS, PRTD Bcc, SCB, TRAP/VS (branch taken) Address even odd even odd Adjustment Value 0 1 0 1
Table A-8 (b) Adjustment Value (Other Instructions by Addressing Modes)
@(d:16, Rn)
@(d:8, Rn)
@aa:16
@aa:8
Instructor MOV.B #xx:8, MOVTPE, MOVFPE MOV.W #xx:16,
Start Address even odd even odd
1 1 2 0 0 0 1 0
1 1 0 2 0 1
1 1 2 0 1 0
1 1 2 0 1 0
1 1 2 0 1 0
1 1 0 2 0 1
1 1 2 0 1 0 0 0 0 0
Instruction other than above
even odd
350
#xx:16
@Rn+
@-Rn
#xx:8
@Rn
Rn
Appendix B Register Field
B.1 Register Addresses and Bit Names
Register Name P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR -- P8DDR P7DR P8DR ADDRA H ADDRA L ADDRB H ADDRB L ADDRC H ADDRC L ADDRD H ADDRD L ADCSR ADCR -- -- -- -- -- -- Bit Names Bit 4 Bit 3 P14DDR P13DDR P24DDR P23DDR P14 P13 P24 P23 P34DDR P33DDR P44DDR P43DDR P34 P33 P44 P43 P54DDR P53DDR P64DDR P63DDR P54 P53 P64 P63 -- -- P84DDR P83DDR -- P73 P84 P83 AD6 AD5 -- -- AD6 AD5 -- -- AD6 AD5 -- -- AD6 AD5 -- -- SCAN CKS -- -- -- -- -- -- -- -- -- -- -- -- -- --
Addr. H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F H'FE90 H'FE91 H'FE92 H'FE93 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FE9C H'FE9D H'FE9E H'FE9F
Bit 7 P17DDR P27DDR P17 P27 P37DDR P47DDR P37 P47 P57DDR P67DDR P57 P67 -- P87DDR -- P87 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE -- -- -- -- -- --
Bit 6 P16DDR P26DDR P16 P26 P36DDR P46DDR P36 P46 P56DDR P66DDR P56 P66 -- P86DDR -- P86 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- -- -- -- -- --
Bit 5 P15DDR P25DDR P15 P25 P35DDR P45DDR P35 P45 P55DDR P65DDR P55 P65 -- P85DDR -- P85 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- -- -- -- -- --
Bit 2 P12DDR P22DDR P12 P22 P32DDR P42DDR P32 P42 P52DDR P62DDR P52 P62 -- P82DDR P72 P82 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- -- -- -- -- --
Bit 1 P11DDR P21DDR P11 P21 P31DDR P41DDR P31 P41 P51DDR P61DDR P51 P61 -- P81DDR P71 P81 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- -- -- -- -- --
Bit 0 P10DDR P20DDR P10 P20 P30DDR P40DDR P30 P40 P50DDR P60DDR P50 P60 -- P80DDR P70 P80 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- -- -- -- -- --
Module Port 1 Port 2 Port 1 Port 2 Port 3 Port 4 Port 3 Port 4 Port 5 Port 6 Port 5 Port 6 -- Port 8 Port 7 Port 8
A/D
Note: A/D: A/D converter
(Continued on next page)
351
(Continued from preceding page) Register Name TCR TCSR FRC H FRC L OCRA H OCRA L OCRB H OCRB L ICR H ICR L -- -- -- -- -- -- TCR TCSR FRC H FRC L OCRA H OCRA L OCRB H OCRB L ICR H ICR L -- -- -- -- -- -- Bit Names Bit 3 OEB OLVLB
Addr. H'FEA0 H'FEA1 H'FEA2 H'FEA3 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEAC H'FEAD H'FEAE H'FEAF H'FEB0 H'FEB1 H'FEB2 H'FEB3 H'FEB4 H'FEB5 H'FEB6 H'FEB7 H'FEB8 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF
Bit 7 ICIE ICF
Bit 6 OCIEB OCFB
Bit 5 OCIEA OCFA
Bit 4 OVIE OVF
Bit 2 OEA OLVLA
Bit 1 CKS1 IEDG
Bit 0 CKS0 CCLRA
Module
FRT1 -- -- -- -- -- -- ICIE ICF -- -- -- -- -- -- OCIEB OCFB -- -- -- -- -- -- OCIEA OCFA -- -- -- -- -- -- OVIE OVF -- -- -- -- -- -- OEB OLVLB -- -- -- -- -- -- OEA OLVLA -- -- -- -- -- -- CKS1 IEDG -- -- -- -- -- -- CKS0 CCLRA
FRT 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Continued on next page)
Notes: FRT1: Free-running timer channel 1 FRT2: Free-running timer channel 2
352
(Continued from preceding page) Register Name TCR TCSR TCORA TCORB TCNT -- -- -- SMR BRR SCR TDR SSR RDR -- -- SMR BRR SCR TDR SSR RDR -- -- RFSHCR Bit Names Bit 4 Bit 3 CCLR1 CCLR0 -- OS3
Addr. H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FECF H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 H'FEDA H'FEDB H'FEDC H'FEDD H'FEDE H'FEDF
Bit 7 CMIEB CMFB
Bit 6 CMIEA CMFA
Bit 5 OVIE OVF
Bit 2 CKS2 OS2
Bit 1 CKS1 OS1
Bit 0 CKS0 OS0
Module
TMR -- -- -- C/A TIE TDRE -- -- C/A TIE TDRE -- -- RFSHE -- -- -- CHR RIE RDRF -- -- CHR RIE RDRF -- -- ASWC -- -- -- PE TE ORER -- -- PE TE ORER -- -- ARFSH -- -- -- O/E RE FER -- -- O/E RE FER -- -- RWC1 -- -- -- STOP -- PER -- -- STOP -- PER -- -- RWC0 -- -- -- -- -- -- -- -- -- -- -- -- -- CYC2 -- -- -- CKS1 CKE1 -- -- -- CKS1 CKE1 -- -- -- CYC1 -- -- -- CKS0 CKE0 SCI1 -- -- -- CKS0 CKE0 SCI2 -- -- -- CYC0
RFSHC
Notes: TMR: 8-Bit timer SCI1: Serial communication interface channel 1 SCI2: Serial communication interface channel 2 RFSHC: Refresh controller
(Continued on next page)
353
(Continued from preceding page) Register Name IPRA IPRB IPRC IPRD -- -- -- -- DTEA DTEB DTEC DTED -- -- -- -- TCSR* TCNT* Bit Names Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Addr. H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF07 H'FF08 H'FF09 H'FF0A H'FF0B H'FF0C H'FF0D H'FF0E H'FF0F H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A H'FF1B H'FF1C H'FF1D
Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OVF
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Module
-- -- -- -- -- -- -- -- -- -- WT/IT
-- -- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
INTC
-- -- -- -- -- -- CKS2 -- -- -- -- -- CKS1 -- -- -- -- CKS0 WDT
-- -- -- -- TME
-- -- -- -- -- --
WCR ARBT AR3T MDCR SBYCR BRCR NMICR IRQCR
--
--
--
--
WMS1
WMS0
WC1
WC0
WSC BSC
-- SSBY -- -- --
-- -- -- -- -- RSTOE
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- IRQ3E --
MDS2 -- -- -- IRQ2E --
MDS1 -- -- -- IRQ1E --
MDS0 -- BRLE NMIEG IRQ0E -- WDT
H'FF1E RSTCSR* H'FF1F RSTCSR* WRST
Notes: INTC: Interrupt controller (Continued on next page) WDT: Watchdog timer WSC: Wait state controller BSC: Bus controller * Read addresses of TCSR and TCNT are shown. Write addresses of both TCSR and TCNT are H'FF10. RSTCSR is written at H'FF1E and read at H'FF1F. These three registers are password-protected. See section 16.2.4, "Notes on Register Access" for details.
354
B.2 Register Descriptions
Register name Acronym of the register
ADCSR--A/D Control/Status Register
Address to which the register is mapped
H'FE98
Name of the on-chip supporting module
A/D
Bit numbers Initial bit values
Bit
7 ADF
6 ADIE 0 R/W
5 ADST 0 R/W
4 SCAN 0 R/W
3 CKS 0 R/W
2 CH2 0 R/W
1 CH1 0 R/W
0 CH0 0 R/W
Initial value Read/Write
0 R/(W)*
Names of the bits. Dashes (--) indicate reserved bits.
Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3
Type of access permitted R Read only W Write only R/W Both read and write
CH2 0 0 0 0
Channel Select CH1 CH0 Single Mode 0 0 AN0 0 1 AN1 1 0 AN2 1 1 AN3
Full name of the bit
Clock Select 0 Conversion time = 247 states (max) 1 Conversion time = 138 states (min)
Functions of the bit settings
Scan Mode 0 Single mode 1 Scan mode
355
P1DDR--Port 1 Data Direction Register
Bit 7 6 5 4
H'FE80
3 2 1
Port 1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 1 Input/Output Selection 0 Input port 1 Output port
P2DDR--Port 2 Data Direction Register
Bit 7 6 5 4
H'FE81
3 2 1
Port 2
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 2 Input/Output Selection 0 Input port 1 Output port
P1DR--Port 1 Data Register
Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W
H'FE82
3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W
Port 1
0 P10 0 R/W
356
P2DR--Port 2 Data Register
Bit 7 P27 Initial value Read/Write 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W
H'FE83
3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W
Port 2
0 P20 0 R/W
P3DDR--Port 3 Data Direction Register
Bit 7 6 5 4
H'FE84
3 2 1
Port 3
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 3 Input/Output Selection 0 Input port 1 Output port
P4DDR--Port 4 Data Direction Register
Bit 7 6 5 4
H'FE85
3 2 1
Port 4
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 4 Input/Output Selection 0 Input port 1 Output port
357
P3DR--Port 3 Data Register
Bit 7 P37 Initial value Read/Write 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W
H'FE86
3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W
Port 3
0 P30 0 R/W
P4DR--Port 4 Data Register
Bit 7 P47 Initial value Read/Write 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W
H'FE87
3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W
Port 4
0 P40 0 R/W
P5DDR--Port 5 Data Direction Register
Bit 7 6 5 4
H'FE88
3 2 1
Port 5
0
P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 5 Input/Output Selection 0 Input port 1 Output port
358
P6DDR--Port 6 Data Direction Register
Bit 7 6 5 4
H'FE89
3 2 1
Port 6
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 6 Input/Output Selection 0 Input port 1 Output port
P5DR--Port 5 Data Register
Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W
H'FE8A
3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W
Port 5
0 P50 0 R/W
P6DR--Port 6 Data Register
Bit 7 P67 Initial value Read/Write 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W
H'FE8B
3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W
Port 6
0 P60 0 R/W
P8DDR--Port 8 Data Direction Register
Bit 7 6 5 4
H'FE8D
3 2 1
Port 8
0
P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Port 8 Input/Output Selection 0 Input port 1 Output port
359
P7DR--Port 7 Data Register
Bit 7 -- 6 -- 5 -- 4 --
H'FE8E
3 P73 2 P72 1 P71
Port 7
0 P70
Read/Write
--
--
--
--
R
R
R
R
P8DR--Port 8 Data Register
Bit 7 P87 Initial value Read/Write 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W
H'FE8F
3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W
Port 8
0 P80 0 R/W
ADDRn (H)--A/D Data Register n (High) (n = A, B, C, D) H'FE90, H'FE92, H'FE94, H'FE96
Bit 7 AD9 Initial value Read/Write 0 R 6 AD8 0 R 5 AD7 0 R 4 AD6 0 R 3 AD5 0 R 2 AD4 0 R 1 AD3 0 R
A/D
0 AD2 0 R
Upper 8 bits of 10-bit A/D conversion result
ADDRn (L)--A/D Data Register n (Low) (n = A, B, C, D) H'FE91, H'FE93, H'FE95, H'FE97
Bit 7 AD1 Initial value Read/Write 0 R 6 AD0 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R
A/D
0 -- 0 R
Lower 2 bits of 10-bit A/D conversion result
360
ADCSR--A/D Control/Status Register
Bit 7 ADF Initial value Read/Write 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W
H'FE98
3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W
A/D
0 CH0 0 R/W
CH2 CH1 CH0 0 0 0 0 0 1 0 1 0 0 1 1
Channel Select Single Mode Scan Mode AN0 AN0 AN1 AN0, AN1 AN2 AN0 to AN2 AN3 AN0 to AN3
Clock Select 0 Conversion time = 266 states (max) 1 Conversion time = 134 states (max) Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is halted. 1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to 0. 2. Scan mode: A/D conversion starts and continues cyclically on all selected channels until 0 is written in this bit. A/D Interrupt Enable 0 A/D-end interrupt is disabled. 1 A/D-end interrupt is enabled. A/D End Flag 0 Cleared from 1 to 0 when: 1. The chip is reset or enters a standby mode. 2. CPU reads ADF = 1, then writes 0 in ADF. 3. ADI interrupt is served by DTC. 1 Set to 1 at the following times: 1. Single mode: at the completion of A/D conversion. 2. Scan mode: when all selected channels have been converted. * Only writing of 0 to clear the flag is enabled.
361
ADCR--A/D Control Register
Bit 7 TRGE Initial value Read/Write 0 R/W 1 -- 1 -- 1 -- 6 5 4
H'FE99
3 2 1
A/D
0
1 --
1 --
1 --
1 --
Trigger Enable 0 The A/D external trigger is disabled. 1 The A/D external trigger is enabled and P40 is set for input. A/D conversion starts on the falling edge of the ADTRG signal input at P40.
362
TCR--Timer Control Register
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FEA0
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT1
0 CKS0 0 R/W
00 01 10 11
Clock Select Internal clock source: o4 Internal clock source: o8 Internal clock source: o32 External clock source: counted on rising edge
Output Enable A 0 Compare-A output is disabled. 1 Compare-A output is enabled. Output Enable B 0 Compare-B output is disabled. 1 Compare-B output is enabled. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Output Compare Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. Input Capture Interrupt Enable 0 Input capture interrupt is disabled. 1 Input capture interrupt is enabled.
363
TCSR--Timer Control/Status Register
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)*
H'FEA1
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT1
0 CCLRA 0 R/W
Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by comparematch A. Input Edge Select 0 Count is captured on falling edge of input capture signal (FTI). 1 Count is captured on rising edge of input capture signal. 0 1 Output Level A Compare-match A causes 0 output. Compare-match A causes 1 output.
0 1 0 1 0 1 0
Output Level B Compare-match B causes 0 output. Compare-match B causes 1 output.
Timer Overflow Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. Set to 1 when FRC changes from H'FFFF to H'0000.
Output Compare Flag A Cleared from 1 to 0 when: 1. CPU reads OCFA = 1, then writes 0 in OCFA. 2. OCIA interrupt is served by DTC. Set to 1 when FRC = OCRA.
Output Compare Flag B Cleared from 1 to 0 when: 1. CPU reads OCFB = 1, then writes 0 in OCFB. 2. OCIB interrupt is served by DTC. 1 Set to 1 when FRC = OCRB. Input Capture Flag 0 Cleared from 1 to 0 when: 1. CPU reads ICF = 1, then writes 0 in ICF. * Only writing of a 0 to 2. ICI interrupt is served by DTC. clear the flag is enabled. 1 Set to 1 when input capture signal is received and FRC count is copied to ICR.
364
FRC (H and L)--Free-Running Counter
Bit 7 6 5 4
H'FEA2, H'FEA3
3 2 1
FRT 1
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value OCRA (H and L)--Output Compare Register A
Bit 7 6 5 4
H'FEA4, H'FEA5
3 2 1
FRT 1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Continually compared with FRC. OCFA is set to 1 when OCRA = FRC. OCRB (H and L)--Output Compare Register B
Bit 7 6 5 4
H'FEA6, H'FEA7
3 2 1
FRT 1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Continually compared with FRC. OCFB is set to 1 when OCRB = FRC. ICR (H and L)--Input Capture Register
Bit 7 6 5 4
H'FEA8, H'FEA9
3 2 1
FRT 1
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Contains FRC count captured when external input capture signal changes.
365
TCR--Timer Control Register
Bit 7 ICIE Initial value Read/Write 0 R/W 6 OCIEB 0 R/W 5 OCIEA 0 R/W 4 OVIE 0 R/W
H'FEB0
3 OEB 0 R/W 2 OEA 0 R/W 1 CKS1 0 R/W
FRT 2
0 CKS0 0 R/W
Note: Bit functions are the same as for FRT1.
TCSR--Timer Control/Status Register
Bit 7 ICF Initial value Read/Write 0 R/(W)* 6 OCFB 0 R/(W)* 5 OCFA 0 R/(W)* 4 OVF 0 R/(W)*
H'FEB1
3 OLVLB 0 R/W 2 OLVLA 0 R/W 1 IEDG 0 R/W
FRT 2
0 CCLRA 0 R/W
Note: Bit functions are the same as for FRT1. * Only writing of a 0 to clear the flag is enabled.
FRC (H and L)--Free-Running Counter
Bit 7 6 5 4
H'FEB2, H'FEB3
3 2 1
FRT 2
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Note: Bit functions are the same as for FRT1.
366
OCRA (H and L)--Output Compare Register A
Bit 7 6 5 4
H'FEB4, H'FEB5
3 2 1
FRT 2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
OCRB (H and L)--Output Compare Register B
Bit 7 6 5 4
H'FEB6, H'FEB7
3 2 1
FRT 2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for FRT1.
ICR (H and L)--Input Capture Register
Bit 7 6 5 4
H'FEB8, H'FEB9
3 2 1
FRT 2
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for FRT1.
367
TCR--Timer Control Register
Bit 7 CMIEB Initial value Read/Write 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W
H'FEC0
3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W
TMR
0 CKS0 0 R/W
Clock Select 0 0 0 No clock source; timer stops. 0 0 1 Internal clock source: o/8, counted on falling edge. 0 1 0 Internal clock source: o/64, counted on falling edge. 0 1 1 Internal clock source: o/1024, counted on falling edge. 1 0 0 No clock source; timer stops. 1 0 1 External clock source, counted on rising edge. 1 1 0 External clock source, counted on falling edge. 1 1 1 External clock source, counted on both rising and falling edges. Counter Clear Counter is not cleared. Cleared by compare-match A. Cleared by compare-match B. Cleared on rising edge of external reset input.
0 0 1 1
0 1 0 1
Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled.
368
TCSR--Timer Control/Status Register
Bit 7 CMFB Initial value Read/Write 0 6 CMFA 5 OVF 4 -- 1 --
H'FEC1
3 OS3*2 0 R/W 2 OS2*2 0 R/W 1 OS1*2 0 R/W
TMR
0 OS0*2 0 R/W
0 0 *1 R/(W)*1 R/(W)*1 R/(W)
0 0 1 1
0 1 0 1
Output Select No change on compare-match A. Output 0 on compare-match A. Output 1 on compare-match A. Invert (toggle) output on compare-match A.
Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. Timer Overflow Flag 0 Cleared from 1 to 0 when CPU reads OVF = 1, then writes 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared from 1 to 0 when: 1. CPU reads CMFA = 1, then writes 0 in CMFA. 2. CMIA interrupt is served by the DTC. 1 Set to 1 when TCNT = TCORA. Compare-Match Flag B 0 Cleared from 1 to 0 when: 1. CPU reads CMFB = 1, then writes 0 in CMFB. 2. CMIB interrupt is served by the DTC. 1 Set to 1 when TCNT = TCORB.
Notes: *1 Only writing of 0 to clear the flag is enabled. *2 When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
369
TCORA--Time Constant Register A
Bit 7 6 5 4
H'FEC2
3 2 1
TMR
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The CMFA bit is set to 1 when TCORA = TCNT. TCORB--Time Constant Register B
Bit 7 6 5 4
H'FEC3
3 2 1
TMR
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
The CMFB bit is set to 1 when TCORB = TCNT. TCNT--Timer Counter
Bit 7 6 5 4
H'FEC4
3 2 1
TMR
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value
370
SMR--Serial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FEC8
3 STOP 0 R/W 2 -- 1 -- 1 CKS1 0 R/W
SCI1
0 CKS0 0 R/W
0 0 1 1
0 1 0 1
Clock Select o clock o/4 clock o/16 clock o/64 clock
Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous
371
BRR--Bit Rate Register
Bit 7 6 5 4
H'FEC9
3 2 1
SCI1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Constant that determines the baud rate SCR--Serial Communication Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FECA
3 -- 1 -- 2 -- 1 -- 1 CKE1 0 R/W
SCI1
0 CKE0 0 R/W
Clock Enable 0 0 SCK pin is not used. 1 SCK pin is used for output. Clock Enable 1 0 Internal clock 1 External clock, input at SCK pin Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt request (RXI) is disabled. 1 Receive interrupt request (RXI) is enabled. Transmit Interrupt Enable 0 Transmit interrupt request (TXI) is disabled. 1 Transmit interrupt request (TXI) is enabled.
372
TDR--Transmit Data Register
Bit 7 6 5 4
H'FECB
3 2 1
SCI1
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Transmit data
373
SSR--Serial Status Register
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)*
H'FECC
3 PER 0 R/(W)* 2 -- 1 -- 1 -- 1 --
SCI1
0 -- 1 --
Parity Error 0 Cleared from 1 to 0 when: 1. CPU reads PER = 1, then writes 0 in PER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a parity error occurs (parity of receive data does not match parity selected by O/E bit). Framing Error 0 Cleared from 1 to 0 when: 1. CPU reads FER = 1, then writes 0 in FER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared from 1 to 0 when: 1. CPU reads ORER = 1, then writes 0 in ORER. 2. The chip is reset or enters a standby mode. 1 Set to 1 when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared from 1 to 0 when: 1. CPU reads RDRF = 1, then writes 0 in RDRF. 2. RDR is read by the DTC. 3. The chip is reset or enters a standby mode. 1 Set to 1 when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared from 1 to 0 when: 1. CPU reads TDRE = 1, then writes 0 in TDRE. 2. The DTC writes data in TDR. 1 Set to 1 when: 1. The chip is reset or enters a standby mode. 2. Data is transferred from TDR to TSR. 3. TE is cleared to 0 when TDRE = 0. * Only writing of 0 to clear the flag is enabled.
374
RDR--Receive Data Register
Bit 7 6 5 4
H'FECD
3 2 1
SCI1
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Receive data SMR--Serial Mode Register
Bit 7 C/A Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W
H'FED0
3 STOP 0 R/W 2 -- 1 -- 1 CKS1 0 R/W
SCI2
0 CKS0 0 R/W
Note: Bit functions are the same as for SCI1.
BRR--Bit Rate Register
Bit 7 6 5 4
H'FED1
3 2 1
SCI2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI1.
SCR--Serial Control Register
Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W
H'FED2
3 -- 1 -- 2 -- 1 -- 1 CKE1 0 R/W
SCI2
0 CKE0 0 R/W
Note: Bit functions are the same as for SCI1.
375
TDR--Transmit Data Register
Bit 7 6 5 4
H'FED3
3 2 1
SCI2
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Note: Bit functions are the same as for SCI1.
SSR--Serial Status Register
Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)*
H'FED4
3 PER 0 R/(W)* 2 -- 1 -- 1 -- 1 --
SCI2
0 -- 1 --
Note: Bit functions are the same as for SCI1. * Only writing of 0 to clear the flag is enabled.
RDR--Receive Data Register
Bit 7 6 5 4
H'FED5
3 2 1
SCI2
0
Initial value Read/Write
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Note: Bit functions are the same as for SCI1.
376
RFSHCR--Refresh Control Register
Bit 7 RFSHE Initial value Read/Write 1 R/W 6 ASWC 1 R/W 5 ARFSH 0 R/W 4 RWC1 1 R/W
H'FED8
3 RWC0 1 R/W 2 CYC2 0 R/W 1 CYC1 0 R/W
RFSHC
0 CYC0 0 R/W
Refresh Cycle 2 to 0
Refresh Request CYC2 CYC1 CYC0 Interval (States) 0 0 0 32 0 0 1 64 0 1 0 96 0 1 1 128 1 0 0 160 1 0 1 192 1 1 0 224 1 1 1 256 Time Interval (Examples) 10 MHz 8 MHz 6 MHz 3.2 s 4.0 s 5.3 s 6.4 s 8.0 s 10.6 s 9.6 s 12.0 s 16.0 s 12.8 s 16.0 s 21.3 s 16.0 s 20.0 s 26.6 s 19.2 s 24.0 s 32.0 s 22.4 s 28.0 s 37.3 s 25.6 s 32.0 s 42.6 s
Refresh Wait Cycle 1 and 0 RWC1 RWC0 Wait States Refresh States 0 0 0 2 0 1 1 3 1 0 2 4 1 1 3 5 Auto-Refresh 0 RD is always 1 during refresh cycles. 1 RD is output as an auto-refresh pulse for pseudo-static RAM AS Wait Control 0 No TP states are inserted. 1 TP states are inserted. Refresh Enable 0 Refresh cycles are not inserted. 1 Refresh cycles are inserted.
377
IPRA--Interrupt Priority Register A
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FF00
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
IRQ0 Interrupt priority level (0 to 7)
IRQ1 to IRQ3 Interrupt priority level (0 to 7)
IPRB--Interrupt Priority Register B
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FF01
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
FRT1 Interrupt priority level (0 to 7)
FRT2 Interrupt priority level (0 to 7)
378
IPRC--Interrupt Priority Register C
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FF02
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
8-bit timer Interrupt priority level (0 to 7)
SCI1 Interrupt priority level (0 to 7)
IPRD--Interrupt Priority Register D
Bit 7 -- Initial value Read/Write 0 R 0 R/W 0 R/W 0 R/W 6 5 4
H'FF03
3 -- 0 R 0 R/W 0 R/W 2 1
INTC
0
0 R/W
SCI2 Interrupt priority level (0 to 7)
A/D converter Interrupt priority level (0 to 7)
379
DTEA--Data Transfer Enable Register A
Bit 7 -- Initial value Read/Write 0 R/W 6 -- 0 R/W 5 -- 0 R/W 0 R/W 4
H'FF08
3 -- 0 R/W 0 R/W 0 R/W 2 1
INTC
0
0 R/W
IRQ1 0 Served by CPU 1 Served by DTC
IRQ2 0 Served by CPU 1 Served by DTC
IRQ3 0 Served by CPU 1 Served by DTC
IRQ0 0 Served by CPU 1 Served by DTC
380
DTEB--Data Transfer Enable Register B
Bit 7 -- Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4
H'FF09
3 -- 0 R/W 0 R/W 0 R/W 2 1
INTC
0
0 R/W
FRT 1
FRT 2
ICI 0 Served by CPU 1 Served by DTC
OCIA 0 Served by CPU 1 Served by DTC
OCIB 0 Served by CPU 1 Served by DTC
ICI 0 Served by CPU 1 Served by DTC
OCIA 0 Served by CPU 1 Served by DTC OCIB 0 Served by CPU 1 Served by DTC
381
DTEC--Data Transfer Enable Register C
Bit 7 -- Initial value Read/Write 0 R/W 6 -- 0 R/W 0 R/W 0 R/W 5 4
H'FF0A
3 -- 0 R/W 0 R/W 0 R/W 2 1
INTC
0 -- 0 R/W
8-bit timer
SCI1
RXI 0 Served by CPU 1 Served by DTC
TXI 0 Served by CPU 1 Served by DTC
CMIA 0 Served by CPU 1 Served by DTC
CMIB 0 Served by CPU 1 Served by DTC
382
DTED--Data Transfer Enable Register D
Bit 7 -- Initial value Read/Write 0 R/W 0 R/W 0 R/W 6 5 4 -- 0 R/W
H'FF0B
3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W
INTC
0
0 R/W
SCI2
A/D converter
ADI 0 Served by CPU 1 Served by DTC
RXI 0 Served by CPU 1 Served by DTC
TXI 0 Served by CPU 1 Served by DTC
383
TCSR--Timer Control/Status Register
Bit 7 OVF Initial value Read/Write 0 R/(W)*3 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 --
H'FF10*1, H'FF11*2
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W
WDT
0 CKS0 0 R/W
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Clock Select o/2 (51.2 s)*4 o/32 (819.2 s) o/64 (1.6 ms) o/128 (3.3 ms) o/256 (6.6 ms) o/512 (13.1 ms) o/2048 (52.4 ms) o/4096 (104.9 ms)
Timer Enable 0 Timer is disabled. * TCNT is initialized to H'00 and stopped. 1 Timer is enabled. * TCNT starts incrementing. * CPU interrupt request is enabled. Timer Mode Select 0 Interval timer mode (IRQ0 interrupt request) 1 Watchdog timer mode (Reset)
Overflow Flag 0 Cleared from 1 to 0 when CPU reads OVF = 1, then wtites 0 in OVF. 1 Set to 1 when TCNT changes from H'FF to H'00.
Notes: *1 *2 *3 *4 Read address Write address Only writing of 0 to clear the flag is enabled. Times in parentheses are the times for TCNT to increment from H'00 to H'FF and change to H'00 again when o = 10 MHz.
384
TCNT--Timer Counter
Bit 7 6 5 4
H'FF11
3 2 1
WDT
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Count value
WCR--Wait-State Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FF14
3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W
WSC
0 WC0 1 R/W
Wait Count 1 and 0 0 0 No wait states (TW) are inserted. 0 1 1 wait state is inserted. 1 0 2 wait states are inserted. 1 1 3 wait states are inserted.
Wait Mode Select 1 and 0 0 0 Programmable wait mode 0 1 No wait states are inserted, regardless of the wait count. 1 0 Pin wait mode 1 1 Pin auto-wait mode
385
ARBT--Byte Area Top Register
Bit 7 6 5 4
H'FF16
3 2 1
BSC
0
Initial value Read/Write
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
AR3T--3-State Area Top Register
Bit 7 6 5 4
H'FF17
3 2 1
BSC
0
Initial value Read/Write
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
MDCR--Mode Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FF19
3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R
Mode Select Value input at mode pins
* Initialized according to the inputs at pins MD2, MD1, and MD0.
386
SBYCR--Software Standby Control Register
Bit 7 SSBY Initial value Read/Write 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FF1A
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
Software Standby 0 SLEEP instruction causes transition to sleep mode. 1 SLEEP instruction causes transition to software standby mode. BRCR--Bus Release Control Register
Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 --
H'FF1B
3 -- 1 -- 2 -- 1 -- 1 -- 1 --
Port 3
0 BRLE 0 R/W
Bus Release Enable 0 P32 and P31 are input and output pins. 1 P32 is the BREQ input pin and P31 is the BACK output pin.
NMICR--NMI Control Register
Bit 7 -- Initial value Read/Write 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R
H'FF1C
3 -- 1 R 2 -- 1 R 1 -- 1 R
INTC
0 NMIEG 0 R/W
Nonmaskable Interrupt Edge 0 Interrupt requested on falling edge of NMI signal. 1 Interrupt requested on rising edge of NMI signal.
387
IRQCR--IRQ Control Register
Bit 7 -- Initial value Read/Write 1 R 6 -- 1 R 5 -- 1 R 4 -- 1 R
H'FF1D
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W
INTC
0 IRQ0E 0 R/W
Interrupt Request 3 Enable 0 P83 is an input/output pin. 1 P83 is used for IRQ3 signal input, regardless of P83DDR. (The pin level can also be read.)
Interrupt Request 2 Enable 0 P82 is an input/output pin. 1 P82 is used for IRQ2 signal input, regardless of P82DDR. (The pin level can also be read.)
Interrupt Request 1 Enable 0 P81 is an input/output pin. 1 P81 is used for IRQ1 signal input, regardless of P81DDR. (The pin level can also be read.)
Interrupt Request 0 Enable 0 P80 is an input/output pin. 1 P80 is used for IRQ0 signal input, regardless of P80DDR. (The pin level can also be read.)
388
RSTCSR--Reset Status/Control Register
Bit 7 WRST Initial value Read/Write 0 R/(W)*1 6 RSTOE 0 R/W 5 -- 1 -- 4 -- 1 --
H'FF1F
3 -- 1 -- 2 -- 1 -- 1 -- 1 --
WDT
0 -- 1 --
Reset Output Enable 0 The reset signal generated when the watchdog timer overflows is not output externally. 1 The reset signal generated when the watchdog timer overflows is output externally.
Watchdog Timer Reset 0 Cleared from 1 to 0 by software, or by a Low input at the RES pin. 1 Set to 1 when TCNT overflows in watchdog timer mode and a reset signal is generated.
Note: *1 Software can write a 0 in bit 7 to clear the flag but cannot write a 1.
389
Appendix C I/O Port Schematic Diagrams
C.1 Schematic Diagram of Port 1
Data write Mode 2 or 4 Reset R Q Mode 1 or 3 D P1 n DDR C WP1D Internal data bus (PDB0 to PDB7) Mode 2 or 4 P1n Mode 1 or 3 Q Internal data bus (PDB8 to PDB15) Reset R D P1 n DR C WP1
WP1D: WP1: RP1: n:
Write to P1DDR Write to Port 1 Read Port 1 0 to 7
Mode 2 or 4
RP1
Read external address
Figure C-1 Schematic Diagram of Port 1
Table C-1 Data Read from Port 1
Mode 2 or 4 1 or 3 Data Always 1 Logic level at pin DR value
DDR = 0 DDR = 1
390
C.2 Schematic Diagram of Port 2
Mode 3 or 4 Software standby Bus release S Q Reset R D Internal data bus (PDB8 to PDB15)
WP2D: WP2: RP2: n: Internal address bus (IAB16 to IAB23)
Write to P2DDR Write to Port 2 Read Port 2 0 to 7
P2 n DDR C Mode 1 or 2 WP2D Reset R P2n Q D P2 n DR C Mode 3 or 4 WP2
RP2
Figure C-2 Schematic Diagram of Port 2
Table C-2 Data Read from Port 2
Mode 3 or 4 1 or 2 Data DR value Logic level at pin DR value
DDR = 0 DDR = 1
391
C.3 Schematic Diagrams of Port 3
Reset R Q D Internal data bus (PDB8) P3 0 DDR C WP3D Reset P30 R Q D P3 0 DR C WP3
WP3D: Write to P3DDR WP3: Write to Port 3 RP3: Read Port 3
Wait state control register bit 3 WMS1 Q
RP3
WAIT to CPU
Figure C-3 (a) Schematic Diagram of Port 3, Pin P30
Table C-3 (a) Data Read from Port 3, Pin P30
Mode WMS1 = 1 WMS1 = 0 Data Logic level at pin Logic level at pin DR value
DDR = 0 DDR = 1
392
Reset R Q D Internal data bus (PDB9) P31 DDR C WP3D Reset R P31 Q D P31 DR C WP3
WP3D: Write to P3DDR WP3: Write to Port 3 RP3: Read Port 3
Port 3 control register bit 3 BRLE Q
BACK
RP3
Figure C-3 (b) Schematic Diagram of Port 3, Pin P31
Table C-3 (b) Data Read from Port 3, Pin P31
Mode BRLE = 1 BRLE = 0 Data DR value Logic level at pin DR value
DDR = 0 DDR = 1
393
Reset R Q D Internal data bus (PDB10) P32 DDR C WP3D Reset P32 R Q D P32 DR C WP3
WP3D: Write to P3DDR WP3: Write to Port 3 RP3: Read Port 3
Port 3 control register bit 3 BRLE Q
RP3
BREQ to CPU
Figure C-3 (c) Schematic Diagram of Port 3, Pins P32
Table C-3 (c) Data Read from Port 3, Pin P32
Mode BRLE = 1 BRLE = 0 Data Logic level at pin Logic level at pin DR value
DDR = 0 DDR = 1
394
Reset R Q D P3n DDR C WP3D Reset R P3n Q D P3n DR C WP3 WP3D: WP3: RP3: n: Write to P3DDR Write to Port 3 Read Port 3 3 to 7
RP3
Figure C-3 (d) Schematic Diagram of Port 3, Pins P33 to P37
Table C-3 (d) Data Read from Port 3, Pins P33 to P37
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
395
C.4 Schematic Diagrams of Port 4
Reset R Q D Internal data bus (PDB8) P40 DDR C WPD Reset P40 R Q D P40 DR C WP4
WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4
A/D control register bit 7 TRGE Q
RP4
TRG to A/D
Figure C-4 (a) Schematic Diagram of Port 4, Pin P40
Table C-4 (a) Data Read from Port 4, Pin P40
Mode TRGE = 1 TRGE = 0 Data Logic level at pin Logic level at pin DR value
DDR = 0 DDR = 1
396
Reset R1 Q D P41 DDR C WP4D Reset R P41 Q D P41 DR C WP4
WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4
Internal data bus (PDB9) 8-bit timer module
RP4
Clock input
Figure C-4 (b) Schematic Diagram of Port 4, Pin P41
Table C-4 (b) Data Read from Port 4, Pin P41
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
397
Reset R1 Q D Internal data bus (PDB10) P42 DDR C WP4D Reset R P42 Q D P42 DR C WP4
WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4
RP4 8-bit timer module Counter reset input
Figure C-4 (c) Schematic Diagram of Port 4, Pin P42
Table C-4 (c) Data Read from Port 4, Pin P42
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
398
Reset R P43 DDR C WP4D Reset R P43 Q D P43 DR C WP4 Internal data bus (PDB11) Q D
WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4
8-bit timer module Output enable 8-bit timer output
RP4
Figure C-4 (d) Schematic Diagram of Port 4, Pin P43
Table C-4 (d) Data Read from Port 4, Pin P43
Mode 8-bit timer output enabled 8-bit timer DDR = 0 output disabled DDR = 1 Data 8-bit timer output Logic level at pin DR value
399
Reset Q D Internal data bus (PDB12, PDB14) R1 P4 n DDR C WP4D Reset R P4n Q D P4 n DR C WP4
WP4D: WP4: RP4: n:
Write to P4DDR Write to Port 4 Read Port 4 4 or 6
Free-running timer module
RP4
Input-capture input
Figure C-4 (e) Schematic Diagram of Port 4, Pins P44 and P46
Table C-4 (e) Data Read from Port 4, Pins P44 and P46
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
400
Reset Q D Internal data bus (PDB13, PDB15) R P4 n DDR C WP4D Reset R P4n Q D P4 n DR C WP4
WP4D: WP4: RP4: n:
Write to P4DDR Write to Port 4 Read Port 4 5 or 7
Free-running timer module
RP4
Counter clock input
Figure C-4 (f) Schematic Diagram of Port 4, Pins P45 and P47
Table C-4 (f) Data Read from Port 4, Pins P45 and P47
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
401
C.5 Schematic Diagrams of Port 5
Reset Q D Internal data bus (PDB8 to PDB11) R P5 n DDR C WP5D Reset R P5n Q D P5 n DR C WP5
WP5D: WP5: RP5: n:
Write to P5DDR Write to Port 5 Read Port 5 0 to 3
Free-running timer module Output enable Output-compare output
RP5
Figure C-5 (a) Schematic Diagram of Port 5, Pins P50 to P53
Table C-5 (a) Data Read from Port 5, Pins P50 to P53
Mode Output enabled Output DDR = 0 disabled DDR = 1 Data Output-compare output Logic level at pin DR value
402
Reset R P5n DDR C WP5D Reset P5n R Q D P5n DR C WP5 Internal data bus (PDB12 to PDB15) Q D
WP5D: WP5: RP5: n:
Write to P5DDR Write to Port 5 Read Port 5 4 to 7
RP5
Figure C-5 (b) Schematic Diagram of Port 5, Pins P54 to P57
Table C-5 (b) Data Read from Port 5, Pins P54 to P57
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
403
C.6 Schematic Diagram of Port 6
Reset R Q D Internal data bus (PDB8 to PDB15) P6n DDR C WP6D Reset P6n R Q D P6n DR C WP6
WP6D: WP6: RP6: n:
Write to P6DDR Write to Port 6 Read Port 6 0 to 7
RP6
Figure C-6 Schematic Diagram of Port 6, Pins P60 to P67
Table C-6 Data Read from Port 6, Pins P60 and P67
Mode DDR = 0 DDR = 1 Data Logic level at pin DR value
404
C.7 Schematic Diagram of Port 7
Internal data bus (PDB8 to PDB11)
RP7: Read Port 7 n: 4 to 7
RP7 P7n
A/D converter module Input multiplexer
Figure C-7 Schematic Diagram of Port 7
405
C.8 Schematic Diagrams of Port 8
Reset Q D Internal data bus (PDB8, PDB9) R P8n DDR C WP8D Reset P8n R Q D P8n DR C WP8
WP8D: WP8: RP8: n:
Write to P8DDR Write to Port 8 Read Port 8 0 or 1
IRQ control register bit 0 or 1 IRQ 0 E or IRQ 1 E Q
RP8
IRQ0 , IRQ 1 to CPU
Figure C-8 (a) Schematic Diagram of Port 8, Pins P80 and P81
Table C-7 (a) Data Read from Port 8, Pins P80 and P81
Mode IRQ0E or IRQ1E = 1 IRQ0E or IRQ1E = 1 Data Logic level at pin Logic level at pin DR value
DDR = 0 DDR = 1
406
Reset R Q D P8n DDR C WP8D
WP8D: WP8: RP8: n: Internal data bus (PDB10, PDB11)
Write to P8DDR Write to Port 8 Read Port 8 2 or 3
Reset R P8n Q D P8n DR C WP8
SCI module
Clock input enable Clock output enable Clock output IRQ control register bit 2 or 3 IRQ 2 E or IRQ 3 E
RP8
Q
Clock input IRQ2 , IRQ 3 to CPU
Figure C-8 (b) Schematic Diagram of Port 8, Pins P82 and P83
Table C-7 (b) Data Read from Port 8, Pins P82 and P83
Mode Clock input enabled Clock output enabled Clock input and output disabled Data Clock input value Clock output value Logic level at pin Logic level at pin DR value
IRQ2E or IRQ3E = 1 IRQ2E or IRQ3E = 0
DDR = 0 DDR = 1
407
Reset R Q D P8n DDR C WP8D WP8D: WP8: RP8: n: Internal data bus (PDB12, PDB14) Write to P8DDR Write to Port 8 Read Port 8 4 or 6
P8n
Reset R Q D P8n DR C WP8
RP8
SCI module
Receive enable Serial receive data
Figure C-8 (c) Schematic Diagram of Port 8, Pins P84 and P86
Table C-7 (c) Data Read from Port 8, Pins P84 and P86
Mode Receive enabled Receive disabled Data Serial receive data Logic level at pin DR value
DDR = 0 DDR = 1
408
Reset R Q D P8 n DDR C WP8D Reset R P8n Q D P8 n DR C WP8
Internal data bus (PDB13, PDB15)
WP8D: WP8: RP8: n:
Write to P8DDR Write to Port 8 Read Port 8 5 or 7
SCI module Transmit enable Serial transmit data
RP8
Figure C-8 (d) Schematic Diagram of Port 8, Pins P85 and P87
Table C-7 (d) Data Read from Port 8, Pins P85 and P87
Mode Transmit enabled Transmit disabled DDR = 0 DDR = 1 Data Serial transmit data Logic level at pin DR value
409
Appendix D Memory Map
Expanded Maximum Modes Mode 1
8 bits H'0000 H'0000
Expanded Maximum Modes Mode 2
16 bits H'000000
Mode 3
8 bits H'000000
Mode 4
16 bits
Vector tables
H'00FF H'00FF
Vector tables
H'0001FF
Vector tables
H'0001FF
Vector tables
Memory
Page 0
Memory
Page 0
Memory
Page 0
Memory
Page 0
H'FE80
H'FE80
H'00FE80
H'00FE80
Register field
H'FF80 H'FF80
Register field
H'00FF80
Register field
H'00FF80
Register field External I/O
H'010000
External I/O
H'FFFF H'FFFF
External I/O
H'010000
External I/O
Page 1
Page 1
H'020000
H'020000
Memory
Memory
H'FF0000
H'FF0000
Page 255
Page 255
H'FFFFFF
H'FFFFFF
Appendix E Pin States
E.1 States of I/O Ports
Table E-1 States of I/O Ports
Hardware Standby Pin Name o, E RD, AS, HWR, LWR RFSH D15 to D8 A15 to A0 P17 to P10 P27 to P20 P37 to P30 P47 to P40 P57 to P50 P67 to P60 P73 to P70 P87 to P80 -- -- 3-state 3-state 3-state 3-state 3-state Prev. state
*4
Software Standby Mode Sleep Mode o=High E=Low 3-state 3-state 3-state 3-state Prev. state 3-state Prev. state 3-state Prev. state
*1
Bus Clock output High*5 High*5 3-state Low Prev. state 3-state Prev. state 3-state Prev. state
*2
Program Execution Clock output RD, AS, HWR, LWR RFSH D15 to D8 A15 to A0 I/O port D7 to D0 I/O port A23 to A16 I/O port or control input/output I/O port
Mode Reset -- -- -- -- -- 1, 3 2, 4 1, 2 3, 4 -- Clock output High High Low
Mode 3-state 3-state 3-state 3-state
Release Mode Mode (Normal Operation) Clock output 3-state High 3-state 3-state Prev. state 3-state Prev. state 3-state Prev. state
*3
3-state 3-state 3-state 3-state 3-state 3-state Low 3-state 3-state 3-state 3-state
Prev. state
*4
Prev. state
Prev. state
--
3-state Prev. state
3-state Prev. state
Input port I/O port
Notes: 3-state: High-impedance state Prev. state: Input pins are in the high-impedance state; output pins maintain their previous state. *1 If P32 is set for BACK output, it goes to the high-impedance state. *2 BREQ can be received, and BACK is high. *3 BACK is low. *4 The on-chip supporting modules are reset, so these pins become input or output pins according to their DDR and DR bits. *5 During refresh cycles, RFSH and AS (and RD) are low.
411
E.2 Pin Status in the Reset State
1. Mode 1 Figure E-1 shows how the pin states change when the RES pin goes low during access to a threestate-access area in mode 1. As soon as RES goes low, all ports are initialized to the input (high-impedance) state. The AS, RD, HWR, and LWR signals all go high. The data bus (D15 to D8) is placed in the highimpedance state. The address bus is initialized 1.5 system clock periods after the low state of the RES pin is sampled. All address bus signals are made low. The clock output pins o and E are initialized 0.5 system clock periods after the low state of the RES pin is sampled. Both pins are initialized to the output state.
412
External memory access
T1 o
T2
T3
RES
Internal reset signal
A15 to A0
H'0000
AS and RD (read)
HWR (write)
High impedance D15 to D8 (write) High impedance I/O ports
Figure E-1 Reset During Access to Three-State-Access Area (Mode 1) 2. Mode 2 Figure E-2 shows how the pin states change when the RES pin goes low during access to a threestate-acdess area in mode 2. As soon as RES goes low, all ports are initialized to the input (high-impedance) state. The AS, RD, HWR, and LWR signals all go high. The data bus (D15 to D0) is placed in the highimpedance state.
413
Pins A15 to A0 of the address bus are initialized to the Low state 1.5 system clock periods after the low state of the RES pin is sampled. The clock output pins o and E are initialized 0.5 o clock periods after the low state of the RES pin is sampled. Both pins are initialized to the output state.
External memory access
T1 o
T2
T3
RES
Internal reset signal
A15 to A0
H'0000
AS and RD (read)
HWR and LWR (write)
High impedance D15 to D 0 (write) High impedance I/O ports
Figure E-2 Reset During Access to Three-State-Access Area (Mode 2)
414
3. Mode 3 Figure E-3 shows how the pin states change when the RES pin goes low during access to a threestate-access area in mode 3. As soon as RES goes low, all ports are initialized to the input (high-impedance) state. The AS, RD, HWR, and LWR signals all go high. The data bus (D15 to D8) is placed in the highimpedance state. The address bus is initialized to the low state 1.5 system clock periods after the low state of the RES pin is sampled. The clock output pins o and E are initialized 0.5 o clock periods after the low state of the RES pin is sampled. Both pins are initialized to the output state.
415
External memory access
T1 o
T2
RES
Internal reset signal
A 23 to A0
H'00000
AS and RD (read)
HWR (write)
High impedance D15 to D8 (write)
High impedance I/O ports
Figure E-3 Reset During Access to Three-State-Access Area (Mode 3) 4. Mode 4 Figure E-4 shows how the pin states change when the RES pin goes low during access to a threestate-access area in mode 4. As soon as RES goes low, all ports are initialized to the input (high-impedance) state. The AS, RD, HWR, and LWR signals all go high. The data bus (D15 to D0) is placed in the highimpedance state.
416
Pins A23 to A0 of the address bus are initialized to the Low state 1.5 system clock periods after the low state of the RES pin is sampled. The clock output pins o and E are initialized 0.5 system clock periods after the low state of the RES pin is sampled. Both pins are initialized to the output state.
T1 o
T2
T3
T1
RES
Internal reset signal
A 23 to A0
H'00000
AS and RD (read)
HWR and LWR (write)
High impedance D15 to D 0 (write)
High impedance I/O ports
Figure E-4 Reset During Access to Three-State-Access Area (Mode 4)
417
Appendix F Package Dimensions
Figure F-1 shows the dimensions of the QFP-112 package.
23.2 0.3
20
84 85 23.2 0.3
57 56
112 1 0.30 0.10 28
29
3.05 Max
0.65
0.13 M
0.17 0.05
2.70
+0.20 -0.16
1.6
0-5
0.10
0.1
0.8 0.3
Figure F-1 Package Dimensions (QFP-112)
418


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