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| Advance Information MC9328MX1/D Rev. 1, 12/2002 MC9328MX1 (DragonBallTM MX1) Integrated Portable System Processor Contents Listing 1 Introduction . . . . . . . . . . . 1 2 Signals and Connections . . . . . . . . . . 4 3 Specifications . . . . . . . . 12 4 Pin-Out and Package Information . . . . . . . . . . 82 1 Introduction Motorola's DragonBallTM family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the DragonBall MX (Media Extensions) series provides a leap in performance with an ARM9TM microprocessor core and highly integrated system functions. DragonBall MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The new MC9328MX1 features the advanced and power-efficient ARM920TTM core that operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller, static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. In addition, the MC9328MX1 is the first BluetoothTM technology-ready applications processor. It is packaged in a 256-pin Mold Array ProcessBall Grid Array (MAPBGA). Figure 1 shows the functional block diagram of the MC9328MX1 and includes feature comparisons with existing DragonBall processors. System Control JTAG/ICE Bootstrap Standard System I/O GPIO Connectivity MMC/SD Memory Stick(R) Host Controller SPI 1 and SPI 2 UART 1 UART 2 SSI/I2S I2C USB Device SmartCard I/F Bluetooth Accelerator Inherited from MC68SZ328 EIM & SDRAMC eSRAM (128K) AIPI 2 DMAC (11 Chnl) Bus Control AIPI 1 VMMU Interrupt Controller CPU Complex ARM9TDMITM Power Control CGM (DPLLx2) MC9328MX1 PWM Timer 1 & 2 RTC Watchdog I Cache D Cache Multimedia Multimedia Accelerator Video Port Human Interface Analog Signal Processor LCD Controller Enhanced from MC68SZ328 New with MC9328MX1 Figure 1. MC9328MX1 Functional Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc., 2002. All rights reserved. Introduction 1.1 Conventions This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Negated means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level one to logic level zero. * * LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal. 1.2 Features To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including the following: * * * * * * * * * * * * * * * ARM920T Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Power Control Module Two Universal Asynchronous Receiver/Transmitters (UART 1 and UART 2) Two Serial Peripheral Interfaces (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Multimedia Card and Secure Digital (MMC/SD) Host Controller Module Memory Stick(R) Host Controller (MSHC) 2 MC9328MX1 Advance Information MOTOROLA Introduction * * * * * * * * * * * SmartCard Interface Module (SIM) Direct Memory Access Controller (DMAC) Synchronous Serial Interface and Inter-IC Sound (SSI/I2S) Module Inter-IC (I2C) Bus Module Video Port General-Purpose I/O (GPIO) Ports Bootstrap Mode Analog Signal Processing (ASP) Module Bluetooth Accelerator (BTA) Multimedia Accelerator (MMA) 256-pin MAPBGA Package 1.3 Target Applications The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging applications such as Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS interactive communicator. 1.4 Product Documentation The following documents are required for a complete description of the MC9328MX1 and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous DragonBall products, the following documents are helpful when used in conjunction with this manual. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM9DT1 Data Sheet Manual (ARM Ltd., order number ARM DDI 0029) ARM Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) EMT9 Technical Reference Manual (ARM Ltd., order number DDI O157E) MC9328MX1 Product Brief (order number MC9328MX1P/D) MC9328MX1 Reference Manual (order number MC9328MX1RM/D) MC68VZ328 Product Brief (order number MC68VZ328P/D) MC68VZ328 User's Manual (order number MC68VZ328UM/D) MC68VZ328 User's Manual Addendum (order number MC68VZ328UMAD/D) MC68SZ328 Product Brief (order number MC68SZ328P/D) MC68SZ328 User's Manual (order number MC68SZ328UM/D) The Motorola manuals are available on the Motorola Semiconductors Web site at http:// www.motorola.com/semiconductors. These documents may be downloaded directly from the Motorola Web site, or printed versions may be ordered. The ARM documentation is available from http://www.arm.com. MOTOROLA MC9328MX1 Advance Information 3 Signals and Connections 1.5 Ordering Information Table 1 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA) package. Table 1. MC9328MX1 Ordering Information Package Type 256-lead MAPBGA 256-lead MAPBGA Frequency 150 MHz 200 MHz Temperature 0C to 70C 0C to 70C Order Number MC9328MX1VH15 MC9328MX1VH20 2 Signals and Connections Table 2 identifies and describes the MC9328MX1 signals that are assigned to package pins. The signals are grouped by the internal module that they are connected to. Table 2. MC9328MX1 Signal Descriptions Signal Name Function/Notes External Bus/Chip-Select (EIM) A [24:0] D [31:0] EB0 EB1 EB2 EB3 OE CS [5:0] Address bus signals Data bus signals MSB Byte Strobe--Active low external enable byte signal that controls D [31:24]. Byte Strobe--Active low external enable byte signal that controls D [23:16]. Byte Strobe--Active low external enable byte signal that controls D [15:8]. LSB Byte Strobe--Active low external enable byte signal that controls D [7:0]. Memory Output Enable--Active low output enables external data bus. Chip-Select--The chip-select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. Active low input signal sent by a flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. Active low signal sent by a flash device causing the external burst device to latch the starting burst address. Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW signal--Indicates whether external access is a read (high) or write (low) cycle. Used as a WE input signal by external DRAM. ECB LBA BCLK RW 4 MC9328MX1 Advance Information MOTOROLA Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name DTACK Function/Notes DTACK Signal--The external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 clock counts have elapsed. Bootstrap BOOT [3:0] System Boot Mode Select--The operational system boot mode of the MC9328MX1 upon system reset is determined by the settings of these pins. SDRAM Controller SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles. SDRAM/SyncFlash interleave addressing mode bank address multiplexed with address signals A [19:16]. These signals are logically equivalent to core address p_addr [12:9] in SDRAM/SyncFlash cycles. SDRAM address signals. SDRAM address signals which are multiplexed with address signals A [10:1]. MA [9:0] are selected on SDRAM/SyncFlash cycles. SDRAM data enable. SDRAM/SyncFlash Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. SDRAM/SyncFlash Chip-select signal which is multiplexed with CS3 signal. These two signals are selectable by programming the system control register. By default, CSD1 is selected, so it can be used as SyncFlash boot chip-select by properly configuring BOOT [3:0] input pins. SDRAM/SyncFlash Row Address Select signal SDRAM/SyncFlash Column Address Select signal SDRAM/SyncFlash Write Enable signal SDRAM/SyncFlash Clock Enable 0 SDRAM/SyncFlash Clock Enable 1 SDRAM/SyncFlash Clock SyncFlash Reset Clocks and Resets EXTAL16M XTAL16M Crystal input (4 MHz to 16 MHz), or a 16 MHz oscillator input when the internal oscillator circuit is shut down. Crystal output SDBA [4:0] SDIBA [3:0] MA [11:10] MA [9:0] DQM [3:0] CSD0 CSD1 RAS CAS SDWE SDCKE0 SDCKE1 SDCLK RESET_SF MOTOROLA MC9328MX1 Advance Information 5 Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name EXTAL32K XTAL32K CLKO RESET_IN 32 KHz crystal input 32 KHz crystal output Clock Out signal selected from internal clock signals. Master Reset--External active low Schmitt trigger input signal. When this signal goes active, all modules (except the reset module and the clock control module) are reset. Reset Out--Internal active low output signal from the Watchdog Timer module and is asserted from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. Power On Reset--Internal active high Schmitt trigger input signal. The POR signal is normally generated by an external RC circuit designed to detect a power-up event. JTAG TRST TDO TDI TCK TMS Test Reset Pin--External active low signal used to asynchronously initialize the JTAG controller. Serial Output for test instructions and data. Changes on the falling edge of TCK. Serial Input for test instructions and data. Sampled on the rising edge of TCK. Test Clock to synchronize test logic and control register access through the JTAG port. Test Mode Select to sequence the JTAG test controller's state machine. Sampled on the rising edge of TCK. DMA Big Endian--Input signal that determines the configuration of the external chip-select space. If it is driven logic-high at reset, the external chip-select space will be configured to little endian. If it is driven logic-low at reset, the external chip-select space will be configured to big endian. ETM ETMTRACESYNC ETMTRACECLK ETMPIPESTAT [2:0] ETMTRACEPKT [7:0] ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM mode. ETM packet signals which are multiplexed with ECB, LBA, BCLK, PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. CMOS Sensor Interface CSI_D [7:0] CSI_MCLK Sensor port data Sensor port master clock Function/Notes RESET_OUT POR BIG_ENDIAN 6 MC9328MX1 Advance Information MOTOROLA Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name CSI_VSYNC CSI_HSYNC CSI_PIXCLK Sensor port vertical sync Sensor port horizontal sync Sensor port data latch clock LCD Controller LD [15:0] FLM/VSYNC LP/HSYNC LSCLK ACD/OE CONTRAST SPL_SPR PS CLS REV LCD Data Bus--All LCD signals are driven low after reset and when LCD is off. Frame Sync or Vsync--This signal also serves as the clock signal output for the gate driver (dedicated signal SPS for Sharp panel HR-TFT). Line pulse or H sync Shift clock Alternate crystal direction/output enable This signal is used to control the LCD bias voltage as contrast control. Program horizontal scan direction (Sharp panel dedicated signal). Control signal output for source driver (Sharp panel dedicated signal). Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SIM SIM_CLK SIM_RST SIM_RX SIM_TX SIM_PD SIM_SVEN SIM Clock SIM Reset Receive Data Transmit Data Presence Detect Schmitt trigger input SIM Vdd Enable SPI SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCLK SPI1_SPI_RDY Master Out/Slave In Slave In/Master Out Slave Select (Selectable polarity) Serial Clock Serial Data Ready Function/Notes MOTOROLA MC9328MX1 Advance Information 7 Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name Function/Notes SPI2 Master TxData Output--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin. SPI2 master RxData Input--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Slave Select--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin. SPI2 Serial Clock--This signal is multiplexed with a GPI/O pin yet shows up as a primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin. General Purpose Timers TIN TMR2OUT Timer Input Capture or Timer Input Clock--The signal on this input is applied to both timers simultaneously. Timer 2 Output USB Device USBD_VMO USBD_VPO USBD_VM USBD_VP USBD_SUSPND USBD_RCV USBD_OE USBD_AFE USB Minus Output USB Plus Output USB Minus Input USB Plus Input USB Suspend Output USB RxD USB OE USB Analog Front End Enable Secure Digital Interface SD_CMD SD_CLK SD_DAT [3:0] SD Command--If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 4.7K-69K external pull up resistor must be added. MMC Output Clock Data--If the system designer does not wish to make use of the internal pull-up, via the Pull-up enable register, a 50K-69K external pull up resistor must be added. SPI2_TXD SPI2_RXD SPI2_SS SPI2_SCLK 8 MC9328MX1 Advance Information MOTOROLA Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name Function/Notes Memory Stick Interface MS_BS MS_SDIO MS_SCLKO MS_SCLKI MS_PI0 MS_PI1 Memory Stick Bus State (Output)--Serial bus control signal Memory Stick Serial Data (Input/Output) Memory Stick External Clock (Input)--External clock source for SCLK Divider Memory Stick Serial Clock (Output)--Serial clock signal General purpose Input0--Can be used for Memory Stick Insertion/Extraction detect General purpose Input1--Can be used for Memory Stick Insertion/Extraction detect UARTs - IrDA/Auto-Bauding UART1_RXD UART1_TXD UART1_RTS UART1_CTS UART2_RXD UART2_TXD UART2_RTS UART2_CTS UART2_DSR UART2_RI UART2_DCD UART2_DTR Receive Data Transmit Data Request to Send Clear to Send Receive Data Transmit Data Request to Send Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Data Terminal Ready Serial Audio Port - SSI (Configurable to I2S protocol) SSI_TXDAT SSI_RXDAT SSI_TXCLK SSI_RXCLK SSI_TXFS SSI_RXFS TxD RxD Transmit Serial Clock Receive Serial Clock Transmit Frame Sync Receive Frame Sync I2C I2C_SCL I2C Clock MOTOROLA MC9328MX1 Advance Information 9 Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name I2C_SDA I2C Data PWM PWMO PWM Output ASP UIN UIP PX1 PY1 PX2 PY2 R1A R1B R2A R2B MIP MIM RVP RVM RVP1 RVM1 RP RM DAC_OP DAC_OM AVDD AGND Positive U analog input (for low voltage, temperature measurement) Negative U analog input (for low voltage, temperature measurement) Positive pen-X analog input Positive pen-Y analog input Negative pen-X analog input Negative pen-Y analog input Positive resistance input (a) Positive resistance input (b) Negative resistance input (a) Negative resistance input (b) Positive voice analog input Negative voice analog input Positive reference for pen ADC Negative reference for pen ADC Positive reference for voice ADC Negative reference for voice ADC Positive bandgap reference Negative bandgap reference Voice DAC positive output Voice DAC negative output Analog power supply Analog ground Bluetooth BT1 BT2 I/O clock signal Output Function/Notes 10 MC9328MX1 Advance Information MOTOROLA Signals and Connections Table 2. MC9328MX1 Signal Descriptions (Continued) Signal Name BT3 BT4 BT5 BT6 BT7 BT8 BT9 BT10 BT11 BT12 BT13 TRISTATE BTRF VDD BTRF GND Input Input Output Output Output Output Output Output Output Output Output Sets all I/O pins to tri-state; May be used for FLASH loading and is pulled low for normal operations. Power supply from external BT RFIC Ground from external BT RFIC Noisy Supply Pins NVDD NVSS Noisy Supply for the I/O pins Noisy Ground for the I/O pins Supply Pins - Analog Modules AVDD AVSS Supply for analog blocks Quiet GND for analog blocks Internal Power Supply QVDD QVSS Power supply pins for silicon internal circuitry GND pins for silicon internal circuitry Substrate Supply Pins SVDD SGND Supply routed through substrate of package; not to be bonded Ground routed through substrate of package; not to be bonded Function/Notes MOTOROLA MC9328MX1 Advance Information 11 Specifications 3 Specifications This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor. 3.1 Maximum Ratings Table 3 provides information on maximum ratings. Table 3. Maximum Ratings Rating Supply voltage Maximum operating temperature range Storage temperature Symbol Vdd TA Test Minimum -0.3 0 -55 Maximum 3.3 70 150 Unit V C C 3.2 Recommended Operating Range Table 4 provides the recommended operating ranges for the supply voltages. MX1 has multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. All other VDD and VSS pins are for the I/O pads voltage supply, and each pair of VDD and VSS provides power to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. Because AVDD pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the AVDD pins from other VDD pins. BTRFVDD is the supply voltage for the Bluetooth interface signals. It is quite sensitive to the data transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used in the system, these Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as other NVDD pins. For more information about I/O pads grouping per VDD, please refer to Table 2 on page 4. Table 4. Recommended Operating Range Rating I/O supply voltage, BTA, USBd, LCD and CSI are only 3V interface I/O supply voltage Internal supply voltage (Core = 150 MHz) Internal supply voltage (Core = 200 MHz) Analog supply voltage Bluetooth I/O voltage (Bluetooth) Bluetooth I/O voltage (Non Bluetooth applications) Symbol NVDD1 NVDD2 QVDD1 QVDD2 AVDD BTRFVDD1 BTRFVDD2 Minimum 2.70 1.70 1.70 1.80 1.70 1.70 1.70 Maximum 3.30 3.30 1.90 2.00 3.30 3.10 3.30 Unit V V V V V V V 12 MC9328MX1 Advance Information MOTOROLA Specifications 3.3 DC Electrical Characteristics Table 5 contains both maximum and minimum DC characteristics of the MC9328MX1. Table 5. Maximum and Minimum DC Characteristics Number or Symbol Parameter Full running operating current at 1.8V (core), 3.3V I/O (Core = 96 MHz, System = 96 MHz, program running in internal SRAM, cache disabled) Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 25C) Standby current (Core = 150 MHz, QVDD = 1.8V, temp = 55C) Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 25C) Standby current (Core = 150 MHz, QVDD = 2.0V, temp = 55C) Input high voltage Input low voltage Output high voltage (IOH = 2.0 mA) Output low voltage (IOL = -2.5 mA) Positive input threshold voltage, Vi =Vih Negative input threshold voltage, Vi =Vil Hysteresis (Vit+ - Vit-) = Vih Input low leakage current (VIN = GND, no pull-up or pull-down) Input high leakage current (VIN = VDD, no pull-up or pull-down) Output high current (VOH = 0.8VDD, VDD = 1.8V) Output low current (VOL = 0.4V, VDD = 1.8V) Output leakage current (Vout = VDD, output is tri-stated) Input capacitance Output capacitance -- -- 4.0 -- -- -- -- 0.640 0.3 -- -- -- -- -- -- -- 1 1 -- A A mA mA A pF pF Minimum Typical Maximum Unit Iop -- 90 -- mA Sidd1 Sidd2 Sidd3 Sidd4 VIH VIL VOH VOL Vit+ VitVhys IIL IIH IOH IOL IOZ Ci Co -- -- -- -- 0.7VDD -- 0.7VDD -- 25 45 35 60 -- -- -- -- -- -- -- -- Vdd+0.2 0.4 Vdd 0.4 1.126 A A A A V V V V V V -4.0 5 5 5 MOTOROLA MC9328MX1 Advance Information 13 Specifications 3.4 AC Electrical Characteristics The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of other signals. All timing specifications are specified at a system operating frequency from 0 MHz to 96 MHz (core operating frequency 150 MHz) with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at pF loading. Table 6. Tri-State Signal Timing Pin TRISTATE Parameter Time from TRISTATE activate until I/O becomes Hi-Z Minimum - Maximum 20.8 Unit ns 3.5 Embedded Trace Macrocell All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the ARM920T processor's TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit shift register comprised of the following: * * * 32-bit data field 7-bit address field A read/write bit The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address field, and a 1 into the read/write bit. A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state. The timing diagram for the ETM9 is shown in Figure 2. See Table 7 on page 14 for the ETM9 timing parameters used in Figure 2. 2a 3a TRACECLK 1 2b 3b TRACECLK (Half-Rate Clocking Mode) Output Trace Port Valid Data Valid Data 4a 4b Figure 2. Trace Port Timing Diagram Table 7. Trace Port Timing Diagram Parameter Table 1.8V +/- 0.10V Ref No. Parameter Minimum 1 CLK frequency 0 Maximum 85 Minimum 0 Maximum 100 MHz 3.0V +/- 0.30V Unit 14 MC9328MX1 Advance Information MOTOROLA Specifications Table 7. Trace Port Timing Diagram Parameter Table (Continued) 1.8V +/- 0.10V Ref No. Parameter Minimum 2a 2b 3a 3b 4a 4b Clock high time Clock low time Clock rise time Clock fall time Output hold time Output setup time 1.3 3 -- -- 2.28 3.42 Maximum -- -- 4 3 -- -- Minimum 2 2 -- -- 2 3 Maximum -- -- 3 3 -- -- ns ns ns ns ns ns 3.0V +/- 0.30V Unit MOTOROLA MC9328MX1 Advance Information 15 Specifications 3.6 DPLL Timing Specifications Parameters of the DPLL are given in Table 8. In this table, Tref is a reference clock period after the predivider and Tdck is the output double clock period. Table 8. DPLL Specifications Parameter Reference clock freq range Pre-divider output clock freq range Double clock freq range Pre-divider factor (PD) Total multiplication factor (MF) MF integer part MF numerator MF denominator Pre-multiplier lock-in time Freq lock-in time after full reset Freq lock-in time after partial reset Phase lock-in time after full reset Phase lock-in time after partial reset Freq jitter (p-p) Phase jitter (p-p) Power supply voltage Power dissipation Test Conditions Vcc = 1.8V Vcc = 1.8V Vcc = 1.8V -- Includes both integer and fractional parts -- Should be less than the denominator -- -- FOL mode for non-integer MF (does not include pre-mult lock-in time) FOL mode for non-integer MF (does not include pre-mult lock-in time) FPL mode and integer MF (does not include pre-mult lock-in time) FPL mode and integer MF (does not include pre-mult lock-in time) -- Integer MF, FPL mode, Vcc=1.8V -- FOL mode, integer MF, fdck = 200 MHz, Vcc = 1.8V Minimum 5 5 80 1 5 5 0 1 -- 250 Typical -- -- -- -- -- -- -- -- -- 280 (56 s) 250 (~50 s) 350 (70 s) 320 (64 s) 0.005 (0.01%) 1.0 (10%) -- -- Maximum 100 30 220 16 15 15 1022 1023 312.5 300 Unit MHz MHz MHz -- -- -- -- -- nsec Tref 220 270 Tref 300 270 -- -- 1.8 -- 400 370 0.01 1.5 2.5 4 Tref Tref 2*Tdck ns V mW 16 MC9328MX1 Advance Information MOTOROLA Specifications 3.7 Reset Module The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up to prevent forward biasing. 1 POR RESET_POR 300ms RESET_DRAM 2 7 cycles @ CLK32 3 14 cycles @ CLK32 HRESET RESET_OUT CLK32 4 HCLK Figure 3. Timing Relationship with POR 5 RESET_IN 14 cycles @ CLK32 HRESET RESET_OUT 4 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN MOTOROLA MC9328MX1 Advance Information 17 Specifications Table 9. Reset Module Timing Parameter Table Ref No. 1 2 3 4 5 6 1.8V +/- 0.10V Parameter Min Width of input POWER_ON_RESET Width of internal POWER_ON_RESET (CLK32 at 32 KHz) 7K to 32K-cycle stretcher for SDRAM reset 14K to 32K-cycle stretcher for internal system reset HRESERT and output reset at pin RESET_OUT Width of external hard-reset RESET_IN 4K to 32K-cycle qualifier 100 300 7 14 4 4 Max -- 300 7 14 -- 4 Min 1 300 Max -- 300 ns ms Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 Cycles of CLK32 3.0V +/- 0.30V Unit 7 7 14 14 4 -- 4 4 18 MC9328MX1 Advance Information MOTOROLA Specifications 3.8 External Interface Module The External Interface Module (EIM) handles the interface to devices external to the MC9328MX1, including generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in Figure 5, and Table 10 defines the parameters of signals. (HCLK) Bus Clock 1a 1b Address Chip-select 2a 2b 3a 3b Read (Write) OE (rising edge) OE (falling edge) EB (rising edge) EB (falling edge) LBA (negated falling edge) LBA (negated rising edge) 6a 5a 4a 4b 4c 4d 5b 5c 5d 6b 6a 6c 7a 7b Burst Clock (rising edge) Burst Clock (falling edge) Read Data 9a 7c 7d 8b 8a 9b Write Data (negated falling) 9a 9c Write Data (negated rising) DTACK_B 10a 10a Figure 5. EIM Bus Timing Diagram Table 10. EIM Bus Timing Parameter Table 1.8 0.10V Ref No. Parameter Min 1a Clock fall to address valid 2.48 Typical 3.31 Max 9.11 Min 2.4 Typical 3.2 Max 8.8 ns 3.0 0.3V Unit MOTOROLA MC9328MX1 Advance Information 19 Specifications Table 10. EIM Bus Timing Parameter Table (Continued) 1.8 0.10V Ref No. Parameter Min 1b 2a 2b 3a 3b 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 7a 7b 7c 7d 8a 8b 9a 9b 9c 10a 1. Clock fall to address invalid Clock fall to chip-select valid Clock fall to chip-select invalid Clock fall to Read (Write) Valid Clock fall to Read (Write) Invalid Clock1 rise to Output Enable Valid Clock1 rise to Output Enable Invalid Clock1 fall to Output Enable Valid Clock1 fall to Output Enable Invalid Clock1 rise to Enable Bytes Valid Clock1 rise to Enable Bytes Invalid Clock1 fall to Enable Bytes Valid Clock1 fall to Enable Bytes Invalid Clock1 fall to Load Burst Address Valid Clock1 fall to Load Burst Address Invalid Clock1 rise to Load Burst Address Invalid Clock1 rise to Burst Clock rise Clock1rise to Burst Clock fall Clock1 fall to Burst Clock rise Clock1 fall to Burst Clock fall Read Data setup time Read Data hold time Clock1 rise to Write Data Valid Clock1 fall to Write Data Invalid Clock1 rise to Write Data Invalid DTACK setup time 1.55 2.69 1.55 1.35 1.86 2.32 2.11 2.38 2.17 1.91 1.81 1.97 1.76 2.07 1.97 1.91 1.61 1.61 1.55 1.55 5.54 0 1.81 1.45 1.63 2.52 Typical 2.48 3.31 2.48 2.79 2.59 2.62 2.52 2.69 2.59 2.52 2.42 2.59 2.48 2.79 2.79 2.62 2.62 2.62 2.48 2.59 -- -- 2.72 2.48 -- -- Max 5.69 7.87 6.31 6.52 6.11 6.85 6.55 7.04 6.73 5.54 5.24 5.69 5.38 6.73 6.83 6.45 5.64 5.84 5.59 5.80 -- -- 6.85 5.69 -- -- Min 1.5 2.6 1.5 1.3 1.8 2.3 2.1 2.3 2.1 1.9 1.8 1.9 1.7 2.0 1.9 1.9 1.6 1.6 1.5 1.5 5.5 0 1.8 1.4 1.62 2.5 Typical 2.4 3.2 2.4 2.7 2.5 2.6 2.5 2.6 2.5 2.5 2.4 2.5 2.4 2.7 2.7 2.6 2.6 2.6 2.4 2.5 -- -- 2.7 2.4 -- -- Max 5.5 7.6 6.1 6.3 5.9 6.8 6.5 6.8 6.5 5.5 5.2 5.5 5.2 6.5 6.6 6.4 5.6 5.8 5.4 5.6 -- -- 6.8 5.5 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3.0 0.3V Unit Clock refers to the system clock signal, HCLK, generated from the System DPLL 20 MC9328MX1 Advance Information MOTOROLA Specifications 3.8.1 DTACK Signal Description The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the external DTACK signal after 1022 HCLK counts have elapsed Only CS5 group supports DTACK signal function when using the external DTACK signal for data acknowledgement. 3.8.2 DTACK Signal Timing Figure 6 shows the access cycle timing used by chip-select 5. The signal values and units of measure for this figure are found in Table 11 on page 21. HCLK CS5 3 RW 1 OE 5 EXT_DTACK 4 2 INT_DTACK Figure 6. DTACK Timing, WSC=111111, DTACK_sel=0 Table 11. Access Cycle Timing Parameters 1.8V +/- 0.1V Ref No. Characteristic Minimum 1 2 3 4 5 Note: 1. n is the number of wait states in the current memory access cycle. The max n is 1022. 2. T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. CS5 asserted to OE asserted External DTACK input setup from CS5 asserted CS5 pulse width External DTACK input hold after CS5 is negated OE negated after CS5 is negated -- 0 3T 0 0 Maximum T -- -- 1.5T 4.5 ns ns ns ns ns Unit MOTOROLA MC9328MX1 Advance Information 21 Specifications HCLK CS5 RW OE 1 EXT_DTACK (WAIT) INT_DTACK Figure 7. DTACK Timing, WSC=111111, DTACK_sel=1 Table 12. Access Cycle Timing Parameters 1.8V +/- 0.10V Ref No. Characteristic Minimum 1 Note: 1. n is the number of wait states in the current memory access cycle. The max n is 1022. 2. T is the system clock period (system clock is 96 MHz). 3. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. External DTACK input setup from CS5 asserted 0 Maximum -- ns Unit 22 MC9328MX1 Advance Information MOTOROLA Specifications 3.8.3 EIM External Bus Timing The following timing diagrams show the timing of accesses to memory or a peripheral. hclk hselm_weim_cs[0] htrans hwrite Seq/Nonseq Read V1 haddr hready weim_hrdata weim_hready Last Valid Data V1 BCLK A[24:0] CS[0] R/W Read Last Valid Address V1 LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN V1 Figure 8. WSC = 1, A.HALF/E.HALF MOTOROLA MC9328MX1 Advance Information 23 Specifications hclk hselm_weim_cs[0] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1) Last Valid Data Unknown weim_hready BCLK A[24:0] CS[0] R/W LBA OE EB SS D[31:0] Last Valid Data Write Data (V1) Write Last Valid Address V1 Figure 9. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF 24 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[0] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK A[24:0] CS[0] R/W LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN Read Last Valid Addr Address V1 Address V1 + 2 1/2 Half Word 2/2 Half Word Figure 10. WSC = 1, OEA = 1, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 25 Specifications hclk hselm_weim_cs[0] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata Last Valid Data Write Data (V1 Word) Last Valid Data weim_hready BCLK A[24:0] CS[0] R/W LBA OE EB SS D[31:0] 1/2 Half Word 2/2 Half Word Last Valid Addr Address V1 Address V1 + 2 Write Figure 11. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 26 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[3] htrans hwrite haddr hready weim_hrdata Nonseq Read V1 Last Valid Data V1 Word weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Address V1 Address V1 + 2 DATA_IN 1/2 Half Word 2/2 Half Word Figure 12. WSC = 3, OEA = 2, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 27 Specifications hclk hselm_weim_cs[3] htrans hwrite haddr hready hwdata Last Valid Data Nonseq Write V1 Write Data (V1 Word) Last Valid Data weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[3] R/W LBA OE Write Address V1 Address V1 + 2 EB SS D[31:0] Last Valid Data 1/2 Half Word 2/2 Half Word Figure 13. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF 28 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK A[24:0] CS[2] R/W Read Last Valid Addr Address V1 Address V1 + 2 LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN 1/2 Half Word 2/2 Half Word Figure 14. WSC = 3, OEA = 4, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 29 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr Nonseq Write V1 hready hwdata weim_hrdata weim_hready BCLK A[24:0] CS[2] R/W LBA OE Last Valid Addr Address V1 Address V1 + 2 Last Valid Data Write Data (V1 Word) Last Valid Data Write EB SS D[31:0] Last Valid Data 1/2 Half Word 2/2 Half Word Figure 15. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF 30 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans Nonseq hwrite haddr hready weim_hrdata Read V1 Last Valid Data V1 Word weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Last Valid Addr Address V1 Address V1 + 2 DATA_IN 1/2 Half Word 2/2 Half Word Figure 16. WSC = 3, OEN = 2, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 31 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr Nonseq Read V1 hready weim_hrdata Last Valid Data V1 Word weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Last Valid Addr Address V1 Address V1 + 2 DATA_IN 1/2 Half Word 2/2 Half Word Figure 17. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF 32 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (V1 Word) Unknown Last Valid Data weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB SS Last Valid Addr Address V1 Address V1 + 2 Write D[31:0] Last Valid Data 1/2 Half Word 2/2 Half Word Figure 18. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 33 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (V1 Word) Last Valid Data Unknown weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB SS D[31:0] Last Valid Addr Address V1 Address V1 + 2 Write Last Valid Data 1/2 Half Word 2/2 Half Word Figure 19. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF 34 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready hwdata weim_hrdata weim_hready Nonseq Nonseq Read V1 Write V8 Last Valid Data Last Valid Data Write Data Read Data BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Write Last Valid Addr Address V1 Address V8 DATA_IN D[31:0] Read Data Last Valid Data Write Data Figure 20. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF MOTOROLA MC9328MX1 Advance Information 35 Specifications Read hclk hselm_weim_cs[2] htrans hwrite haddr Idle Write Nonseq Nonseq Read V1 Write V8 hready hwdata weim_hrdata Last Valid Data Write Data Last Valid Data Read Data weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) Read Write Last Valid Addr Address V1 Address V8 EB (EBC=1) SS DATA_IN D[31:0] Read Data Last Valid Data Write Data Figure 21. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF 36 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata Last Valid Data Nonseq Write V1 Write Data (Word) Last Valid Data weim_hready BCLK A[24:0] CS[3:0] R/W Last Valid Addr Address V1 Address V1 + 2 Write LBA OE EB SS D[31:0] Last Valid Data Write Data (1/2 Half Word) Write Data (2/2 Half Word) Figure 22. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 37 Specifications hclk hselm_weim_cs[4] htrans hwrite haddr Nonseq Nonseq Read V1 Write V8 hready hwdata weim_hrdata weim_hready Last Valid Data Last Valid Data Write Data Read Data BCLK A[24:0] CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Write Last Valid Addr Address V1 Address V8 DATA_IN D[31:0] Read Data Last Valid Data Write Data Figure 23. WSC = 3, CSA = 1, A.HALF/E.HALF 38 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[4] htrans hwrite haddr Nonseq Idle Seq Read V1 Read V2 hready weim_hrdata weim_hready Last Valid Data Read Data (V1) Read Data (V2) BCLK A[24:0] Last Valid Addr Address V1 CNC Address V2 CS[4] R/W LBA Read OE EB (EBC=0) EB (EBC=1) SS DATA_IN Read Data (V1) Read Data (V2) Figure 24. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF MOTOROLA MC9328MX1 Advance Information 39 Specifications hclk hselm_weim_cs[4] htrans hwrite haddr hready hwdata weim_hrdata Nonseq Idle Nonseq Read V1 Write V8 Last Valid Data Last Valid Data Write Data Read Data weim_hready BCLK A[24:0] Last Valid Addr Address V1 CNC Address V8 CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Write DATA_IN D[31:0] Read Data Last Valid Data Write Data Figure 25. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF 40 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[4] htrans hwrite haddr Nonseq Nonseq Nonseq Nonseq Nonseq Nonseq Idle Read E1 Write I1 Read I2 Write I3 Read I4 Write E2 hready w ei La ms _h t rd at a ahb_hrdata hwdata Read Data E1 Read Data (I2) Read Data (I4) Last Valid Data Write Data (I1) Write Data (I3) Write Data (E2) weim_hrdata Last Valid Data Read Data (E1) weim_hready BCLK A[24:0] Last Valid Addr CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN D[31:0] Read Data Read Write Read Write Read Write Address E1 Address I1 Address I2 Address Address I3 I4 Address E2 Last Valid Data I1 Data I2 Data I3 Data I4 Data Write Data (E2) Figure 26. WSC = 1, WEA = 1, WEN = 1, SHEN = 01 or SHEN = 10, A.HALF/E.HALF MOTOROLA MC9328MX1 Advance Information 41 Specifications Dead Cycles hclk hselm_weim_cs[4] htrans hwrite Nonseq Nonseq Nonseq Nonseq Nonseq Nonseq Idle Read E1 Write I1 Read I2 Write I3 Read I4 Write E2 haddr hready w ei La ms _h t rd at a ahb_hrdata Read Data (E1) Read Data (I2) Write Data (I3) Read Data (I4) hwdata weim_hrdata Last Valid Data Last Valid Data Write Data (I1) Write Data (E2) Read Data (E1) weim_hready BCLK A[24:0] CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN D[31:0] Write Read Write Last Valid Addr Address E1 Address I2 Address Address I3 I4 Address E2 Read Read Data Last Valid Data I2 Data I3 Data I4 Data Write Data (E2) Figure 27. WSC = 1, WEA = 1, WEN = 1, EDC = 2, SHEN = 01, A.HALF/E.HALF 42 MC9328MX1 Advance Information MOTOROLA Specifications Dead Cycles hclk hselm_weim_cs[4] htrans hwrite haddr hready w ei La ms _h t rd at a Nonseq Nonseq Nonseq Nonseq Nonseq Nonseq Idle Read E1 Write I1 Read I2 Write Read Write I3 I4 E2 ahb_hrdata hwdata weim_hrdata Read Data (E1) Read Data (I2) Write Data (I3) Read Data (I4) Last Valid Data Last Valid Data Write Data (I1) Write Data (E2) Read Data (E1) weim_hready BCLK A[24:0] CS[4] R/W LBA OE EB (EBC=0) EB (EBC=1) SS DATA_IN Last Valid Addr Address E1 Address I1 Address I2 Address Address I3 I4 Address E2 Read Write Read Write Read Write Read Data Write Data (E2) D[31:0] Last Valid Data I1 Data I2 Data I3 Data I4 Data Figure 28. WSC = 1, WEA = 1, WEN = 1, EDC = 2, SHEN = 10, A.HALF/E.HALF MOTOROLA MC9328MX1 Advance Information 43 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Nonseq Nonseq Idle Read V1 Read V5 Last Valid Addr Address V1 Address V5 CS[2] R/W LBA Read OE EB (EBC=0) EB (EBC=1) SS ECB DATA_IN V1 Word V2 Word V5 Word V6 Word Figure 29. WSC = 3, SYNC = 1, A.HALF/E.HALF 44 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata weim_hready BCLK A[24:0] Last Valid Addr CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Read Last Valid Data V1 Word V2 Word V3 Word V4 Word Nonseq Seq Seq Seq Idle Read V1 Read V2 Read V3 Read V4 Address V1 ECB DATA_IN V1 Word V2 Word V3 Word V4 Word Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD MOTOROLA MC9328MX1 Advance Information 45 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word V3 Word V4 Word Nonseq Seq Seq Seq Idle Read V1 Read V2 Read V3 Read V4 weim_hready BCLK A[24:0] Last Valid Addr Address V1 Address V2 Address V3 Address V4 CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS ECB DATA_IN V1 Word V2 Word V3 Word V4 Word Read Figure 31. WSC = 2, SYNC = 1, DOL = [1/0], SHEN = 01, A.WORD/E.WORD 46 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word Nonseq Seq Idle Read V1 Read V2 weim_hready BCLK A[24:0] Last Valid Addr Address V1 Address V1+2 Address V2 Address V2+2 CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) Read SS ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 32. WSC = 2, SYNC = 1, DOL = [1/0], SHEN = 10, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 47 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word Nonseq Seq Idle Read V1 Read V2 weim_hready BCLK A[24:0] CS[2] R/W LBA OE Read Last Valid Addr Address V1 Address V2 EB (EBC=0) EB (EBC=1) SS ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 33. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 48 MC9328MX1 Advance Information MOTOROLA Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word Non seq Seq Idle Read V1 Read V2 weim_hready BCLK A[24:0] CS[2] Read Last Valid Addr Address V1 R/W LBA OE EB (EBC=0) EB (EBC=1) SS ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 34. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF MOTOROLA MC9328MX1 Advance Information 49 Specifications hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hrdata Last Valid Data V1 Word V2 Word Non seq Seq Idle Read V1 Read V2 weim_hready BCLK A[24:0] CS[2] R/W LBA OE EB (EBC=0) EB (EBC=1) SS Last Valid Addr Address V1 Read ECB DATA_IN V1 1/2 V1 2/2 V2 1/2 V2 2/2 Figure 35. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 50 MC9328MX1 Advance Information MOTOROLA Specifications 3.9 Pen ADC Specifications The specifications for the pen ADC are shown in Table 13 through Table 15. Table 13. Pen ADC System Performance Full Range Resolution1 Non-Linearity Error1 Accuracy 1 1. 13 bits 4 bits 9 bits Tested under input = 0~1.8V at 25C Table 14. Pen ADC Test Conditions Vp max Vp min Vn 1800 mV GND GND ip max ip min in 12 MHz 1.2 KHz 100 Hz 0-1800 mV +7 A 1.5 A 1.5 A Sample frequency Sample rate Input frequency Input range Note: Ru1 = Ru2 = 200K Table 15. Pen ADC Absolute Rating ip max ip min in max in min +9.5 A -2.5 A +9.5 A -2.5 A 3.10 Bluetooth Accelerator The Bluetooth Accelerator (BTA) radio interface supports the Motorola Radio, MC13180 using an SPI interface. This section provides the data bus timing diagrams and SPI interface timing diagrams shown in Figure 36 and Figure 37 on page 53, and the associated parameters shown in Table 16 and Table 17 on page 53. MOTOROLA MC9328MX1 Advance Information 51 Specifications 2 BT CLK (BT1) 7 FS (BT5) Receive 1 PKT DATA (BT3) 3 4 RXTX_EN (BT9) 8 PKT DATA (BT2) 5 6 Transmit Figure 36. Motorola MC13180 Data Bus Timing Diagram Table 16. Motorola MC13180 Data Bus Timing Parameter Table Ref No. 1 2 3 4 5 6 7 8 1. 2. Parameter FrameSync setup time relative to BT CLK rising edge1 FrameSync hold time relative to BT CLK rising edge1 Receive Data setup time relative to BT CLK rising edge1 Receive Data hold time relative to BT CLK rising edge1 Transmit Data setup time relative to RXTX_EN rising edge2 TX DATA period BT CLK duty cycle Transmit Data hold time relative to RXTX_EN falling edge Minimum -- -- -- -- 172.5 Maximum -- -- -- -- 192.5 Unit ns ns ns ns s ns % s 1000 +/- 0.02 40 4 60 10 Please refer to Motorola 2.4 GHz RF Transceiver Module (MC13180) Technical Data documentation. The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and RF_Status (0x0021605C) registers. 52 MC9328MX1 Advance Information MOTOROLA Specifications 1 4 5 6 SPI CLK (BT13) 9 SPI_EN (BT11) 8 SPI_DATA_OUT (BT12) 3 SPI_DATA_IN (BT4) 7 2 Figure 37. SPI Interface Timing Diagram Using Motorola MC13180 Table 17. SPI Interface Timing Parameter Table Using Motorola MC13180 Ref No. 1 2 3 4 5 6 7 8 9 1. Parameter SPI_EN setup time relative to rising edge of SPI_CLK Transmit data delay time relative to rising edge of SPI_CLK Transmit data hold time relative to rising edge of SPI_EN SPI_CLK rise time SPI_CLK fall time SPI_EN hold time relative to falling edge of SPI_CLK Receive data setup time relative to falling edge of SPI_CLK1 Receive data hold time relative to falling edge of SPI_CLK1 SPI_CLK frequency, 50% duty cycle required1 Minimum 15 0 0 0 0 15 15 15 -- Maximum -- 15 15 25 25 -- -- -- 20 Unit ns ns ns ns ns ns ns ns MHz The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by programming SPI_Control (0x00216138) register together with system clock. 3.11 SPI Timing Diagrams To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI 1 Control Register (CONTROLREG1) to match the external SPI master's timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. MOTOROLA MC9328MX1 Advance Information 53 Specifications . 2 SS 1 SPIRDY 3 5 4 SCLK, MOSI, MISO Figure 38. Master SPI Timing Diagram Using SPI_RDY Edge Trigger SS SPIRDY SCLK, MOSI, MISO Figure 39. Master SPI Timing Diagram Using SPI_RDY Level Trigger SS (output) SCLK, MOSI, MISO Figure 40. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 41. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO 7 Figure 42. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge 54 MC9328MX1 Advance Information MOTOROLA Specifications Table 18. Timing Parameter Table for Figure 38 through Figure 42 Ref No. 1 2 3 4 5 6 7 1. 2. 3. Parameter SPI_RDY to SS output low SS output low to first SCLK edge Last SCLK edge to SS output high SS output high to SPI_RDY low SS output pulse width SS input low to first SCLK edge SS input pulse width Minimum 2T 1 3*Tsclk 2 2*Tsclk 0 Tsclk + WAIT 3 T T Maximum -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns T = CSPI system clock period (PERCLK2). Tsclk = Period of SCLK. WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample Period Control Register. 3.12 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MX1 Reference Manual. LSCLK LD[15:0] 1 Figure 43. SCLK to LD Timing Diagram Table 19. LCDC SCLK Timing Parameter Table Ref No. 1 Parameter SCLK to LD valid Minimum -- Maximum 2 Unit ns MOTOROLA MC9328MX1 Advance Information 55 Specifications Non-display region T1 T3 Display region T4 VSYN HSYN OE LD[15:0] T2 Line Y Line 1 Line Y T5 HSYN SCLK OE LD[15:0] VSYN T6 XMAX T7 T8 (1,1) (1,2) (1,X) Figure 44. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Diagram Table 20. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T9 Description End of OE to beginning of VSYN HSYN period VSYN pulse width End of VSYN to beginning of OE HSYN pulse width End of HSYN to beginning to T9 End of OE to beginning of HSYN SCLK to valid LD data End of HSYN idle2 to VSYN edge (for non-display region) End of HSYN idle2 to VSYN edge (for Display region) Minimum T5+T6 +T7+T9 XMAX+5 T2 2 1 1 1 -3 2 1 Corresponding Register Value (VWAIT1*T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH*(T2) VWAIT2*(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 3 2 1 Unit Ts Ts Ts Ts Ts Ts Ts ns Ts Ts 56 MC9328MX1 Advance Information MOTOROLA Specifications Table 20. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table (Continued) Symbol T10 T10 Note: * * * * * * Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 44, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 44, SCLK is always active. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels. Description VSYN to OE active (Sharp = 0), when VWAIT2 = 0 VSYN to OE active (Sharp = 1) when VWAIT2 = 0 Minimum 1 2 Corresponding Register Value 1 2 Unit Ts Ts 3.13 Multimedia Card/Secure Digital Host Controller The DMA interface block controls all data routing between the external data bus (DMA access), internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/ SD module (inner system) and the application (user programming). 3a 3b Bus Clock 1 2 4b 4a 5a CMD_DAT Input Valid Data 5b Valid Data 7 CMD_DAT Output Valid Data Valid Data 6a 6b Figure 45. Chip-Select Read Cycle Timing Diagram Table 21. SDHC Bus Timing Parameter Table Ref No. 1.8V +/- 0.10V Parameter Min CLK frequency at Data transfer Mode (PP)1--10/30 cards CLK frequency at Identification Mode2 Clock high time1--10/30 cards 0 0 6/33 Max 25/5 400 -- Min 0 0 10/50 Max 25/5 400 -- MHz KHz ns 3.0V +/- 0.30V Unit 1 2 3a MOTOROLA MC9328MX1 Advance Information 57 Specifications Table 21. SDHC Bus Timing Parameter Table (Continued) Ref No. 3b 4a 1.8V +/- 0.10V Parameter Min Clock low time1--10/30 cards Clock fall time1--10/30 cards Clock rise time1--10/30 cards Input hold time3--10/30 cards Input setup time3--10/30 cards Output hold time3--10/30 cards Output setup time3--10/30 cards Output delay time3 CL 100 pF / 250 pF (10/30 cards) CL 250 pF (21 cards) CL 25 pF (1 card) 15/75 -- Max -- 10/50 (5.00)3 14/67 (6.67)3 -- -- -- -- 16 Min 10/50 -- Max -- 10/50 ns ns 3.0V +/- 0.30V Unit 4b 5a 5b 6a 6b 7 1. 2. 3. -- 5.7/5.7 5.7/5.7 5.7/5.7 5.7/5.7 0 -- 5/5 5/5 5/5 5/5 0 10/50 -- -- -- -- 14 ns ns ns ns ns ns 3.13.1 Command Response Timing on MMC/SD Bus The card identification and card operation conditions timing are processed in open-drain mode. The card response to the host command starts after exactly NID clock cycles. For the card address assignment, SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and card response is NCR clock cycles as illustrated in Figure 46. The symbols for Figure 46 through Figure 50 are defined in Table 22. Table 22. State Signal Parameters for Figure 46 through Figure 50 Card Active Symbol Z D * CRC Definition High impedance state Data bits Repetition Cyclic redundancy check bits (7 bits) Symbol S T P E Host Active Definition Start bit (0) Transmitter bit (Host = 1, Card = 0) One-cycle pull-up (1) End bit (1) 58 MC9328MX1 Advance Information MOTOROLA Specifications NID cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ Identification Timing NCR cycles Host Command CMD S T Content CRC E Z ****** Z ST CID/OCR Content ZZZ SET_RCA Timing Figure 46. Timing Diagrams at Identification Mode After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 47 on page 59, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC. NCR cycles Host Command CMD S T Content CRC E Z Z P ****** PST Response Content CRC E Z Z Z Command response timing (data transfer mode) NRC cycles Response CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z Timing response end to next CMD start (data transfer mode) NCC cycles Host Command CMD S T Content CRC E Z ****** Z ST Host Command Content CRC E Z Z Z Timing of command sequences (all modes) Figure 47. Timing Diagrams at Data Transfer Mode Figure 48 on page 60 shows basic read operation timing. In a read operation, the sequence starts with a single block read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC , beginning from the last bit of the read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The data stops two clock cycles after the end bit of the stop command. MOTOROLA MC9328MX1 Advance Information 59 Specifications NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z DAT Z****Z Z Z P ****** P S D D D D NAC cycles ***** Read Data Timing of single block read NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T Response Content CRC E Z DAT Z****Z ZZP ****** P S DDDD ***** P ***** P S DDDD ***** NAC cycles Read Data NAC cycles Read Data Timing of multiple block read NCR cycles Host Command CMD S T Content CRC E Z Z P ****** P S T NST DAT D D D D ***** DDDDE Z Z Z ***** Timing of stop command (CMD12, data transfer mode) Response Content CRC E Z Valid Read Data Figure 48. Timing Diagrams at Data Read Figure 49 on page 61 shows the basic write operation timing. As with the read operation, after the card response, the data transfer starts after NWR cycles. The data is suffixed with CRC check bits to allow the card to check for transmission errors. The card sends back the CRC check result as a CC status token on the data line. If there was a transmission error, the card sends a negative CRC status (101); otherwise, a positive CRC status (010) is returned. The card expects a continuous flow of data blocks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. 60 MC9328MX1 Advance Information MOTOROLA MOTOROLA NCR cycles Host Command Response ****** PST Content CRC E Z Z P ****** PP P CMD S T Content CRC E Z Z P DAT Z****Z Z ZZPPS Z ZZPPS Content Content Z****Z DAT CRC E Z Z S Status ES L*L EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CRC status NWR cycles Write Data Timing of the block write command CMD E Z Z P ****** Content CRC E Z Z S Status Content Write Data EZPPS Content Content Write Data CRC status NWR cycles CRC status CRC E Z Z S Status ES L*L DAT Z Z P P S DAT Z Z P P S PPP EZ CRC E Z Z X X X X X X X X X X X X X X X X Z Busy CRC E Z Z X X X X X X X X Z P P S NWR cycles Timing of the multiple block write command Figure 49. Timing Diagrams at Data Write MC9328MX1 Advance Information Specifications 61 62 NCR cycles Host Command Card Response ****** PST CRC E Z Z Z Content ST CMD S T Content CRC E Z Z P Host Command Content CRC E DAT D D D D D D D D D D D D D E Z Z S L ****** Write Data Busy (Card is programming) DAT D D D D D D D Z Z S CRC E Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during data transfer from the host. EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission during CRC status transfer from the card. DAT S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming. DAT Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z S L ****** EZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Stop transmission received after last data block. Card becomes busy programming. Specifications The stop transmission command may occur when the card is in different states. Figure 50 shows the different scenarios on the bus. Figure 50. Stop Transmission During Different Scenarios MC9328MX1 Advance Information MOTOROLA Specifications Table 23. Timing Values for Figure 46 through Figure 50 Parameter Symbol Minimum Maximum Unit MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Command read cycle Command-command cycle Command write cycle Stop transmission cycle NCR NID NAC NRC NCC NWR NST 2 5 2 8 8 2 2 64 5 TAAC + NSAC -- -- -- 2 Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles TAAC: Data read access time -1 defined in CSD register bit[119:112] NSAC: Data read access time -2 in CLK cycles (NSAC*100) defined in CSD register bit[111:104] 3.13.2 SDIO-IRQ and ReadWait Service Handling In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data in this mode. The memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (SD_DAT[1] returns to its high level). In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the "Interrupt Period" during the data access, and the controller must sample SD_DAT[1] during this short period to determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes). CMD ST Content CRC E Z Z P S Response EZZZ ****** ZZZ DAT[1] For 4-bit Interrupt Period S Block Data E IRQ S Block Data E IRQ LH DAT[1] For 1-bit Interrupt Period Figure 51. SDIO IRQ Timing Diagram ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as normal. After all commands are submitted, the user can switch back to the data transfer operation and all counter and status values are resumed as access continues. MOTOROLA MC9328MX1 Advance Information 63 Specifications CMD ****** P S T CMD52 CRC E Z Z Z ****** DAT[1] For 4-bit DAT[2] For 4-bit S Block Data EZZL H S Block Data E S Block Data E Z Z L L L L L L L L L L L L L L L L L L L L L HZ S Block Data E Figure 52. SDIO ReadWait Timing Diagram 3.14 Memory Stick Host Controller The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS, MS_SDIO, and MS_SCLKO (or MS_SCLKI). Communication is always initiated by the MSHC and operates the bus in either four-state or two-state access mode. The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1, BS2, and BS3 states are regarded as one packet length and one communication transfer is always completed within one packet length (in four-state access mode). The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0 and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. 64 MC9328MX1 Advance Information MOTOROLA Specifications 2 1 4 3 5 MS_SCLKI 6 7 8 MS_SCLKO 11 9 10 11 MS_BS 12 12 MS_SDIO(output) 14 13 MS_SDIO (input) (RED bit = 0) 15 16 MS_SDIO (input) (RED bit = 1) Figure 53. MSHC Signal Timing Diagram Table 24. MSHC Signal Timing Parameter Table Ref No. 1 2 3 4 5 6 7 8 9 10 11 MS_SCLKI frequency MS_SCLKI high pulse width MS_SCLKI low pulse width MS_SCLKI rise time MS_SCLKI fall time MS_SCLKO frequency1 MS_SCLKO high pulse width1 MS_SCLKO low pulse width1 MS_SCLKO rise time1 MS_SCLKO fall time1 MS_BS delay time1 Parameter Min -- 20 20 -- -- -- 20 15 -- -- -- Max 25 -- -- 3 3 25 -- -- 5 5 3 Unit MHz ns ns ns ns MHz ns ns ns ns ns MOTOROLA MC9328MX1 Advance Information 65 Specifications Table 24. MSHC Signal Timing Parameter Table (Continued) Ref No. 12 13 14 15 16 1. 2. Parameter MS_SDIO output delay time1,2 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)3 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)4 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)4 Min -- 18 0 23 0 Max 3 -- -- -- -- Unit ns ns ns ns ns 3. 4. Loading capacitor condition is less than or equal to 30pF. An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin, because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin direction changes. If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge. If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge. 3.15 Pulse-Width Modulator The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. 2a System Clock 1 3b 2b 3a 4a PWM Output 4b Figure 54. PWM Output Timing Diagram Table 25. PWM Output Timing Parameter Table Ref No. 1 2a 2b 3a 3b 1.8V +/- 0.10V Parameter Minimum System CLK frequency1 Clock high time1 Clock low time1 Clock fall time1 Clock rise time1 0 3.3 7.5 -- -- Maximum 87 -- -- 5 6.67 Minimum 0 5/10 5/10 -- -- Maximum 100 -- -- 5/10 5/10 MHz ns ns ns ns 3.0V +/- 0.30V Unit 66 MC9328MX1 Advance Information MOTOROLA Specifications Table 25. PWM Output Timing Parameter Table (Continued) Ref No. 4a 4b 1. 1.8V +/- 0.10V Parameter Minimum Output delay time1 Output setup time1 CL of PWMO = 30 pF 3.0V +/- 0.30V Unit Minimum 5 5 Maximum -- -- ns ns Maximum -- -- 5.7 5.7 3.16 SDRAM Memory Controller A write to an address within the memory region initiates the program sequence. The first command issued to the SyncFlash is Load Command Register. A [7:0] determine which operation the command performs. For this write setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the address to be programmed. The next command is Active which registers the row address and confirms the bank address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required. A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The bank and other address lines are driven to the selected address. The second command is Active which sets up the status register read. The bank and row addresses are driven during this command. The third command of the triplet is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from memory on the low order 8 data bits following the CAS latency. MOTOROLA MC9328MX1 Advance Information 67 Specifications 1 SDCLK 2 3S CS 3 3S RAS 3S 3H CAS 3S 3H WE 3H 3H 4S ADDR 4H COL/BA 8 5 6 Data 7 3S ROW/BA DQ DQM 3H Figure 55. SDRAM/SyncFlash Read Cycle Timing Diagram Table 26. SDRAM Timing Parameter Table Ref No. 1 2 3 3S 3H 4S 4H 1.8V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, WE, DQM setup time CS, RAS, CAS, WE, DQM hold time Address setup time Address hold time 2.6 6 11.4 3.42 2.28 3.42 2.28 Maximum -- -- -- -- -- -- -- Minimum 4 4 10 3 2 3 2 Maximum -- -- -- -- -- -- -- ns ns ns ns ns ns ns 3.3V Unit 68 MC9328MX1 Advance Information MOTOROLA Specifications Table 26. SDRAM Timing Parameter Table (Continued) Ref No. 5 5 5 6 7 7 7 8 Note: 1.8V Parameter Minimum SDRAM access time (CL = 3) SDRAM access time (CL = 2) SDRAM access time (CL = 1) Data out hold time Data out high-impedance time (CL = 3) Data out high-impedance time (CL = 2) Data out high-impedance time (CL = 1) Active to read/write command period (RC = 1) CKE is high during the read/write cycle. -- -- -- 2.85 -- -- -- tRCD Maximum 6.84 6.84 -- -- 6.84 6.84 -- -- Minimum -- -- -- 2.5 -- -- -- tRCD Maximum 6 6 -- -- 6 6 -- -- ns ns ns ns ns ns ns ns 3.3V Unit SDCLK 1 CS 3 2 RAS 6 CAS WE 4 ADDR 5 7 COL/BA 8 DQ DATA 9 / BA ROW/BA DQM Figure 56. SDRAM/SyncFlash Write Cycle Timing Diagram MOTOROLA MC9328MX1 Advance Information 69 Specifications Table 27. SDRAM Write Timing Parameter Table Ref No. 1 2 3 4 5 6 7 8 9 Note: 1.8V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Active to read/write command delay Data setup time Data hold time 2.66 6 11.4 3.42 2.28 tRP tRCD 2.28 2.28 Maximum -- -- -- -- -- -- -- -- -- Minimum 4 4 10 3 2 tRP tRCD 2 2 Maximum -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns 3.3V Unit Precharge cycle timing is included in the write timing diagram. SDCLK 1 CS 3 2 RAS 6 CAS 7 7 WE 4 ADDR BA 5 ROW/BA DQ DQM Figure 57. SDRAM Refresh Timing Diagram 70 MC9328MX1 Advance Information MOTOROLA Specifications Table 28. SDRAM Refresh Timing Parameter Table Ref No. 1 2 3 4 5 6 7 1.8V Parameter Minimum SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time Address setup time Address hold time Precharge cycle period Auto precharge command period 2.67 6 11.4 3.42 2.28 tRP tRC Maximum -- -- -- -- -- -- -- Minimum 4 4 10 3 2 tRP tRC Maximum -- -- -- -- -- -- -- ns ns ns ns ns ns ns 3.3V Unit SDCLK CS RAS CAS WE ADDR BA DQ DQM CKE Figure 58. SDRAM Self-Refresh Cycle Timing Diagram MOTOROLA MC9328MX1 Advance Information 71 Specifications 3.17 USB Device Port Four types of data transfer modes exist for the USB module: control transfers, bulk transfers, isochronous transfers, and interrupt transfers. From the perspective of the USB module, the interrupt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. This section covers the transfer modes and how they work from the ground up. Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. USBD_AFE (Output) 1 t ROE_VPO t VMO_ROE 4 USBD_ROE (Output) tPERIOD USBD_VPO (Output) 6 3 tVPO_ROE USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) USBD_VP (Input) USBD_VM (Input) tROE_VMO 2 tFEOPT 5 Figure 59. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 29. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) Ref No. 1 2 3 4 5 6 Parameter tROE_VPO; USBD_ROE active to USBD_VPO low tROE_VMO; USBD_ROE active to USBD_VMO high tVPO_ROE; USBD_VPO high to USBD_ROE deactivated tVMO_ROE; USBD_VMO low to USBD_ROE deactivated (includes SE0) tFEOPT; SE0 interval of EOP tPERIOD; Data transfer rate Min 83.14 81.55 83.54 248.90 160.00 11.97 Max 83.47 81.98 83.80 249.13 175.00 12.03 Unit ns ns ns ns ns Mb/s 72 MC9328MX1 Advance Information MOTOROLA Specifications USBD_AFE (Output) USBD_ROE (Output) USBD_VPO (Output) USBD_VMO (Output) USBD_SUSPND (Output) USBD_RCV (Input) 1 tFEOPR USBD_VP (Input) USBD_VM (Input) Figure 60. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 30. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) Ref No. 1 Parameter tFEOPR; Receiver SE0 interval of EOP Minimum 82 Maximum -- Unit ns MOTOROLA MC9328MX1 Advance Information 73 Specifications 3.18 I2C Module The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA 5 SCL 1 2 3 4 6 Figure 61. Definition of Bus Timing for I2C Table 31. I2C Bus Timing Parameter Table Ref No. 1 2 3 4 5 6 1.8V +/- 0.10V Parameter Minimum Hold time (repeated) START condition Data hold time Data setup time HIGH period of the SCL clock LOW period of the SCL clock Setup time for STOP condition 182 0 11.4 80 480 182.4 Maximum -- 171 -- -- -- -- Minimum 160 0 10 120 320 160 Maximum -- 150 -- -- -- -- ns ns ns ns ns ns 3.0V +/- 0.30V Unit 3.19 Synchronous Serial Interface The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external clock timing diagrams are shown in Figure 63 through Figure 65 on page 76. Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. 74 MC9328MX1 Advance Information MOTOROLA Specifications 1 STCK Output 2 STFS (bl) Output 4 6 STFS (wl) Output 8 12 10 STXD Output 11 31 SRXD Input 32 Note: SRXD input in synchronous mode only. Figure 62. SSI Transmitter Internal Clock Timing Diagram 1 SRCK Output 3 SRFS (bl) Output 5 7 SRFS (wl) Output 9 13 14 SRXD Input Figure 63. SSI Receiver Internal Clock Timing Diagram MOTOROLA MC9328MX1 Advance Information 75 Specifications 15 16 STCK Input 17 18 STFS (bl) Input 20 22 STFS (wl) Input 24 26 STXD Output 27 28 33 SRXD Input Note: SRXD Input in Synchronous mode only 34 Figure 64. SSI Transmitter External Clock Timing Diagram 15 16 SRCK Input 17 19 SRFS (bl) Input 21 23 SRFS (wl) Input 25 29 SRXD Input 30 Figure 65. SSI Receiver External Clock Timing Diagram Table 32. SSI (Port C Primary Function) Timing Parameter Table Ref No. 1.8V +/- 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V +/- 0.30V Unit Internal Clock Operation1 (Port C Primary Function)2 1 2 3 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 95 1.5 -1.2 -- 4.5 -1.7 83.3 1.3 -1.1 -- 3.9 -1.5 ns ns ns 76 MC9328MX1 Advance Information MOTOROLA Specifications Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued) Ref No. 4 5 6 7 8 9 10 11a 11b 12 13 14 1.8V +/- 0.10V Parameter Minimum STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 2.5 0.1 1.48 -1.1 2.51 0.1 14.25 0.91 0.57 12.88 21.1 0 Maximum 4.3 -0.8 4.45 -1.5 4.33 -0.8 15.73 3.08 3.19 13.57 -- -- Minimum 2.2 0.1 1.3 -1.1 2.2 0.1 12.5 0.8 0.5 11.3 18.5 0 Maximum 3.8 -0.8 3.9 -1.5 3.8 -0.8 13.8 2.7 2.8 11.9 -- -- ns ns ns ns ns ns ns ns ns ns ns ns 3.0V +/- 0.30V Unit External Clock Operation (Port C Primary Function)2 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low 92.8 27.1 61.1 -- -- -- -- -- -- -- -- 18.01 8.98 9.12 -- -- -- 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 28.16 18.13 18.24 81.4 40.7 40.7 0 0 0 0 0 0 0 0 15.8 7.0 8.0 -- -- -- 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 24.7 15.9 16.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MOTOROLA MC9328MX1 Advance Information 77 Specifications Table 32. SSI (Port C Primary Function) Timing Parameter Table (Continued) Ref No. 28 29 30 1.8V +/- 0.10V Parameter Minimum STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low 18.47 1.14 0 Maximum 28.5 -- -- Minimum 16.2 1.0 0 Maximum 25.0 -- -- ns ns ns 3.0V +/- 0.30V Unit Synchronous Internal Clock Operation (Port C Primary Function)2 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 15.4 0 -- -- 13.5 0 -- -- ns ns Synchronous External Clock Operation (Port C Primary Function)2 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 -- -- 1.0 0 -- -- ns ns 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length. Table 33. SSI (Port B Alternate Function) Timing Parameter Table Ref No. 1.8V +/- 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V +/- 0.30V Unit Internal Clock Operation1 (Port B Alternate Function)2 1 2 3 4 5 6 7 8 STCK/SRCK clock period1 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 95 1.7 -0.1 3.08 1.25 1.71 -0.1 3.08 -- 4.8 1.0 5.24 2.28 4.79 1.0 5.24 83.3 1.5 -0.1 2.7 1.1 1.5 -0.1 2.7 -- 4.2 1.0 4.6 2.0 4.2 1.0 4.6 ns ns ns ns ns ns ns ns 78 MC9328MX1 Advance Information MOTOROLA Specifications Table 33. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 9 10 11a 11b 12 13 14 1.8V +/- 0.10V Parameter Minimum SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hold time after SRCK low 1.25 14.93 1.25 2.51 12.43 20 0 Maximum 2.28 16.19 3.42 3.99 14.59 -- -- Minimum 1.1 13.1 1.1 2.2 10.9 17.5 0 Maximum 2.0 14.2 3.0 3.5 12.8 -- -- ns ns ns ns ns ns ns 3.0V +/- 0.30V Unit External Clock Operation (Port B Alternate Function)2 15 16 17 18 19 20 21 22 23 24 25 26 27a 27b 28 29 30 STCK/SRCK clock period1 STCK/SRCK clock high period STCK/SRCK clock low period STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STXD valid from high impedance STCK high to STXD high STCK high to STXD low STCK high to STXD high impedance SRXD setup time before SRCK low SRXD hole time after SRCK low 92.8 27.1 61.1 -- -- -- -- -- -- -- -- 18.9 9.23 10.60 17.90 1.14 0 -- -- -- 92.8 92.8 92.8 92.8 92.8 92.8 92.8 92.8 29.07 20.75 21.32 29.75 -- -- 81.4 40.7 40.7 0 0 0 0 0 0 0 0 16.6 8.1 9.3 15.7 1.0 0 -- -- -- 81.4 81.4 81.4 81.4 81.4 81.4 81.4 81.4 25.5 18.2 18.7 26.1 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MOTOROLA MC9328MX1 Advance Information 79 Specifications Table 33. SSI (Port B Alternate Function) Timing Parameter Table (Continued) Ref No. 1.8V +/- 0.10V Parameter Minimum Maximum Minimum Maximum 3.0V +/- 0.30V Unit Synchronous Internal Clock Operation (Port B Alternate Function)2 31 32 SRXD setup before STCK falling SRXD hold after STCK falling 18.81 0 -- -- 16.5 0 -- -- ns ns Synchronous External Clock Operation (Port B Alternate Function)2 33 34 1. SRXD setup before STCK falling SRXD hold after STCK falling 1.14 0 -- -- 1.0 0 -- -- ns ns 2. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function. bl = bit length; wl = word length 80 MC9328MX1 Advance Information MOTOROLA Specifications 3.20 CMOS Sensor Interface The CSI module consists of a control register to configure the interface timing, a control register for statistic data generation, a status register, interface logic, a 32 x 32 image data receive FIFO, and a 16 x 32 statistic data FIFO. Figure 66 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the CSI is programmed to received data in positive edge.The parameters for the timing diagram are listed in Table 34 on page 81. 1 2a 2b csi_pixclk 3a 3b csi_vsync 4b csi_hsync/csi_d valid_data 5 4a Figure 66. CSI Signal Timing Diagram Table 34. CSI Signal Timing Parameter Table Ref No. 1 2a 2b 3a 3b 4a 4b 5 1. Parameter csi_pixclk frequency csi_pixclk high time1 csi_pixclk low time1 csi_pixclk fall time1 csi_pixclk rise time1 csi_hsync/csi_d hold time1 csi_hsync/csi_d setup time1 csi_vsync to data valid time1 CL 30 pF Minimum 0 10.42 10.42 -- -- 1 1 200 Maximum 48 -- -- 5 6.67 -- -- -- Unit MHz ns ns ns ns ns ns ns MOTOROLA MC9328MX1 Advance Information 81 4 Pin-Out and Package Information Table 35. MC9328MX1 BGA Pin Assignments 1 2 3 4 5 6 7 8 UART1_R TS SSI_TXC LK SSI_RXF S SSI_RXD AT SSI_TXD AT SSI_TXF S UART1_C TS VSS NVDD1 NVDD1 CAS MA10 9 UART1_R XD SPI1_SC LK UART1_T XD SPI1_SPI _RDY SPI1_SS SPI1_MIS O SPI1_MO SI QVDD1 VSS NVDD2 TCK RAS 10 11 12 13 14 15 16 82 MC9328MX1 Advance Information MOTOROLA A VSS SD_DAT3 SD_CLK VSS USBD_AFE NVDD4 USBD_V P UART2_C TS USBD_V PO USBD_V M SIM_RST VSS SSI_RXC LK UART2_R XD USBD_V MO UART2_R TS UART2_T XD SIM_CLK VSS VSS VSS VSS RW NVDD3 BT5 BT3 QVDD4 RVP UIP RM B A24 SD_DAT1 SD_CMD SIM_TX USBD_OE BT11 BTRFGN D BT13 BT7 BT1 VSS RVM UIN RP C A23 D31 SD_DAT0 SIM_PD USBD_RCV USBD_SUS PND SD_DAT2 BT8 BTRFVDD RVM1 AVDD2 VSS R1B D A22 D30 D29 SIM_SVEN BT6 DAC_OM RVP1 MIM R1A R2B E A20 A21 D28 D26 BT12 BT4 DAC_OP MIP PY2 PX2 R2A F A18 D27 D25 A19 A16 BT10 BT2 REV PY1 PX1 LP/ HSYNC LD5 LD11 LD14 CSI_D1 CSI_VSY NC CSI_D7 I2C_SCL TDO EXTAL16 M LSCLK SPL_SPR G H J K L M A15 A13 A12 A10 A8 A5 A17 D22 A11 D16 A7 D12 D24 A14 D18 A9 D13 D11 D23 D20 D19 D17 D15 A6 D21 NVDD1 NVDD1 NVDD1 D14 SDCLK SIM_RX NVDD1 NVDD1 VSS NVDD1 VSS BT9 PS VSS NVDD2 TIN RESET_I N RESET_S F SDCKE1 DQM0 CLS LD0 LD6 LD10 PWMO BIG_END IAN RESET_ OUT BOOT3 SDCKE0 CONTRAST LD2 LD7 LD12 CSI_MCLK CSI_D4 ACD/OE LD4 LD8 LD13 CSI_D0 CSI_HSY NC CSI_PIXC LK TRST BOOT1 TRISTAT E FLM/VSYNC LD9 QVDD3 TMR2OUT CSI_D2 CSI_D6 LD1 LD3 VSS LD15 CSI_D3 CSI_D5 N P R A4 A3 EB2 EB1 D9 EB3 D10 EB0 A1 D7 CS3 CS4 A0 D6 D8 D4 ECB D5 PA17 D2 LBA D1 D3 BCLK DQM1 DQM3 D0 BOOT2 BOOT0 POR TMS I2C_SDA QVDD2 TDI XTAL32K EXTAL32 K VSS T VSS A2 OE CS5 CS2 CS1 CS0 MA11 DQM2 SDWE CLKO AVDD1 XTAL16M Pin-Out and Package Information 4.1 MAPBGA Package Dimensions Figure 67 illustrates the MAPBGA 14 mm x 14 mm x 1.30 mm package, which has 0.8 mm spacing between the pads. The device designator for the MAPBGA package is VH. Figure 67. MC9328MX1 MAPBGA Mechanical Drawing MOTOROLA MC9328MX1 Advance Information 83 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. All other product or service names are the property of their respective owners. The Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc. under license. ARM and the ARM POWERED logo are the registered trademarks of ARM Limited. ARM9, ARM920T, and ARM9TDMI are the trademarks of ARM Limited. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2002 MC9328MX1/D |
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