View MC68HC908Q_991016.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

9/2002
MC68HC908QY4, MC68HC908QT4, MC68HC908QY2, MC68HC908QT2, MC68HC908QY1, MC68HC908QT1
MC68HC908QY4MC68HC908QT4MC68HC908QY2 MC68HC908QT2MC68HC908QY1 MC68HC908QT1 MC68HC908QY4 Data Sheet Motorola MC68HC908QY4/D : MC68HC908QY4 Data Sheet Summary Motorola MC68HC908QY4SM/D
MC68HC908QYxMC68HC908QTx MC68HC08 M68HC08 8 MC68HC08 CPU08 MC68HC908QYxMC68HC908QTx MC 1 1 1. MCU
MC68HC908QY1 MC68HC908QY2 MC68HC908QY4 MC68HC908QT1 MC68HC908QT2 MC68HC908QT4
: C = -40C to +85C V = -40C to +105C ( VDD = 5 V) M = -40C to +125C ( VDD = 5 V) P = Plastic dual in-line package (PDIP) DW = Small outline integrated circuit package (SOIC) DT = Thin shrink small outline package (TSSOP)
--
FLASH 1536 1536 4096
16 PDIP 16 SOIC 16 TSSOP
--
1536 1536 4096 8 PDIP 8 SOIC
(c) Motorola, Inc., 2002
MC68HC908QY4
MC68HC908QYxMC68HC908QTx
* * * * * * * *
M68HC08 M68HC05 5V 3V VDD 5V 8MHz3V 4MHz 8 3.2MHz 5% STOP CONFIG MCU LVI FLASH FLASH FLASH /
- -
MC68HC908QY4 MC68HC908QT4 FLASH 4096 MC68HC908QY2MC68HC908QY1MC68HC908QT2 MC68HC908QT1 FLASH 1536
* * * *
128 RAM 16 TIM MC68HC908QY2 MC68HC908QY4 MC68HC908QT2 MC68HC908QT4 4 8 ADC 5 13 I/O
- -
I/O I/O
* * *
6 LVI CONFIG
- - - -
COP
* * * * *
IRQ RST I/O IRQ RST I/O
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 2 MOTOROLA
* *
WAIT STOP MC68HC908QY4MC68HC908QY2 MC68HC908QY1
- - -
16 PDIP 16 SOIC 16 TSSOP 8 PDIP 8 SOIC
*
MC68HC908QT4 MC68HC908QT2 MC68HC908QT1
- -
MC68HC908QYxMC68HC908QTx 1
CPU08 64K 3 $0000-$003F 3
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 3
MC68HC908QY4
DDRA
PTA
8-BIT ADC
4 MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1
PTB[0:7] VDD PTB DDRB POWER SUPPLY VSS PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2 PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 CPU REGISTERS INDEX REGISTER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER V11HINZC BREAK MODULE POWER-ON RESET MODULE CPU CONTROL 68HC08 CPU ACCUMULATOR SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE ALU CLOCK GENERATOR 16-BIT TIMER MODULE 128 BYTES RAM MC68HC908QY4 AND MC68HC908QT4: 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH COP MODULE MONITOR ROM RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up PTB[0:7]: Not available on 8-pin devices - MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
MOTOROLA
1. MC68HC908QYxMC68HC908QTx

VDD PTA5/OSC1/KBI5 PTA4/OSC2/KBI4 PTA3/RST/KBI3
1 2 3 4
8 7 6 5
VSS PTA0/TCH0/KBI0 PTA1/TCH1/KBI1 PTA2/IRQ/KBI2
VDD PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTA3/RST/KBI3
1 2 3 4
8 7 6 5
VSS PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2
8 MC68HC908QT1 PDIP/SOIC
8 MC68HC908QT2 MC68HC908QT4 PDIP/SOIC
VDD PTB7 PTB6 PTA5/OSC1/KBI5 PTA4/OSC2/KBI4 PTB5 PTB4 PTA3/RST/KBI3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VSS PTB0 PTB1 PTA0/TCH0/KBI0 PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2
VDD PTB7 PTB6 PTA5/OSC1/AD3/KBI5 PTA4/OSC2/AD2/KBI4 PTB5 PTB4 PTA3/RST/KBI3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VSS PTB0 PTB1 PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2
16 MC68HC908QY1 PDIP/SOIC
16 MC68HC908QY2 MC68HC908QY4 PDIP/SOIC
PTA0/TCH0/KBI0 PTB1 PTB0 VSS VDD PTB7 PTB6 PTA5/OSC1/KBI5
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PTA1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2 PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/KBI4
PTA0/AD0/TCH0/KBI0 PTB1 PTB0 VSS VDD PTB7 PTB6 PTA5/OSC1/AD3/KBI5
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PTA1/AD1/TCH1/KBI1 PTB2 PTB3 PTA2/IRQ/KBI2 PTA3/RST/KBI3 PTB4 PTB5 PTA4/OSC2/AD2/KBI4
16 MC68HC908QY1 TSSOP
16 MC68HC908QY2 MC68HC908QY4 TSSOP
2.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 5
MC68HC908QY4

2.
Pin Name VDD VSS Power supply Power supply ground PTA0 -- General purpose I/O port Description Input/Output Power Power Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input Input Input Input/Output Input Input Input/Output Output Output Input Input Input/Output Input Input Input Input/Output
PTA0
AD0 -- ADC channel 0 input TCH0 -- Timer Channel 0 I/O KBI0 -- Keyboard interrupt input 0 PTA1 -- General purpose I/O port
PTA1
AD1 -- ADC channel 1 input TCH1 -- Timer Channel 1 I/O KBI1 -- Keyboard interrupt input 1 PTA2 -- General purpose input-only port
PTA2
IRQ -- External interrupt with programmable pullup and Schmitt trigger input KBI2 -- Keyboard interrupt input 2 PTA3 -- General purpose I/O port
PTA3
RST -- Reset input, active low with internal pullup and Schmitt trigger KBI3 -- Keyboard interrupt input 3 PTA4 -- General purpose I/O port
PTA4
OSC2 -- XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) AD2 -- ADC channel 2 input KBI4 -- Keyboard interrupt input 4 PTA5 -- General purpose I/O port
PTA5
OSC1 -- XTAL, RC, or external oscillator input AD3 -- ADC channel 3 input KBI5 -- Keyboard interrupt input 5
PTB[0:7](1)
8 general-purpose I/O ports.
1. The PTB pins are not available on the 8-pin packages.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 6 MOTOROLA
$0000 $003F $0040 $007F $0080 $00FF $0100 $27FF $2800 $2DFF $2E00 $EDFF $EE00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0F $FE10 $FFAF $FFB0 $FFBD $FFBE $FFBF $FFC0 $FFC1 $FFC2 $FFCF $FFD0 $FFFF
I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 9984 BYTES AUXILIARY ROM 1536 BYTES UNIMPLEMENTED 49152 BYTES FLASH MEMORY MC68HC908QT4 AND MC68HC908QY4 4096 BYTES BREAK STATUS REGISTER (BSR) RESET STATUS REGISTER (SRSR) BREAK AUXILIARY REGISTER (BRKAR) BREAK FLAG CONTROL REGISTER (BFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR) FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS HIGH REGISTER (BRKH) BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVISR RESERVED FOR FLASH TEST 3 BYTES MONITOR ROM 416 BYTES FLASH 14 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) RESERVED FLASH INTERNAL OSCILLATOR TRIM VALUE RESERVED FLASH FLASH 14 BYTES USER VECTORS 48 BYTES UNIMPLEMENTED 9984 BYTES AUXILIARY ROM 1536 BYTES $0100 $27FF $2800 $2DFF $2E00 UNIMPLEMENTED 51712 BYTES
$F7FF $F800 $FDFF
FLASH MEMORY 1536 BYTES MC68HC908QT1, MC68HC908QT2, MC68HC908QY1, and MC68HC908QY2 Memory Map
3.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 7
MC68HC908QY4
.
Addr. $0000 $0001 $0002 $0003 $0004 $0006 $0007- $000A $000B $000C $000D- $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B- $0035 $0036 $0037 $0038 $0039- $003B $003C $003D $003E $003F
Register PTA PTB Unimplemented Unimplemented DDRA DDRB Unimplemented Unimplemented PTAPUE PTBPUE Unimplemented Unimplemented KBSCR KBIER Unimplemented INTSCR CONFIG2 CONFIG1 TSC TCNTH TCNTL TMODH TMODL TSC0 TCH0H TCH0L TSC1 TCH1H TCH1L Unimplemented Unimplemented OSCSTAT Unimplemented OSCTRIM Unimplemented Unimplemented ADSCR Unimplemented ADR ADICLK
Bit 7 0 PTB7
6 AWUL PTB6
5 PTA5 PTB5
4 PTA4 PTB4
3 PTA3 PTB3
2 PTA2 PTB2
1 PTA1 PTB1
Bit 0 PTA0 PTB0
0 DDRB7
0 DDRB6
DDRA5 DDRB5
DDRA4 DDRB4
DDRA3 DDRB3
0 DDRB2
DDRA1 DDRB1
DDRA0 DDRB0
OSC2EN PTBPUE7
0 PTBPUE6
PTAPUE5 PTBPUE5
PTAPUE4 PTBPUE4
PTAPUE3 PTBPUE3
PTAPUE2 PTBPUE2
PTAPUE1 PTBPUE1
PTAPUE0 PTBPUE0
0 0 0 IRQPUD COPRS TOF Bit 15 Bit 7 Bit 15 Bit 7 CH0F Bit 15 Bit 7 CH1F Bit 15 Bit 7
0 AWUIE 0 IRQEN LVISTOP TOIE Bit 14 Bit 6 Bit 14 Bit 6 CH0IE Bit 14 Bit 6 CH1IE Bit 14 Bit 6
0 KBIE5 0 LVIRSTD TSTOP Bit 13 Bit 5 Bit 13 Bit 5 MS0B Bit 13 Bit 5 0 Bit 13 Bit 5
0 KBIE4 0 OSCOPT1 LVIPWRD TRST Bit 12 Bit 4 Bit 12 Bit 4 MS0A Bit 12 Bit 4 MS1A Bit 12 Bit 4
KEYF KBIE3 IRQF1 OSCOPT0 LVI5OR3 0 Bit 11 Bit 3 Bit 11 Bit 3 ELS0B Bit 11 Bit 3 ELS1B Bit 11 Bit 3
ACKK KBIE2 ACK1 SSREC PS2 Bit 10 Bit 2 Bit 10 Bit 2 ELS0A Bit 10 Bit 2 ELS1A Bit 10 Bit 2
IMASKK KBIE1 IMASK1 STOP PS1 Bit 9 Bit 1 Bit 9 Bit 1 TOV0 Bit 9 Bit 1 TOV1 Bit 9 Bit 1
MODEK KBIE0 MODE1 RSTEN COPD PS0 Bit 8 Bit 0 Bit 8 Bit 0 CH0MAX Bit 8 Bit 0 CH1MAX Bit 8 Bit 0
ECGON TRIM7 TRIM6 TRIM5 TRIM4 TRIM3 TRIM2 TRIM1
ECGST TRIM0
COCO AD7 ADIV2
AIEN AD6 ADIV1
ADCO AD5 ADIV0
CH4 AD4 0
CH3 AD3 0
CH2 AD2 0
CH1 AD1 0
CH0 AD0 0
= Unimplemented or Reserved
4.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 8 MOTOROLA
Addr. $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D- $FE0F $FFBE $FFBF $FFC0 $FFC1 $FFFF
Register BSR SRSR BRKAR BFCR INT1 INT2 INT3 Reserved FLCR BRKH BRKL BRKSCR LVISR Reserved for FLASH Test Reserved for FLASH Test FLBPR Reserved TRIMLOC Reserved COPCTL
Bit 7 POR 0 BCFE 0 IF14 0 0 Bit 15 Bit 7 BRKE LVIOUT
6 PIN 0 IF5 0 0 0 Bit 14 Bit 6 BRKA 0
5 COP 0 IF4 0 0 0 Bit 13 Bit 5 0 0
4 ILOP 0 IF3 0 0 0 Bit 12 Bit 4 0 0
3 ILAD 0 0 0 0 HVEN Bit 11 Bit 3 0 0
2 MODRST 0 IF1 0 0 MASS Bit 10 Bit 2 0 0
1 SBSW LVI 0 0 0 0 ERASE Bit 9 Bit 1 0 0
Bit 0 0 BDCOP 0 0 IF15 PGM Bit 8 Bit 0 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
NON-VOLATILE TRIM ADJUSTMENT VALUE WRITE ANY VALUE TO RESET COP WATCHDOG = Unimplemented or Reserved
4.
.
3.
IF15 IF14 IF13 IF6 IF5 IF4 IF3 IF2 IF1 -- --
$FFDE $FFDF $FFE0 $FFE1 -- $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 -- $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF
ADC 1 0 IRQ
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 9
MC68HC908QY4
FLASH
MC68HC908QYxMC68HC908QTx FLASH 4096 1536 80 FLASH FLASH 64 32
* * *
MC68HC908QY4 MC68HC908QT4 4096 $EE00-$FDFF MC68HC908QY2MC68HC908QT2MC68HC908QY1 MC68HC908QT1 1536 $F800-$FDFF $FFB0-$FFFF
FLASH 0 FLASH 1FLASH FLASH
FLASH FLCR FLCR
FLASH FLCR FLASH
:
$FE08 7 0 0 6 0 0 5 0 0 4 0 0 3 HVEN 0 2 MASS 0 1 ERASE 0 0 PGM 0
:
5. FLASH FLCR HVEN -- PGM=1 ERASE=1 HVEN FLASH 1 = FLASH MASS -- ERASE=1 FLASH 1 = 0 = ERASE -- FLASH ERASE PGM 1 1 = PGM -- FLASH 1 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 10 MOTOROLA
FLASH
FLASH 64 $XX00$XX40 $XX80 $XXC0 80 FLASH $FFB0-$FFBF $FFC0-$FFFF FLASH 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. ERASE 1 MASS 0 FLASH FLASH tnvs 10s HVEN 1 tErase 1ms 4ms ERASE MASS 0 tnvh 5s HVEN 0 trcv 1sFLASH
FLASH FLASH FLASH FLASH FLASH RAM FLASH 10000 4ms FLASH 1000 1ms FLASH FLASH FLASH 32 $XX00$XX20$XX40$XX60$XX80$XXA0$XXC0 $XXE0 FLASH FLASH $FF 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. PGM 1 FLASH FLASH FLASH tnvs 10s HVEN 1 tpgs 5s tPROG 30s 7 8 PGM 0 tnvh 5s HVEN 0 trcv 1sFLASH
FLASH FLASH FLASH
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 11
MC68HC908QY4
FLASH FLBPR FLBPR
FLASH FLASH FLASH FLASH HVEN FLASH FLASH $FFFF FLBPR 0 FLASH FLBPR $FF FLASH FLBPR FLASH
:
$FFBE 7 BPR7 6 BPR6 5 BPR5 4 BPR4 3 BPR3 2 BPR2 1 BPR1 0 BPR0
:
1
6. FLASH FLBPR BPR[7:0] -- FLASH 8 FLASH 8
16-BIT MEMORY ADDRESS START ADDRESS OF PROTECTED FLASH BLOCK 1 1 FLBPR VALUE 0 0 0 0 0 0
7. FLASH
4. FLASH
BPR[7:0] $00-$B8 $B9 (1011 1001) $BA (1011 1010) $BB (1011 1011) $BC (1011 1100) and so on... $DE (1101 1110) $DF (1101 1111) $FE (1111 1110) $FF $F780 (1111 0111 1000 0000) $F7C0 (1111 0111 1100 0000) $FF80 (1111 1111 1000 0000) FLBPR, OSCTRIM, and vectors are protected The entire FLASH memory is not protected. Start of Address of Protect Range The entire FLASH memory is protected. $EE40 (1110 1110 0100 0000) $EE80 (1110 1110 1000 0000) $EEC0 (1110 1110 1100 0000) $EF00 (1110 1111 0000 0000)
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 12 MOTOROLA
CONFIG CONFIG1, CONFIG2
CONFIG CONFIG 0 CONFIG CONFIG CONFIG CONFIG $001E $001F
: : POR:
7 0 0 R 6 IRQEN 0 0 = Reserved 5 R 0 0 4 0 0 U = Unaffected 3 0 0 2 R 0 0 1 R 0 0 0 RSTEN U 0
$001E IRQPUD
OSCOPT1 OSCOPT0
8. CONFIG 2 CONFIG2 IRQPUD -- IRQ 0 = IRQ VDD IRQEN=1 IRQEN -- IRQ 1 = PTA2/IRQ/KBI2 IRQ 0 = PTA2/IRQ/KBI2 PTA2 KBI2 OSCOPT1:OSCOPT2 -- (0:0) (0:1) (1:0) (1:1) RC XTAL
RSTEN -- RST 1 = PTA2/RST/KBI3 RST 0 = PTA2/RST/KBI3 PTA3 KBI3 POR RSTEN
:
$001F 7 COPRS 0 0 U = Unaffected 6 0 0 5 0 0 4 0 0 3 U 0 2 SSREC 0 0 1 STOP 0 0 0 COPD 0 0
LVISTOP LVIRSTD LVIPWRD LVI5OR3
: POR:
9. CONFIG 1 (CONFIG1) COPRS STOP -- COP 1 = COP 213 -24 BUSCLKX4 0 = COP 218 -24 BUSCLKX4 COP COP COPCTL $FFFF
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 13
MC68HC908QY4
COPRS STOP ) -- 1 = 16ms 0 = 512ms LVISTOP -- STOP LVI 1 = STOP LVI 0 = STOP LVI LVIRSTD -- LVI 1 = LVI 0 = LVI LVIPWRD -- LVI 1 = LVI LVI5OR3 -- LVI 5V 3V 1 = LVI 5V 0 = LVI 3V POR LVI5OR3 SSREC -- STOP 1 = 32 BUSCLKX4 STOP 0 = 4096 BUSCLKX4 STOP LVI STOP 4096 BUSCLKX4 STOP -- STOP 1 = STOP 0 = STOP COPD -- COP 1 = COP
LVISR LVI LVISR
LVI LVI LVISR VDD VTRIPF
: :
7 0 R 6 0 0 = Reserved 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 R 0
$FE0C LVIOUT
10. LVI LVISR) LVIOUT -- LVI VDD VTRIPF 1 VDD VTRIPF 0
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 14 MOTOROLA
IRQ INTSCR INTSCR INTSCR
:
$001D 7 0 0 6 0 0 5 0 0 4 0 0 3 IRQF1 0 2 ACK1 0 1 IMASK1 0 0 MODE1 0
:
11. IRQ INTSCR IRQF1 -- IRQ IRQ 1 1 = IRQ ACK1 -- IRQ 1 IRQ ACK1 0 IMASK1 -- IRQ 1 = IRQ MODE1 -- IRQ 1 = 0 =
SIM SRSR SRSR
SIM POR 1
:
$FE01 POR: 7 POR 1 6 PIN 0 5 COP 0 4 ILOP 0 3 ILAD 0 2 MODRST 0 1 LVI 0 0 0 0
12. SIM SRSR POR -- 1 = POR PIN -- 1 = RST COP -- 1 = COP ILOP -- 1 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 15
MC68HC908QY4
ILAD -- 1 = MODRST -- 1 = $FFFE $FFFF $FF PTA2/IRQ=VDD LVI 1 =
INT1, INT2, INT3)
3 3
:
$FE04 7 0 0 6 IF5 0 TOF 5 IF4 0 TCH1 4 IF3 0 TCH0 3 0 0 2 IF1 0 IRQ 1 0 0 0 0 0
:
:
13. 1 INT1
:
$FE05 7 IF14 0 KBI 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0
:
:
14. 2 INT2
:
$FE06 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 IF15 0 ADC
:
: 15. 3 INT3
IFxx 3 1 = 0 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 16 MOTOROLA
CPU
16 CPU 5 CPU
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
16. CPU
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 17
MC68HC908QY4
5 M68HC08 16 5.

ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
VH I NZC

A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4

ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff

2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT - IX2 IX1 IX SP1 SP2 IMM DIR EXT - IX2 IX1 IX SP1 SP2
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT - IX2 IX1 IX SP1 SP2
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
DIR INH - - INH IX1 IX SP1 DIR INH INH -- IX1 IX SP1
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F rr dd dd dd dd dd dd dd dd
Arithmetic Shift Right
b7 b0
C
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BCLR n, opr
Clear Bit n in M
Mn 0
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 18 MOTOROLA
5.

BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
VH I NZC

25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 rr rr rr rr rr rr rr rr rr rr

3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3
- - - - - - REL - - - - - - REL - - - - - - REL
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 - IX1 IX SP1 SP2
Bit Test
(A) & (M)
0--
ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
BRN rel
Branch Never
PC (PC) + 2
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 19
MC68HC908QY4
5.

00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
VH I NZC

dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd

5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
DIR (b0) DIR (b1) DIR (b2) - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00
- - - - - - REL
AD
rr
4
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel Compare and Branch if Equal CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr Clear Carry Bit Clear Interrupt Mask
DIR IMM IMM - - - - - - IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT - - IX2 IX1 IX SP1 SP2 DIR INH 1 INH IX1 IX SP1
31 41 51 61 71 9E61 98 9A
dd rr ii rr ii rr ff rr rr ff rr
5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4
Clear
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
Complement (One's Complement)
M A X M M M
(M) = $FF - (M) (A) = $FF - (M) (X) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M) (M) = $FF - (M)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 ii ii+1 dd
Compare H:X with M
(H:X) - (M:M + 1)
IMM - - DIR
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 20 MOTOROLA
5.

CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
VH I NZC

A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B

ii dd hh ll ee ff ff ff ee ff

2 3 4 4 3 2 4 5 2
Compare X with M
(X) - (M)
IMM DIR EXT - - IX2 IX1 IX SP1 SP2
Decimal Adjust A
(A)10
U - - INH
DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR INH PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 IX PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1
dd rr rr rr ff rr rr ff rr
5 3 3 5 4 6 4 1 1 4 3 5 7
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
- - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH - IX1 IX SP1
Exclusive OR M with A
A (A M)
0--
2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT - IX2 IX1 IX SP1 SP2
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 21
MC68HC908QY4
5.

LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX
Load H:X from M
H:X (M:M + 1)
VH I NZC
0--

45 55 AE BE CE DE EE FE 9EEE 9EDE

ii jj dd ii dd hh ll ee ff ff ff ee ff

3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3
- IMM DIR IMM DIR EXT - IX2 IX1 IX SP1 SP2
Load X from M
X (M)
0--
Logical Shift Left (Same as ASL)
C b7 b0
0
DIR INH - - INH IX1 IX SP1 DIR INH INH --0 IX1 IX SP1 DD - DIX+ IMD IX+D
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
C
Move
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
Unsigned multiply
- 0 - - - 0 INH DIR INH - - INH IX1 IX SP1
Negate (Two's Complement)
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT - IX2 IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
2 3 4 4 3 2 4 5 2 2 2 2 2 2
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 22 MOTOROLA
5.

ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
VH I NZC

4 1 1 4 3 5 4 1 1 4 3 5 1
Rotate Left through Carry
C b7 b0
DIR INH - - INH IX1 IX SP1 DIR INH - - INH IX1 IX SP1
39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Right through Carry
b7 b0
C
Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
7
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 - - IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Subtract with Carry
A (A) - (M) - (C)
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
IMM DIR EXT IX2 - - IX1 IX SP1 SP2
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 23
MC68HC908QY4
5.

PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC

SWI
Software Interrupt
- - 1 - - - INH
83
9
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH - INH IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94
2 1 1 3 1 1 3 2 4 2 1 2
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1 n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) #
? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 24 MOTOROLA
OSC)
MC68HC908QYx MC68HC908QTx 1. 3.2MHz 5 0.2 2. OSC1 3. RC OSC1 RC 4. OSC1 OSC2

OSCRCXTAL 1. OSCOPT[1:0]=1:1 PTA4 OSC2 OSCOPT[1:0] 2. CONFIG2 OSCOPT[1:0] OSC1 OSC2 3. 4096 4MHz 1ms 4. OSC OSCSTAT ECGON 1 5. ECGON OSC 6. OSC 7. OSC OSCSTAT ECGST
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 25
MC68HC908QY4
FROM SIM
TO SIM BUSCLKX4
TO SIM BUSCLKX2
XTALCLK SIMOSCEN
/2
MCU
PTA5/OSC1/AD3/KBI5 RB PTA4/OSC2/AD2/KBI4
X1
RS(1)
C1
C2
Note 1. RS can be zero (shorted) when used with higher-frequency crystals. Refer to crystal manufacturer's data.
17. XTAL
OSCRCOPT FROM SIM INTCLK 0 BUSCLKX4 1 SIMOSCEN EXTERNAL RC EN OSCILLATOR RCCLK /2 BUSCLKX2 TO SIM TO SIM
1 PTA4 I/O
0
PTA4 OSC2EN
MCU
PTA5/OSC1/AD3/KBI5 VDD REXT PTA4/OSC2/AD3/KBI4
18. RC
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 26 MOTOROLA
OSCSTAT
OSCSTAT
:
$0036 7 R 0 R 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 R 0 1 ECGON 0 0 ECGST 0
:
19. OSCSTAT ECGON -- 1 = ECGST -- 1 =
OSCTRIM
:
$0038
7 TRIM7 1
6 TRIM6 0
5 TRIM5 0
4 TRIM4 0
3 TRIM3 0
2 TRIM2 0
1 TRIM71 0
0 TRIM0 0
:
20. OSCTRIM TRIM7-TRIM0 -- / 1 1 $80 0.2 5 OSCTRIM $80 3.2MHz 25 FLASH TRIMLOC $FFC0 TRIMLOC OSCTRIM $0038
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 27
MC68HC908QY4
TIM
MC68HC908QYx MC68HC908QTx
*
/ - - PWM TIM TIM 16 TIM
* * * *
INTERNAL BUS CLOCK TSTOP TRST
PRESCALER
PRESCALER SELECT / 1, 2, 4, 8, 16, 32, OR 64
PS2
PS1
PS0
16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL
TOF TOIE TOGGLE
INTERRUPT LOGIC
TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0
21. TIM 21.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 28 MOTOROLA
PWM
PWM : 1. TSC : a. TSTOP TIM b. TRST TIM 2. TMODH:TMODL PWM 3. TCHxH:TCHxL PWM 4. TIM x TSCx : a. MSxB:MSxA 0:1 PWM MSxB:MSxA. 1:0 PWM 7 7 b. TOVx 1 c. / ELSxB:ELSxA 1:0 ELSxB:ELSxA 1:1 PWM 7 7 5. TSC TSTOP
TIM TSC TSC
:
$0020
7 TOF 0
6 TOIE 0
5 TSTOP 1
4 TRST 0
3 0 0
2 PS2 0
1 PS1 0
0 PS0 0
:
22. TIM TSC TOF -- TOF 1 = TOIE -- 1 = TSTOP -- 1 = TRST -- 1 0 TSTOP TRST $0000
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 29
MC68HC908QY4
PS[2:0] -- 6.
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 Reserved
TCNTH:TCNTL TCNTH:TCNTL
TCNTH TCNTL TCNTH TCNTL TCNTL
:
TCNTH $0021 7 Bit 15 0 7 Bit 7 0 6 Bit 14 0 6 Bit 6 0 5 Bit 13 0 5 Bit 5 0 4 Bit 12 0 4 Bit 4 0 3 Bit 11 0 3 Bit 3 0 2 Bit 10 0 2 Bit 2 0 1 Bit 9 0 1 Bit 1 0 0 Bit 8 0 0 Bit 0 0
: :
TCNTL $0022
:
23. TCNTH:TCNTL
TMODH:TMODL TMODH:TMODL
TOF $0000 TMODH TOF TMODL
:
TMODH $0023 7 Bit15 1 7 Bit7 1 6 Bit14 1 6 Bit6 1 5 Bit13 1 5 Bit5 1 4 Bit12 1 4 Bit4 1 3 Bit11 1 3 Bit3 1 2 Bit10 1 2 Bit2 1 1 Bit9 1 1 Bit1 1 0 Bit8 1 0 Bit0 1
: :
TMODL $0024
:
24. TMODH:TMODL
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 30 MOTOROLA
TSC0, TSC1 TSC1
:
TSC0 $0025
7 CH0F 0 7 CH1F 0
6 CH0IE 0 6 CH1IE 0
5 MS0B 0 5 0 0
4 MS0A 0 4 MS1A 0
3 ELS0B 0 3 ELS1B 0
2 ELS0A 0 2 ELS1A 0
1 TOV0 0 1 TOV1 0
0 CH0MAX 0 0 CH1MAX 0
: :
TSC1 $0028
:
25. TSC0, TSC1 CHxF -- x x x CHxF 1 x x CHxF 1 CHxF x CHxF 1 = x CHxIE -- x 1 = x CPU MSxB:MSxA -- ELSxB:ELSxA -- / 7. /
MSxB X X 0 0 0 0 0 0 1 1 1 MSxA 0 1 0 0 0 1 1 1 X X X ELSxB 0 0 0 1 1 0 1 1 0 1 1 ELSxA 0 Output preset 0 1 0 1 1 0 1 1 0 1 Buffered output compare or buffered PWM Output compare or PWM Input capture Mode Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare
TOVx -- 1 = x TOVx x
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 31
MC68HC908QY4
CHxMAX -- x TOVx CHxMAX PWM 100CHxMAX CHxMAX 100
OVERFLOW PERIOD OVERFLOW OVERFLOW OVERFLOW OVERFLOW
TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
26. CHxMAX PWM
TCH1H:L TCH0H:L, TCH1H:L
MSxB:MSxA = 0:0 x TCHxH TCHxL MSxB:MSxA 0:0 x TCHxH TCHxL
:
7 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 0 Bit 8
TCH0H $0026
: :
TCH0L $0027 7 Bit 7 6 Bit 6 5 Bit 5
Indeterminate after reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 0 Bit 0
: :
TCH1H $0029 7 Bit 15 6 Bit 14 5 Bit 13
Indeterminate after reset 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 0 Bit 8
: :
TCH1L $002A 7 Bit 7 6 Bit 6 5 Bit 5
Indeterminate after reset 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 0 Bit 0
:
Indeterminate after reset
27. TCH0H:L, TCH1H:L
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 32 MOTOROLA
ADC
MC68HC908QY2 MC68HC908QT2 MC68HC908QY4 MC68HC908QT4 4 8 ADC ADC
* * * * *
INTERNAL DATA BUS
4 AD 8 AD AD ADC
ADC DATA REGISTER A/D PIN INPUTS AD[3:0] CONVERSION COMPLETE ADC VOLTAGE IN ADCVIN CHANNEL SELECT (1 OF 4 CHANNELS)
INTERRUPT LOGIC
ADC
CH[4:0]
AIEN
COCO
ADC CLOCK CLOCK GENERATOR
BUS CLOCK
ADIV[2:0]
28. ADC
16 ADC
x
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 33
MC68HC908QY4
ADC ADSCR ADSCR
:
$003C
7 COCO 0
6 AIEN 0
5 ADCO 0
4 CH4 1
3 CH3 1
2 CH2 1
1 CH1 1
0 CH0 1
:
29. ADC ADSCR COCO -- AIEN 0 COCO AD 1 ADSCR ADR AIEN 1 CPU COCO 0 1 = AIEN = 0 AIEN -- ADC 1 = ADC ADCO -- ADC 1 = ADC 0 = ADC CH[4:0] -- ADC ADC 8. ADC 8. AD
CH4 0 0 0 0 0 1 1 1 1 1 1 CH3 0 0 0 0 0 1 1 1 1 1 1 CH2 0 0 0 0 1 0 0 1 1 1 1 CH1 0 0 1 1 0 1 1 0 0 1 1 CH0 0 1 0 1 0 0 1 0 1 0 1 ADC Channel AD0 AD1 AD2 AD3 -- -- -- -- -- -- -- -- Input Select PTA0 PTA1 PTA4 PTA5 Unused(1) Reserved Unused VDDA(2) VSSA(2) ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes, as specified in the table, are used to verify the operation of the ADC converter both in production test and for user applications.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 34 MOTOROLA
ADC ADR ADR
ADC
: $003E :
7 AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 AD0
Indeterminate after reset
30. ADC ADR
ADC ADICLK ADICLK
: $003F :
7 ADIV2 0
6 ADIV1 0
5 ADIV0 0
4 0 0
3 0 0
2 0 0
1 0 0
0 0 0
31. ADC ADICLK ADIV2-ADIV0 -- ADC 9. ADC
ADIV2 0 0 0 0 1
X = don't care
ADIV1 0 0 1 1 X
ADIV0 0 1 0 1 X
ADC Clock Rate Bus clock / 1 Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16
A A 6 KBI ADC RSTIRQ A KBI IRQ PORTA PTA3 RST
PTA2
A
PTA PTA
:
$0000 7 0 6 AWUL 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 0 PTA0
:
Additional Functions: KBI5 AD3 OSC1
KBI4 AD2 OSC2 KBI3 RST KBI2 IRQ KBI1 AD1 TCH1 KBI0 AD0 TCH0
32. A PTA 32.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 35
MC68HC908QY4
PTA[5:0] -- A / PTA2 AWUL
A DDRA DDRA
:
$0004
7 0 0
6 0 0
5 DDRA5 0
4 DDRA4 0
3 DDRA3 0
2 0 0
1 DDRA1 0
0 DDRA0 0
:
33. A DDRA DDRA 33. DDRA DDRA[5:0] -- A 1 = A 0 = A
A PTAPUE PTAPUE
:
7
6
5
4
3
2
1
0
$000B OSC2EN
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE2 PTAPUE0 0 0 0 0 0 0 0
:
0
34. A PTAPUE OSC2EN -- OSC2 RC OSC2 XTAL 1 = OSC2 RC BUSCLKX4 PTAPUE[5:0] -- A 1 = DDRA 0 KBIIRQ A
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 36 MOTOROLA
B
B 8 I/O MC68HC908QY1MC68HC908QY2 MC68HC908QY4 B
B PTB PTB
:
$0001
7 PTB7
6 PTB6
5 PTB5
4 PTB4
3 PTB3
2 PTB2
1 PTB1
0 PTB0
:
35. B PTB PTB[7:0] -- B /
B DDRB DDRB
: $0005 :
7 DDRB7 0
6 DDRB6 0
5 DDRB5 0
4 DDRB4 0
3 DDRB3 0
2 DDRB2 0
1 DDRB1 0
0 DDRB0 0
36. B DDRB DDRB[7:0] -- B 1 = B 0 = B
B PTBPUE PTBPUE
7 6 5 4 3 2 1 0 : $000C PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
:
0
0
0
0
0
0
0
0
37. B PTBPUE PTBPUE 37. PTBPUE PTBPUE[7:0] -- B / B 1 = DDRB 0 B
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 37
MC68HC908QY4
KBI KBI KBI
* * * * *
6
INTERNAL BUS
VECTOR FETCH DECODER KBI0 VDD ACKK RESET D CLR Q SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST KEYF
KBIE0 TO PULLUP ENABLE
. . .
KBI5
KEYBOARD INTERRUPT FF MODEK KBIE5
IMASKK
TO PULLUP ENABLE
1. AWUGEN logic 39
AWUIREQ(1)
38.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 38 MOTOROLA
COPRS (FROM CONFIG1) AUTOWUGEN 1 = DIV 29 SHORT 0 = DIV 214 INT RC OSC EN 32KHz CLK OVERFLOW RST VDD TO PTA READ, BIT 6 D Q AWUL
E
AWUIREQ R TO KBI INTERRUPT LOGIC ( 38) 38
CLRLOGIC CLEAR (CGMXCLK) 2OSCOUT CLK RST RESET ISTOP RESET ACKK
RESET AWUIE
39.
KBSCR KBSCR
:
$001A
7 0 0
6 0 0
5 0 0
4 0 0
3 KEYF 0
2 ACKK 0
1 IMASKK 0
0 MODEK 0
:
40. KBSCR KEYF -- 1 = ACKK -- 1 ACKK 0 IMASKK -- 1 = MODEK -- 1 = 0 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 39
MC68HC908QY4
KBIER KBIER
:
$001B
7 0 0
6 AWUIE 0
5 KBIE5 0
4 KBIE4 0
3 KBIE3 0
2 KBIE2 0
1 KBIE1 0
0 KBIE0 0
:
41. KBIER KBIER KBIER 41. KBIE5-KBIE0 -- A 1 = KBIx AWUIE -- 1 = CONFIG1 COPRS COPRS = 0 -- 512ms COPRS = 1 -- 16ms

BRKSCR BRKSCR
:
$FE0B
7 BRKE 0
6 BRKA 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
0 0 0
:
42. BRKSCR 42. BRKE -- 1 = 16 0 = BRKA -- BRKA 1 0 BRKA 1 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 40 MOTOROLA
BRKH:BRKL BRKH:BRKL
BRKH BRKL
:
$FE09 7 Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 0 Bit 8 0
:
43. BRKH 43.
:
$FE0A 7 Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 0 Bit 0 0
:
44. BRKL 44.
BRKAR BRKAR
MCU BRKAR BDCOP COP
:
$FE02 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 BDCOP 0
:
45. BRKAR BRKAR BRKAR 45. BDCOP -- COP 1 = COP
BFCR BFCR
BFCR BCFE MCU
:
$FE03 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R 0 R
:
46. BFCR BFCR BFCR 46. BCFE MCU BCFE 1 1 = 0 =
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 41
MC68HC908QY4
BSR BSR
BSR
:
$FE00 7 R 6 R 5 R 4 R 3 R 2 R 1 SBSW 0 R = Reserved 0 R
:
47. BSR 47. BSR BSR
5V
Characteristic(1) VDD supply current Run, fOP = 4 MHz(3) Wait(4) Stop(5), -40C to 85C POR rearm voltage(6) POR rise time ramp rate(7) Monitor mode entry voltage Pullup resistors(8) RST, IRQ, PTA0-PTA5, PTB0-PTB7 Low-voltage inhibit reset, trip falling voltage Low-voltage inhibit reset, trip rising voltage Low-voltage inhibit reset/recover hysteresis Symbol Min -- -- -- 0 0.035 VDD + 2.5 16 3.90 4.00 -- Typ(2) 7 5 1 -- -- -- 26 4.20 4.30 100 Max 10 5.5 5 100 -- 9.1 36 4.50 4.60 -- Unit mA mA A mV V/ms V k V V mV
IDD
VPOR RPOR VDD +VHI RPU VTRIPF VTRIPR VHYS
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. All ports configured as inputs. 5. All ports configured as inputs. All ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as inputs with pullups enabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0 V.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 42 MOTOROLA
5V
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 750 Max 8 -- Unit MHz ns
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
5V
Characteristic Internal oscillator frequency Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1)
1. No more than 10% duty cycle deviation from 50%.
Symbol fINTCLK fOSCXCLK fRCCLK fOSCXCLK
Min -- 1 2 dc
Typ 12.8 -- -- --
Max -- 32 12 32
Unit MHz MHz MHz MHz
14 5 V @ 25C 12 RC FREQUENCY, fRCCLK (MHz) MCU 10 8 6 VDD 4 2 0 0 10 20 30 40 50 Resistor, REXT (k) REXT OSC1
48. RC 5V, 25C 25 C
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 43
MC68HC908QY4
3V
Characteristic(1) VDD supply current Run, fOP = 2 MHz(3) Wait, fOP = 2 MHz(4) Stop(5),-40C to 85C POR rearm voltage(6) POR rise time ramp rate
(7)
Symbol
Min -- -- -- 0 0.035 VDD + 2.5 16 2.40 2.50 --
Typ(2) 5 1 1 -- -- -- 26 2.55 2.65 60
Max 8 2.5 5 100 -- VDD + 4.0 36 2.70 2.80 --
Unit mA mA A mV V/ms V k V V mV
IDD
VPOR RPOR VDD +VHI RPU VTRIPF VTRIPR VHYS
Monitor mode entry voltage Pullup resistors RST, IRQ, PTA0-PTA5, PTB0-PTB7 Low-voltage inhibit reset, trip falling voltage Low-voltage inhibit reset, trip rising voltage Low-voltage inhibit reset/recover hysteresis
(8)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOP = 4 MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD. 5. All ports configured as inputs. All ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as inputs with pullups enabled. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. RPU1 and RPU2 are measured at VDD = 5.0 V
3V
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 1.5 Max 4 -- Unit MHz s
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 44 MOTOROLA
3V
Characteristic Internal oscillator frequency Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock reference frequency(1)
1. No more than 10% duty cycle deviation from 50%
Symbol fINTCLK fOSCXCLK fRCCLK fOSCXCLK
Min -- 1 2 dc
Typ 12.8 -- -- --
Max -- 16 12 16
Unit MHz MHz MHz MHz
14 3 V @ 25C 12
MCU
RC FREQUENCY, fRCCLK (MHz) 10 8 6 VDD 4 2 0 0 10 20 30 40 50 RESISTOR, REXT (K) REXT OSC1
49. RC 3V, 25C 25 C
14 12 10 8 IDD (mA) 6 4 2 0 0 1 2 3 4 5 fOP OR fBUS (MHz) 6 7 8 9 5.5 V 3.3 V
50. 25 C 25C 50.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 45
MC68HC908QY4
2 1.75 1.50 1.25 IDD (mA) 1 0.75 0.5 0.25 0 0 1 2 3 4 fOP OR fBUS (MHz) 5 6 7 8 5.5 V 3.3 V
51. ADC WAIT 25C 25 C
Characteristic Input voltages Resolution Absolute accuracy ADC internal clock Conversion range Power-up time Conversion time Sample time(1) Zero input reading Full-scale reading Input capacitance Input leakage
(3) (2)
Symbol VADIN BAD AAD fADIC RAD tADPU tADC tADS ZADI FADI CADI --
Min VSS 8 0.5 0.5 VSS 16 16 5 00 FE -- --
Max VDD 8 1.5 1.048 VDD
Unit V Bits LSB MHz V tADIC cycles
Comments -- -- Includes quantization tADIC = 1/fADIC, tested only at 1 MHz -- tADIC = 1/fADIC tADIC = 1/fADIC tADIC = 1/fADIC VIN = VSS VIN = VDD Not tested --
17 -- 01 FF 8 1
tADIC cycles tADIC cycles Hex Hex pF A
(3)
1. Source impedances greater than 10 k may adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 46 MOTOROLA
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time <1 K cycles <10 K cycles FLASH mass erase time FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program hv period FLASH row erase endurance(6)
(7) (8)
Symbol VRDR -- fRead(1) tErase(2) tMErase(3) tnvs tnvh tnvhl tpgs tPROG trcv
(4)
Min 1.3 1 32 k 1 4 4 10 5 100 5 30 1 -- 10 k 10 k 10
Max -- -- 8M -- -- -- -- -- -- -- 40 -- 4 -- -- --
Unit V MHz Hz ms ms us us us us us us ms Cycles Cycles Years
tHV(5) -- -- --
FLASH row program endurance FLASH data retention time
1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. If the page erase time is longer than tErase (Min), there is no erase disturb, but it reduces the endurance of the FLASH memory. 3. If the mass erase time is longer than tMErase (Min), there is no erase disturb, but it reduces the endurance of the FLASH memory. 4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 5. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG x 32) tHV max. 6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase/program cycles. 7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many erase/program cycles. 8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
MC68HC908QY4*MC68HC908QT4*MC68HC908QY2*MC68HC908QT2*MC68HC908QY1*MC68HC908QT1 MOTOROLA 47
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) Motorola, Inc. 2002

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