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HC705RC16GRS/D REV. 3.0
General Release Specification
CSIC MCU Design Center Austin, Texas
NON-DISCLOSURE
December 13, 1996
AGREEMENT
68HC705RC16
REQUIRED
General Release Specifiation REQUIRED AGREEMENT
NON-DISCLOSURE
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
General Release Specification 2
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Section 3. Central Processor Unit . . . . . . . . . . . . . . . . . 31 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . 51 Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 55 Section 8. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 9. Carrier Modulator Transmitter (CMT) . . . . . . 65 Section 10. EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 89 Section 12. Electrical Specifications . . . . . . . . . . . . . . 107 Section 13. Mechanical Specifications . . . . . . . . . . . 113 Section 14. Ordering Information . . . . . . . . . . . . . . . . 117
MC68HC705RC16 -- Rev. 3.0 MOTOROLA List of Sections General Release Specification 3
NONDISCLOSURE
AGREEMENT
REQUIRED
List of Sections REQUIRED NONDISCLOSURE
General Release Specification 4 List of Sections
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Section 2. Memory
2.1 2.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3.1 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.2 EPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.4 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Table of Contents
General Release Specification 5
NON-DISCLOSURE
1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .20 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.5 LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.7 PA0--PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.8 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 PC0-PC3 (PC4-PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
AGREEMENT
REQUIRED
Table of Contents REQUIRED Section 3. Central Processor Unit
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AGREEMENT
Section 4. Interrupts
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CPU Interrupt Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt (IRQ/Port B Pullup) . . . . . . . . . . . . . . . . . . .39 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Carrier Modulator Transmitter Interrupt (CMT) . . . . . . . . . . . . .40 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
NON-DISCLOSURE
Section 5. Resets
5.1 5.2 5.3 5.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .46
General Release Specification 6 Table of Contents
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Table of Contents
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .47 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .48 5.5.2.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 6. Low-Power Modes
6.1 6.2 6.3 6.4 6.5 6.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
7.1 7.2 7.3 7.4 7.5 7.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Section 8. Core Timer
8.1 8.2 8.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .61
MC68HC705RC16 MOTOROLA
-- Rev.
3.0 Table of Contents
General Release Specification 7
NON-DISCLOSURE
Section 7. Parallel Input/Output (I/O)
AGREEMENT
REQUIRED
Table of Contents REQUIRED
8.4 8.5 8.6 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .63 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .64 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Section 9. Carrier Modulator Transmitter (CMT)
9.1 9.2 9.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
AGREEMENT
9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . .70 9.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.5.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.5.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5.3.1 End Of Cycle (EOC) Interrupt . . . . . . . . . . . . . . . . . . . . .77 9.5.3.2 Modulator Control and Status Register . . . . . . . . . . . . . .78 9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .81
NON-DISCLOSURE
Section 10. EPROM
10.1 10.2 10.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
10.4 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.4.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.4.2 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.4.3 Mask Option Registers (MOR1 and MOR2) . . . . . . . . . . . .87
General Release Specification 8 Table of Contents
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Table of Contents
Section 11. Instruction Set
11.1 11.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .94 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .95 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .96 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .98 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Section 12. Electrical Specifications
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .109 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .110 DC Electrical Characteristics (3.3 Vdc). . . . . . . . . . . . . . . . . .111 Control Timing (5.0 Vdc and 3.3 Vdc). . . . . . . . . . . . . . . . . . .112
MC68HC705RC16 MOTOROLA
-- Rev.
3.0 Table of Contents
General Release Specification 9
NON-DISCLOSURE
AGREEMENT
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
REQUIRED
Table of Contents REQUIRED Section 13. Mechanical Specifications
13.1 13.2 13.3 13.4 13.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 28-Pin Plastic Dual In-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02). . . . . . . . . . . . . . . . . . . . . . . . . . .115
AGREEMENT
Section 14. Ordering Information
14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
NON-DISCLOSURE
General Release Specification 10 Table of Contents
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
List of Figures
Figure 1-1 1-2 1-3 1-4 1-5 2-1 2-2 3-1 3-2 4-1 4-2 5-1 5-2 5-3 6-1 6-2 7-1 7-2 8-1 8-2 8-3
Title
Page
16-KByte Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .38 IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .39 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Reset and POR Timing Diagram . . . . . . . . . . . . . . . . . . . . .45 COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .49 Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .52 Stop/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .60 Core Timer Control and Status Register (CTCSR) . . . . . . .61 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .63
MC68HC705RC16 -- Rev. 3.0 MOTOROLA List of Figures
General Release Specification 11
NON-DISCLOSURE
AGREEMENT
MC68HC705RC16 Block Diagram . . . . . . . . . . . . . . . . . . . .18 28-Pin DIP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 28-Pin SOIC Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .19 44-Pin PLCC Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
REQUIRED
List of Figures REQUIRED
Figure 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 10-3 10-4 10-5 Title Page
AGREEMENT
Carrier Modulator Transmitter Module Block Diagram . . . . .67 Carrier Generator Block Diagram . . . . . . . . . . . . . . . . . . . . .68 Carrier Generator Data Register CHR1 . . . . . . . . . . . . . . . .70 Carrier Generator Data Register CLR1 . . . . . . . . . . . . . . . .70 Carrier Generator Data Register CHR2 . . . . . . . . . . . . . . . .70 Carrier Generator Data Register CLR2 . . . . . . . . . . . . . . . .71 Modulator Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .73 CMT Operation in Time Mode . . . . . . . . . . . . . . . . . . . . . . .75 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .77 Modulator Control and Status Register (MCSR) . . . . . . . . .78 Modulator Period Data Register MDR1 . . . . . . . . . . . . . . . .81 Modulator Period Data Register MDR2 . . . . . . . . . . . . . . . .81 Modulator Period Data Register MDR3 . . . . . . . . . . . . . . . .81 Programmer Interface to Host . . . . . . . . . . . . . . . . . . . . . . .84 MC68HC705RC16 Programming Circuit . . . . . . . . . . . . . . .85 Programming Register (PROG) . . . . . . . . . . . . . . . . . . . . . .86 Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . .87 Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . .87
NON-DISCLOSURE
General Release Specification 12 List of Figures
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
List of Tables
Table 4-1 5-1 7-1 8-1 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 14-1
Title
Page
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .36 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .48 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 RTI and COP Rates at 4.096 MHz Oscillator . . . . . . . . . . . . .62 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .94 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .95 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .97 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .98 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
MC68HC705RC16 -- Rev. 3.0 MOTOROLA List of Tables
General Release Specification 13
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List of Tables REQUIRED NON-DISCLOSURE
General Release Specification 14 List of Tables
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MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MC68HC705RC16 -- Rev. 3.0 MOTOROLA General Description
General Release Specification 15
NON-DISCLOSURE
1.5 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.2 IRQ/VPP (Maskable Interrupt Request) . . . . . . . . . . . . . . . .20 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.5 LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.6 IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.7 PA0-PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.8 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 PC0-PC3 (PC4-PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
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General Description REQUIRED 1.2 Introduction
The MC68HC705RC16 is a low-cost addition to the M68HC05 Family of microcontrollers (MCUs) and is suitable for remote control applications. It contains the HC05 CPU core, including the 14-stage core timer with RTI and COP watchdog systems. On-chip peripherals include a carrier modulator transmitter. The 16-Kbyte memory map has 15,936 bytes of user EPROM, 340 bytes of boot ROM, and 352 bytes of RAM. There are 20 input/output (I/O) lines (eight having keyscan pullups/interrupts) and a low-power reset pin. The MC68HC705RC16 is available in 28-pin small outline integrated circuit (SOIC), dual in-line (DIP), or plastic leaded chip carrier (PLCC) packages. Four additional I/O lines are available for bond out in the 44-lead PLCC package.
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1.3 Features
Features of the MC68HC705RC16 are: * * * Low Cost HC05 Core 28-Pin Plastic Dual In-Line (PDIP), Small Outline Integrated Circuit (SOIC), or 44-Lead Plastic Leaded Chip Carrier (PLCC) Packages On-Chip Oscillator with Crystal/Ceramic Resonator 4-MHz Maximum Oscillator Frequency at 5 V and 3.3 V Supply Fully Static Operation 15,936 Bytes of User ROM 64 Bytes of Burn-In ROM 352 Bytes of On-Chip RAM 14-Stage Core Timer with Real-Time Interrupt (RTI) and Computer Operating Properly (COP) Watchdog Circuits
NON-DISCLOSURE
* * * * * * *
General Release Specification 16 General Description
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Description Mask Options
*
Carrier Modulator Transmitter Supporting Baseband, Pulse Length Modulator (PLM), and Frequency Shift Keying (FSK) Protocols Low-Power Reset Pin 20 Bidirectional I/O Lines (Four Additional I/O Lines Available for Bond Out in 44-Lead PLCC Package) Mask Programmable Pullups and Interrupt on Eight Port Pins (PB0-PB7) High-Current Infrared (IR) Drive Pin High-Current Port Pin (PC0) Power-Saving Stop and Wait Modes Mask Selectable Options: - COP Watchdog Timer - STOP Instruction Disable - Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger - Port B Pullups for Keyscan
* * * * * * *
The mask options on the MC68HC705RC16 are handled with 11 EPROM bits in two separate MOR registers, MOR1 and MOR2. These options are: * * * * Eight port B pullups IRQ sensitivity STOP enable/disable COP enable/disable
ROM versions of this device will have these options programmed by the factory.
NOTE:
A line over a signal name indicates an active low signal. For example, RESET is active low.
General Release Specification General Description 17
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
NON-DISCLOSURE
1.4 Mask Options
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OSC2 OSC1 VDD VSS
OSCILLATOR IRQEN /2 INTERNAL PROCESSOR CLOCK
CARRIER MODULATOR TRANSMITTER
IRO
PC0 DATA DIRECTION REGISTER PC1 PC2 PORT C PC3 PC4* PC5* PC6* PC7*
COP SYSTEM
RTI SYSTEM
CORE TIMER SYSTEM
AGREEMENT
RESET LPRST CPU CONTROL M68HC05 CPU CPU REGISTERS IRQEN 0 IRQ 00 0 0 0 0 1 1 ACCUMULATOR INDEX REGISTER STACK POINTER ALU
PA0 DATA DIRECTION REGISTER PA1 PA2 PORT A PA3 PA4 PA5 PA6 PA7 PB0 SRAM -- 352 BYTES DATA DIRECTION REGISTER PB1 KEYSCAN PULLUPS PB2 PB3 PB4 PB5 PB6 PB7
PROGRAM COUNTER 11 1H I NZ C
CONDITION CODE REGISTER
NON-DISCLOSURE
EPROM -- 15,936 BYTES
BURN-IN ROM -- 64 BYTES
* Marked pins are available only in higher pin count (>28) packages.
Figure 1-1. MC68HC705RC16 Block Diagram
General Release Specification 18 General Description
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
PORT B
General Description Signal Description
1.5 Signal Description
Pinout for the 28-pin dual in-line package (DIP) is shown in Figure 1-2. Figure 1-3 provides the pinout for the 28-pin small outline integrated circuit (SOIC) package. Figure 1-4 shows the pinout for the 44-lead plastic leaded chip carrier (PLCC). The signals are described in the following subsections.
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OSC1
VDD IRQ/VPP RESET IRO VSS LPRST PC3 PC2 PC1 PC0 PA7 PA6
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
OSC1 OSC2 VDD IRQ/VPP RESET IRO VSS LPRST PC3 PC2 PC1 PC0 PA7 PA6
Figure 1-3. 28-Pin SOIC Assignments
MC68HC705RC16 -- Rev. 3.0 MOTOROLA General Description General Release Specification 19
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Figure 1-2. 28-Pin DIP Pinout
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OSC2
REQUIRED
General Description REQUIRED
OSC1
OSC2
PB3
PB2
PB1
PB0
VDD 42
1 NC
IRQ 41
NC
44
NC PB4 PB5 PB6 PB7 NC
43
40
6
5
4
3
2
NC
7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 17
39 38 37 36 35 34 33 32 31 30 29
NC RESET IRO VSS LPRST NC PC5 PC4 PC3 PC2 NC
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PC6 PC7 PA0 PA1 NC
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
NC
NC
NOTE: NC = No Connect All no connects should be tied to an appropriate logic level (either VDD or VSS).
Figure 1-4. 44-Pin PLCC Pinout 1.5.1 VDD and VSS Power is supplied to the microcontroller's digital circuits using these two pins. VDD is the positive supply and VSS is ground. 1.5.2 IRQ/VPP (Maskable Interrupt Request) In addition to suppling the EPROM with the required programming voltage, this pin has a mask option as specified by the user that provides one of two different choices of interrupt triggering sensitivity. The options are: 1. Negative edge-sensitive triggering only 2. Both negative edge-sensitive and level-sensitive triggering.
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General Release Specification 20 General Description
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
NC
General Description Signal Description
The MCU completes the current instruction before it responds to the interrupt request. When IRQ goes low for at least one tILIH (see 12.8 Control Timing (5.0 Vdc and 3.3 Vdc)), a logic 1 is latched internally to signify that an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic 1 and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for wired-OR operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to 4.2 Introduction for more detail.
1.5.3 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic resonator, or an external signal connects to these pins to provide a system clock. The oscillator frequency is two times the internal bus rate. Figure 1-5 shows the recommended circuit when using a crystal. The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. A ceramic resonator may be used in place of the crystal in cost-sensitive applications. Figure 1-5 (a) shows the recommended circuit for using a ceramic resonator. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. An external clock should be applied to the OSC1 input with the OSC2 pin not connected (see Figure 1-5 (b)). This setup can be used if the user does not want to run the CPU with a crystal.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA General Description
General Release Specification 21
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General Description REQUIRED
MCU OSC1 OSC2 OSC1
MCU OSC2
10 M
UNCONNECTED
< EXTERNAL CLOCK 30 pF 30 pF
AGREEMENT
(a) Crystal/Ceramic Resonator Oscillator Connections
(b) External Clock Source Connections
Figure 1-5. Oscillator Connections 1.5.4 RESET This active-low pin is used to reset the MCU to a known start-up state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets.
NON-DISCLOSURE
1.5.5 LPRST The LPRST pin is an active-low pin and is used to put the MCU into low-power reset mode. In low-power reset mode the MCU is held in reset with all processor clocks halted. See Section 5. Resets.
1.5.6 IRO The IRO pin is the high-current source and sink output of the carrier modulator transmitter subsystem which is suitable for driving infrared (IR) LED biasing logic. See Section 9. Carrier Modulator Transmitter (CMT).
General Release Specification 22 General Description
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Description Signal Description
1.5.7 PA0-PA7 These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. For detailed information on I/O programming, see 2.4 Input/Output Programming.
1.5.8 PB0-PB7 These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. Each port B I/O line has a mask optionable pullup/interrupt for keyscan. For detailed information on I/O programming, see 2.4 Input/Output Programming.
1.5.9 PC0-PC3 (PC4-PC7) These eight I/O lines comprise port C. PC0 is a high-current pin. PC4-PC7 are available only in the 44-lead PLCC package. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. For detailed information on I/O programming, see 2.4 Input/Output Programming.
NOTE:
Only four bits of port C are bonded out in 28-pin packages for the MC68HC705RC16, although port C is truly an 8-bit port. Since pins PC4-PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs. Any unused inputs, I/O ports, and no connects should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC705RC16 do not require termination, termination is recommended to reduce the possibility of static damage.
NOTE:
MC68HC705RC16 -- Rev. 3.0 MOTOROLA General Description
General Release Specification 23
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REQUIRED
General Description REQUIRED NON-DISCLOSURE
General Release Specification 24 General Description
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MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 2. Memory
2.1 Contents
2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3.1 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.2 EPROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3.3 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3.4 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.4 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2 Introduction
This section describes the organization of the on-chip memory.
2.3 Memory Map
The MC68HC705RC16 has a 16-Kbyte memory map consisting of user EPROM, RAM, burn-in ROM, and input/output (I/O). Figure 2-1 shows the MC68HC705RC16 memory map in user mode.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Memory
General Release Specification 25
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REQUIRED
Memory REQUIRED
$0000 $001F $0020
I/O 32 BYTES
0000 0031 0032
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DATA DIRECTION REGISTER
$00 $01 $02 $03 $04 $05 $06 $07
RAM 160 BYTES $00B0 $00BF $00C0 $00FF $0100 $0170 $0171 $0180 STACK 64 BYTES RAM 128 BYTES 0191 0192 0255 0256 0383 0384
PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER RESERVED
CORE TIMER CONTROL & STATUS REGISTER $08 CORE TIMER COUNTER REGISTER RESERVED $09 $0A
AGREEMENT
.......
$3FAF $3FB0 $3FEF $3FF0 $3FF1
BOOT ROM MOR1 MOR2 USER VECTORS 16 BYTES USER MODE MEMORY MAP
16303 16304 16368 16370 16383
RESERVED CMT CHR1 CMT CLR1 CMT CHR2 CMT CLR2 CMT MCSR CMT MDR1 CMT MDR2 CMT MDR3 RESERVED
$3FFF
..
NON-DISCLOSURE
PROGRAMMING REGISTER RESERVED UNUSED
..
UNUSED CORE TIMER VECTOR (HIGH BYTE) CORE TIMER VECTOR (LOW BYTE) CMT VECTOR (HIGH BYTE) CMT VECTOR (LOW BYTE) IRQ/ PTB KEYSCAN PULLUPS VECTOR (HIGH BYTE) IRQ/PTB KEYSCAN PULLUPS VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
Figure 2-1. 16-KByte Memory Map
General Release Specification 26 Memory MC68HC705RC16 -- Rev. 3.0 MOTOROLA
..
$3FF5 $3FF6 $3FF7 $3FF8 $3FF9 $3FFA $3FFB $3FFC $3FFD $3FFE $3FFF
..
$1E $1F $3FF2
.......
$0F $10 $11 $12 $13 $14 $15 $16 $17 $18
USER EPROM 15920 BYTES
Memory Memory Map
Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019
Register Port A Data Register Port B Data Register Port C Data Register Reserved Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Reserved
Bit 7
6
5
4
3
2
1
Bit 0
R
R
R
R
R
R
R
R
R
R RTIF
R TOFE
R RTIE
R TOFC
R RTFC
R RT1
R RT0
Timer Control and Status Reg. CTOF Timer Counter Register Reserved Reserved Reserved Reserved Reserved Reserved R R R R R R
R R R R R R 0 0 0 0 0 MB10 MB6 SB6 R R
R R R R R R PH5 PL5 SH5 SL5 EIMSK MB9 MB5 SB5 R R
R R R R R R PH4 PL4 SH4 SL4 EXMRK MB8 MB4 SB4 R R
R R R R R R PH3 PL3 SH3 SL3 BASE SB11 MB3 SB3 R R
R R R R R R PH2 PL2 SH2 SL2 MODE SB10 MB2 SB2 R R
R R R R R R PH1 PL1 SH1 SL1 EOCIE SB9 MB1 SB1 R R
R R R R R R
IR Timer CLR1 IROLP IR Timer CHR2 IR Timer CLR2 IR Timer MCSR 0 0 EOC
PL0 SH0 SL0 MCGEN SB8 MB0 SB0 R R
IR Timer MDR1 MB11 IR Timer MDR2 IR Timer MDR3 Reserved Reserved MB7 SB7 R R
R
= Reserved
Figure 2-2. I/O Registers
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Memory
General Release Specification 27
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IR Timer CHR1 IROLN
PH0
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Memory REQUIRED
Addr. $001A $001B $001C $001D $001E $001F
Register Reserved Reserved Reserved Reserved Reserved Reserved
Bit 7 R R R R R R
6 R R R R R R
5 R R R R R R
4 R R R R R R
3 R R R R R R
2 R R R R R R
1 R R R R R R
Bit 0 R R R R R R
AGREEMENT
R
= Reserved
Figure 2-2. I/O Registers (Continued) 2.3.1 EPROM The user EPROM consists of 15,936 bytes of EPROM from $0180 to $3FAF and 14 bytes of user vectors from $3FF2 to $3FFF. The bootloader ROM and vectors are located from $3FB0 to $3FEF. Ten of the user vectors, $3FF6 thorough $3FFF, are dedicated to reset and interrupt vectors. The four remaining locations, $3FF2-$3FF5 are general-purpose user EPROM locations. The mask option registers (MOR1 and MOR2) are located at $3FF0 and $3FF1.
NON-DISCLOSURE
2.3.2 EPROM Security The MC68HC705RC16 contains special circuitry to prevent accessing the EPROM in nonuser mode. Emulation is not affected by security. Security is controlled by a security bit in the MOR1 register. The security bit is intended to be programmed while the code is being programmed.. When set, this will inhibit reading of the EPROM in all modes other than user mode.1
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users.
General Release Specification 28 Memory
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Memory Input/Output Programming
2.3.3 RAM The user RAM consists of 352 bytes of a shared stack area. The RAM starts at address $0020 and ends at address $017F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
2.3.4 Bootloader ROM Addresses $3FB0 to $3FEF are reserved ROM addresses that contain the instructions for the bootloader functions. (See Section 10. EPROM.)
2.4 Input/Output Programming
In user mode, 20 lines (28-pin PDIP or 28-pin SOIC) or 24 lines (44-lead PLCC) are arranged as three 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers. For detailed information, refer to Section 7. Parallel Input/Output (I/O).
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Memory
General Release Specification 29
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REQUIRED
Memory REQUIRED NON-DISCLOSURE
General Release Specification 30 Memory
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 3. Central Processor Unit
3.1 Contents
3.2 3.3 3.4 3.5 3.6 3.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.2 Introduction
This section describes the registers of the MC68HC705RC16 central processor unit (CPU). The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2.
7 A 70 X 13 PC 13 0 0 0 0 0 0 7 1 1 SP CCR H I N Z C CONDITION CODE REGISTER 0 STACK POINTER 0 PROGRAM COUNTER INDEX REGISTER 0 ACCUMULATOR
Figure 3-1. Programming Model
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Central Processor Unit
General Release Specification 31
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Central Processor Unit REQUIRED
7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1
0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL
STACK I N T E R R U P T
DECREASING MEMORY ADDRESSES
UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order.
AGREEMENT
Figure 3-2. Stacking Order
3.3 Accumulator
The accumulator (A) is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
7 A 0
NON-DISCLOSURE
3.4 Index Register
The index register (X) is an 8-bit register used for the indexed addressing value to create an effective address. The index register also may be used as a temporary storage area.
7 X 0
General Release Specification 32 Central Processor Unit
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Central Processor Unit Condition Code Register
3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.
CCR H I N Z C
H -- Half Carry This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. I -- Interrupt When this bit is set, timer and external interrupts are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the interrupt bit is cleared. N -- Negative When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Z -- Zero When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. C -- Carry/Borrow When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Central Processor Unit
General Release Specification 33
NON-DISCLOSURE
AGREEMENT
REQUIRED
Central Processor Unit REQUIRED 3.6 Stack Pointer
The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
13 0 0 0 0 0 1 7 1 SP 0
AGREEMENT NON-DISCLOSURE
3.7 Program Counter
The program counter (PC) is a 13-bit register that contains the address of the next byte to be fetched.
13 PC 0
NOTE:
The HC05 CPU core is capable of addressing a 64-Kbyte memory map. For this implementation, however, the addressing registers are limited to an 16-Kbyte memory map.
General Release Specification 34 Central Processor Unit
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 4. Interrupts
4.1 Contents
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 CPU Interrupt Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Interrupt (IRQ/Port B Pullup) . . . . . . . . . . . . . . . . . . .39 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Carrier Modulator Transmitter Interrupt (CMT) . . . . . . . . . . . . .40 Core Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.2 Introduction
The MCU can be interrupted four different ways: 1. Nonmaskable software interrupt instruction (SWI) 2. External asynchronous interrupt (IRQ/port B keyscan) 3. Internal carrier modulator transmitter interrupt 4. Internal core timer interrupt
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Interrupts
General Release Specification 35
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED 4.3 CPU Interrupt Processor
Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. If interrupts are not masked (I bit in the CCR is clear) and the corresponding interrupt enable bit is set, the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs, the processor completes the current instruction, stacks the current CPU register state, sets the I bit to inhibit further interrupts, and finally checks the pending hardware interrupts. If more than one interrupt is pending after the stacking operation, the interrupt with the highest vector location shown in Table 4-1 will be serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. When an interrupt is to be processed, the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $3FF6-$3FFF as defined in Table 4-1. Table 4-1. Vector Address for Interrupts and Reset
Register N/A N/A N/A MCSR Flag Name N/A N/A N/A EOC CTOF, RTIF Interrupt Reset Software Interrupt External Interrupts* End of Cycle Interrupt Real-Time Interrupt Core Timer Overflow CPU Interrupt RESET SWI IRQ CMT CORE TIMER Vector Address $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9
NON-DISCLOSURE
AGREEMENT
CTCSR
$3FF6-$3FF7
*External interrupts include IRQ and port B keyscan sources.
General Release Specification 36 Interrupts
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Interrupts Reset Interrupt Sequence
The M68HC05 CPU does not support interruptible instructions. The maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. Latency = (Longest instruction execution time + 10) x tcyc seconds An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing.
4.4 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low-level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address, which is specified by the contents of memory locations $3FFE and $3FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset.
4.5 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Interrupts
General Release Specification 37
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED
FROM RESET
Y
I BIT IN CCR SET? N IRQ/PORT B KEYSCAN EXTERNAL INTERRUPTS N INTERNAL CMT INTERRUPT N INTERNAL CORE TIMER INTERRUPT N Y Y Y EIMSK CLEAR? N Y CLEAR IRQ REQUEST LATCH.
AGREEMENT
STACK PC, X, A, CCR.
NON-DISCLOSURE
FETCH NEXT INSTRUCTION.
SET I BIT IN CC REGISTER.
SWI INSTRUCTION ? N Y RTI INSTRUCTION ? N RESTORE REGISTERS FROM STACK: CCR, A, X, PC. EXECUTE INSTRUCTION.
Y
LOAD PC FROM APPROPRIATE VECTOR.
Figure 4-1. Interrupt Processing Flowchart
General Release Specification 38 Interrupts MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Interrupts Hardware Interrupts
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. The three types of hardware interrupts are explained in the following sections.
4.7 External Interrupt (IRQ/Port B Pullup)
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply to the level on the IRQ pin itself and to the output of the logic OR function with the port B IRQ interrupts. The states of the individual port B pins can be checked by reading the appropriate port B pins as inputs.
The IRQ pin is one source of an external interrupt. All port B pins (PB0-PB7) act as other external interrupt sources if the pullup feature is enabled as specified by the user.
EIMSK IRQ PIN PORT B KEYSCAN INTERRUPT IRQ VECTOR FETCH
VDD
IRQ LATCH R
TO IRQ PROCESSING IN CPU
RST LEVEL (MASK OPTION)
Figure 4-2. IRQ Function Block Diagram
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Interrupts
General Release Specification 39
NON-DISCLOSURE
TO BIH & BIL INSTRUCTION SENSING
AGREEMENT
REQUIRED
Interrupts REQUIRED
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Falling edge on the IRQ pin 2. Falling edge on any port B pin with pullup enabled When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to these cases: 1. Low level on the IRQ pin
AGREEMENT
2. Falling edge on the IRQ pin 3. Falling edge or low level on any port B pin with pullup enabled External interrupts also can be masked by setting the EIMSK bit in the MSCR register of the IR remote timer. See 9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) for details.
4.8 External Interrupt Timing
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of the IRQ source. It is then synchronized internally and serviced as specified by the contents of $3FFA and $3FFB. Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger is available via the MOR register for the IRQ pin.
NON-DISCLOSURE
4.9 Carrier Modulator Transmitter Interrupt (CMT)
A CMT interrupt occurs when the end of cycle flag (EOC) and the end of cycle interrupt enable (EOCIE) bits are set in the modulator control and status register (MCSR). This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9.
General Release Specification 40 Interrupts
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Interrupts Core Timer Interrupt
4.10 Core Timer Interrupt
This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. Either of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Interrupts
General Release Specification 41
NON-DISCLOSURE
AGREEMENT
REQUIRED
Interrupts REQUIRED NON-DISCLOSURE
General Release Specification 42 Interrupts
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 5. Resets
5.1 Contents
5.2 5.3 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Low-Power External Reset (LPRST) . . . . . . . . . . . . . . . . . . . .46
5.5 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.5.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.5.2 Computer Operating Properly Reset (COPR) . . . . . . . . . . .47 5.5.2.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.2 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.3 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.5.2.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . .48 5.5.2.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 5.5.3 Illegal Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.2 Introduction
The MCU can be reset from five sources: two external inputs and three internal restart conditions. The RESET and LPRST pins are inputs as shown in Figure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Resets
General Release Specification 43
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED 5.3 External Reset (RESET)
The RESET pin is one of the two external sources of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU.
AGREEMENT
NOTE:
Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified.
IRQ D LATCH RESET R
TO IRQ LOGIC MODE SELECT
NON-DISCLOSURE
CLOCKED
OSC DATA ADDRESS LPRST
COP WATCHDOG (COPR) CPU S D LATCH PH2 TO OTHER PERIPHERALS
VDD
POWER-ON RESET (POR) ILLEGAL ADDRESS (ILLADDR)
RST
ADDRESS
Figure 5-1. Reset Block Diagram
General Release Specification 44 Resets
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
MC68HC705RC16 -- Rev. 3.0 General Release Specification
MOTOROLA Resets 45
VDD 0V > VPOR 4 OSC12 4064 tCYC tCYC INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1
3FFE
3FFF
NEW PC NEW PC
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC NEW PC
NEW PCH
NEW PCL
OP CODE tRL
PCH
PCL
OP CODE
RESET
3
NOTES: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. 4. VDD must fall to a level lower than VPOR to be recognized as a power-on reset. 5. The LPRST pin resets the CPU like RESET. However, 4064 POR cycles are first, before the reset vector address appears on the internal address bus. (See 5.4 Low-Power External Reset (LPRST).)
Resets External Reset (RESET)
Figure 5-2. Reset and POR Timing Diagram
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED 5.4 Low-Power External Reset (LPRST)
The LPRST pin is one of the two external sources of a reset. This external reset occurs whenever the LPRST pin is pulled below the lower threshold and remains in reset until the LPRST pin rises. This active low input will, in addition to generating the RST signal and resetting the CPU and peripherals, halt all internal processor clocks. The MCU will remain in this low-power reset condition as long as a logic 0 remains on LPRST. When a logic 1 is applied to LPRST, processor clocks will be re-enabled with the MCU remaining in reset until the 4064 internal processor clock cycle (tcyc) oscillator stabilization delay is completed. If any other reset function is active at the end of this 4064-cycle delay, the RST signal remains in the reset condition until the other reset condition(s) end.
AGREEMENT
5.5 Internal Resets
The three internally generated resets are the initial power-on reset function, the COP watchdog timer reset, and the illegal address detector. Termination of the external reset input, external LPRST input, or the internal COP watchdog timer are the only reset sources that can alter the operating mode of the MCU. The other internal resets do not have any effect on the mode of operation when their reset state ends.
NON-DISCLOSURE
5.5.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles (PH2) after the oscillator becomes active. The POR generates the RST signal that resets the CPU. If any other reset function is active at the end of this 4064-cycle delay, the RST signal remains in the reset condition until the other reset condition(s) ends.
General Release Specification 46 Resets
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Resets Internal Resets
5.5.2 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. The COP reset function is enabled or disabled by the mask option registers (MOR). 5.5.2.1 Resetting the COP Writing a zero to the COPF bit prevents a COP reset. This action resets the counter and begins the time-out period again. The COPF bit is bit 0 of address $3FF0. A read of address $3FF0 returns user data programmed at that location. 5.5.2.2 COP During Wait Mode The COP continues to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset. 5.5.2.3 COP During Stop Mode When the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. When stop is executed, the COP counter will hold its current state. If a reset is used to exit stop mode, the COP counter is reset and held until 4064 POR cycles are completed. At this time, counting will begin. If an external IRQ is used to exit stop mode, the COP counter does not wait for the completion of the 4064 POR cycles but does count these cycles. It is, therefore, recommended that the COP is fed before executing the STOP instruction.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Resets
General Release Specification 47
NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets REQUIRED
5.5.2.4 COP Watchdog Timer Considerations The COP watchdog timer is active in all modes of operation if enabled by a mask option. If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentionally or inadvertently due to the CPU being disturbed) causes the oscillator to halt and prevents the COP watchdog timer from timing out. If the COP watchdog timer is selected by a mask option, the COP resets the MCU when it times out. Therefore, it is recommended that the COP watchdog be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP time-out period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized in Table 5-1. Table 5-1. COP Watchdog Timer Recommendations
IF the Following Conditions Exist: Wait Time Wait Time Less than COP Time-Out Wait Time More than COP Time-Out THEN the COP Watchdog Timer Should Be: Enable or Disable COP by MOR Disable COP by MOR Disable COP by MOR
NON-DISCLOSURE
AGREEMENT
Any Length Wait Time
General Release Specification 48 Resets
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Resets Internal Resets
5.5.2.5 COP Register The COP register is shared with the LSB of an unimplemented user interrupt vector as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a zero to the COPR bit in this location clears the COP watchdog timer.
Address: $0FF) BIt 7 Read: Write: Reset: -- -- -- -- -- -- -- X 6 X 5 X 4 X 3 X 2 X 1 X Bit 0
COPR 0
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
5.5.3 Illegal Address An illegal address reset is generated when the CPU attempts to fetch an instruction from I/O address space ($0000 to $001F).
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Resets
General Release Specification 49
NON-DISCLOSURE
AGREEMENT
X
REQUIRED
Resets REQUIRED NON-DISCLOSURE
General Release Specification 50 Resets
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 6. Low-Power Modes
6.1 Contents
6.2 6.3 6.4 6.5 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Low-Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.2 Introduction
This section describes the low-power modes.
6.3 Stop Mode
The STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation. During stop mode, the CTCSR ($08) bits are altered to remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit in the CCR is cleared to enable external interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged.
NOTE:
The EIMSK bit is not cleared automatically by the execution of a STOP instruction. Care should be taken to clear this bit before entering stop mode.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Low-Power Modes
General Release Specification 51
NON-DISCLOSURE
AGREEMENT
REQUIRED
Low-Power Modes REQUIRED
OSC11 tRL RESET
IRQ2
tLIH
IRQ3
tILCH
4064 tCYC
AGREEMENT
INTERNAL CLOCK INTERNAL ADDRESS BUS
3FFE
3FFE
3FFE
3FFE
3FFF
NOTES: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option
RESET OR INTERRUPT VECTOR FETCH
Figure 6-1. Stop Recovery Timing Diagram
NON-DISCLOSURE
6.4 Stop Recovery
The processor can be brought out of stop mode only by an external interrupt, LPRST, or RESET. Refer to Figure 6-1.
NOTE:
If an external interrupt is pending when stop mode is entered, then stop mode will be exited immediately.
6.5 Wait Mode
The WAIT instruction places the MCU in a low power-consumption mode, but wait mode consumes more power than stop mode. All CPU action is suspended, but the core timer, the oscillator, and any enabled module remain active. Any interrupt or reset will cause the MCU to exit wait mode. The user must shut off subsystems to reduce power
General Release Specification 52 Low-Power Modes
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Low-Power Modes Low-Power Reset
consumption. Wait current specifications assume CPU operation only and do not include current consumption by any other subsystems. During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous states. The timer may be enabled to allow a periodic exit from the wait mode.
6.6 Low-Power Reset
Low-power reset mode is entered when a logic 0 is detected on the LPRST pin. When in this mode (as long as LPRST is held low), the MCU is held in reset and all internal clocks are halted. Applying a logic 1 to LPRST will cause the part to exit low-power reset mode and begin counting out the 4064-cycle oscillator stabilization period. Once this time has elapsed, the MCU will begin operation from the reset vectors ($3FFE-$3FFF).
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Low-Power Modes
General Release Specification 53
NON-DISCLOSURE
AGREEMENT
REQUIRED
Low-Power Modes REQUIRED
STOP
WAIT
STOP OSCILLATOR AND ALL CLOCKS. CLEAR I BIT.
OSCILLATOR ACTIVE. IR TIMER CLOCK ACTIVE. CORE TIMER CLOCK ACTIVE. PROCESSOR CLOCKS STOPPED.
AGREEMENT
N
RESET OR LPRST Y
RESET OR LPRST Y
N
N
EXTERNAL INTERRUPT (PTB KEYSCAN PULLUPS) (IRQ) Y
EXTERNAL INTERRUPT N (PTB KEYSCAN PULLUPS) (IRQ) Y IR TIMER INTERNAL Y INTERRUPT Y
N
TURN ON OSCILLATOR. WAIT FOR TIME DELAY TO STABILIZE.
RESTART PROCESSOR CLOCK.
CORE TIMER INTERNAL INTERRUPT Y
N
NON-DISCLOSURE
1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE
Figure 6-2. Stop/Wait Flowchart
General Release Specification 54 Low-Power Modes
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 7. Parallel Input/Output (I/O)
7.1 Contents
7.2 7.3 7.4 7.5 7.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.2 Introduction
In user mode, 20 lines (28-pin PDIP or 28-pin SOIC) or 24 lines (44-lead PLCC) are arranged as three 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers.
NOTE:
To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Parallel Input/Output (I/O)
General Release Specification 55
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output (I/O) REQUIRED 7.4 Port B
Port B is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The address of the port B data register is $0001 and the data direction register (DDR) is at address $0005. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Each of the port B pins has a mask programmable pullup device that can be enabled. When the pullup device is enabled, this pin will also become an interrupt pin. The edge or edge and level sensitivity of the IRQ pin will also pertain to the enabled port B pins. Care needs to be taken when using port B pins that have the pullup enabled. Before switching from an output to an input, the data should be preconditioned to a logic one or the I bit should be set in the condition code register to prevent an interrupt from occurring. The EIMSK bit in the CMT MCSR register can be used to mask port B keyscan and external interrupts (IRQ).
AGREEMENT
NOTE:
When a port B pin is configured as an output, it's corresponding keyscan interrupt is disabled, regardless of it's MOR register setting.
VDD VDD DISABLED MASK OPTION (PB7PU) DDR BIT ENABLED PB7 NORMAL PORT CIRCUITRY AS SHOWN IN FIGURE 7-2 IRQEN IRQ TO INTERRUPT LOGIC
NON-DISCLOSURE
FROM ALL OTHER PORT B PINS
Figure 7-1. Port B Pullup Option
7.5 Port C
Port C is an 8-bit bidirectional port (PC0-PC7) which does not share any of its pins with other subsystems. The port C data register is at $0003 and the data direction register (DDR) is at $0006. Reset does not affect the data register, but clears the data direction register, thereby returning
General Release Specification 56 Parallel Input/Output (I/O) MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Parallel Input/Output (I/O) Input/Output Programming
the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Port C pins PC4-PC7 are available only with the 44-lead PLCC package.
NOTE:
Only four bits of port C are bonded out in 28-pin packages for the MC68HC705RC16, although port C is truly an 8-bit port. Since pins PC4-PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs.
7.6 Input/Output Programming
Port pins may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. Table 7-1. I/O Pin Functions
Access Write Write Read Read DDR 0 1 0 1 I/O Pin Functions The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Parallel Input/Output (I/O)
General Release Specification 57
NON-DISCLOSURE
AGREEMENT
REQUIRED
Parallel Input/Output (I/O) REQUIRED
DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS
LATCHED OUTPUT DATA BIT
OUTPUT
I/O PIN
INPUT REG BIT INPUT I/O
AGREEMENT
Figure 7-2. I/O Circuitry
NON-DISCLOSURE
General Release Specification 58 Parallel Input/Output (I/O)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 8. Core Timer
8.1 Contents
8.1 8.2 8.3 8.4 8.5 8.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Core Timer Control and Status Register. . . . . . . . . . . . . . . . . .61 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .63 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .64 Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
8.2 Introduction
The core timer for this device is a 14-stage multifunctional ripple counter. Features include timer overflow, power-on reset (POR), real-time interrupt (RTI), and COP watchdog timer. As seen in Figure 8-1, the internal peripheral clock is divided by four, and then drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the core timer counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock (E)/1024. This point is then followed by three more stages, with the resulting clock (E/4096) driving the real-time interrupt circuit (RTI). The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location $08.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Core Timer
General Release Specification 59
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED
INTERNAL BUS COP CLEAR
8
8 CTCR $09 CORE TIMER COUNTER REGISTER (CTCR)
INTERNAL PERIPHERAL CLOCK (E) E / 22
E / 210
/4
E / 212
POR
AGREEMENT
5-BIT COUNTER
E / 215 E / 214 E / 213 E / 212
TCBP
RTI SELECT CIRCUIT
OVERFLOW DETECT CIRCUIT RTIOUT CTCSR CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0 TIMER CONTROL & $08 STATUS REGISTER
NON-DISCLOSURE
INTERRUPT CIRCUIT
COP WATCHDOG TIMER (/8) 23
TO INTERRUPT LOGIC
TO RESET LOGIC
Figure 8-1. Core Timer Block Diagram
General Release Specification 60 Core Timer
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Core Timer Core Timer Control and Status Register
8.3 Core Timer Control and Status Register
The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTCSR when coming out of reset.
Address: Read: Write: Reset: 0 0 0 0 $08 CTOF RTIF TOFE RTIE TOFC 0 RTFC 0 1 1 0 0 RT1 RT0
= Unimplemented
Figure 8-2. Core Timer Control and Status Register (CTCSR) CTOF -- Core Timer Overflow CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. Clearing the CTOF is done by writing a one to TOFC. Writing to this bit has no effect. Reset clears CTOF. RTIF -- Real-Time Interrupt Flag The real-time interrupt circuit consists of a 3-stage divider and a one-of-four selector. The clock frequency that drives the RTI circuit is E/212 (or E / 4096 with three additional divider stages, giving a maximum interrupt period of 16 milliseconds at a bus rate of 2.024 MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. Clearing the RTIF is done by writing a one to RTFC. Writing has no effect on this bit. Reset clears RTIF. TOFE -- Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears this bit. RTIE -- Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Core Timer
General Release Specification 61
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED
TOFC -- Timer Overflow Flag Clear When a one is written to this bit, CTOF is cleared. Writing a zero has no effect on the CTOF bit. This bit always reads as zero. RTFC -- Real-Time Interrupt Flag Clear When a one is written to this bit, RTIF is cleared. Writing a zero has no effect on the RTIF bit. This bit always reads as zero. RT1 and RT0 -- Real-Time Interrupt Rate Select
AGREEMENT
These two bits select one of four taps from the real-time interrupt circuit. Refer to Table 8-1. Reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. To avoid problems, the COP should be cleared before changing RTI taps. Table 8-1. RTI and COP Rates at 4.096 MHz Oscillator
RTI RATE 2.048-MHz Bus
2 ms 4 ms 8 ms 16 ms
RT1:RT0
00 01 10 11
MINIMUM COP RATES 2.048-MHz Bus (215-212)/E (216-213)/E (217-214)/E (218-215)/E
14 ms 28 ms 56 ms 112 ms
NON-DISCLOSURE
212 / E 213 / E 214 / E 215 / E
General Release Specification 62 Core Timer
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Core Timer Core Timer Counter Register
8.4 Core Timer Counter Register
The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions, including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter.
Address: Read: Write: Reset: 0 0 0 0 0 0 1 1 $09 D7 D6 D5 D4 D3 D2 D1 D0
= Unimplemented
Figure 8-3. Core Timer Counter Register (CTCR) The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. When RESET is asserted any time during operation (other than POR and low-power reset), the counter chain is cleared.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Core Timer
General Release Specification 63
NON-DISCLOSURE
AGREEMENT
REQUIRED
Core Timer REQUIRED 8.5 Computer Operating Properly (COP) Reset
The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout or clearing the COP is accomplished by writing a zero to bit 0 of address $3FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared. If the COP watchdog timer is allowed to time out, an internal reset is generated to reset the MCU. The COP remains enabled after execution of the WAIT instruction and all associated operations apply. If the STOP instruction is disabled, execution of STOP instruction causes the CPU to execute a WAIT instruction. In addition, the COP is prohibited from being held in reset. This prevents a device lock-up condition. This COP's objective is to make it impossible for this device to become stuck or locked-up and to be sure the COP is able to rescue the part from any situation where it might entrap itself in abnormal or unintended behavior. This function is a mask option.
NON-DISCLOSURE
AGREEMENT
8.6 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. The COP is always enabled while in user mode.
General Release Specification 64 Core Timer
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 9. Carrier Modulator Transmitter (CMT)
9.1 Contents
9.2 9.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
9.4 Carrier Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 9.4.1 Time Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . .70 9.5 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 9.5.1 Time Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 9.5.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 9.5.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . .76 9.5.3.1 End Of Cycle (EOC) Interrupt . . . . . . . . . . . . . . . . . . . . .77 9.5.3.2 Modulator Control and Status Register . . . . . . . . . . . . . .78 9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . .81
9.2 Introduction
The carrier modulator transmitter (CMT) module provides a means to generate the protocol timing and carrier signals for a wide variety of encoding schemes. It incorporates hardware to off-load the critical and/or lengthy timing requirements associated with code generation from the CPU, releasing much of its bandwidth to handle other tasks such as code data generation, data decompression, or keyboard scanning. The CMT does not include dedicated hardware configurations for specific protocols, but is intended to be sufficiently programmable in its function to handle the timing requirements of most protocols with minimal CPU intervention. When disabled, certain CMT registers can be
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 65
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
used to change the state of the infrared out pin (IRO) directly. This feature allows for the generation of future protocols not readily producible by the current architecture.
9.3 Overview
The module consists of carrier generator, modulator, and transmitter output blocks. The block diagram is shown in Figure 9-1. The carrier generator has a resolution of 500 ns with a 2-MHz oscillator. The user may independently define the high and low times of the carrier signal to determine both period and duty cycle. The carrier generator can generate signals with periods between 1 s (1 MHz) and 64 s (15.6 kHz) in steps of 500 ns. The possible duty cycle options will depend upon the number of counts required to complete the carrier period. For example, a 400-kHz signal has a period of 2.5 s and will therefore require 5 x 500 ns counts to generate. These counts may be split between high and low times so the duty cycles available will be 20% (one high, four low), 40% (two high, three low), 60% (three high, two low) and 80% (four high, one low). For lower frequency signals with larger periods, higher resolution (as a percentage of the total period) duty cycles are possible. The carrier generator may select between two sets of high and low times. When operating in normal mode (subsequently referred to as time mode), just one set will be used. When operating in FSK (frequency shift key) mode, the generator will toggle between the two sets when instructed to do so by the modulator, allowing the user to dynamically switch between two carrier frequencies without CPU intervention. When the BASE bit in the modulator control and status register (MCSR) is set, the carrier output to the modulator is held high continuously to allow for the generation of baseband protocols. See 9.4 Carrier Generator.
NON-DISCLOSURE
AGREEMENT
General Release Specification 66 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Overview
PRIMARY/SECONDARY SELECT MODE BASE
fOSC
.
CARRIER GENERATOR
CARRIER OUT
MODULATOR OUT MODULATOR
TRANSMITTER OUTPUT
IRO PIN
EOC INTERRUPT ENABLE
EOC FLAG
MODULATOR/ CARRIER ENABLE
fOSC / 2
CPU INTERFACE
DB
AB
EOC INTERRUPT
Figure 9-1. Carrier Modulator Transmitter Module Block Diagram The modulator provides a simple method to control protocol timing. The modulator has a resolution of 4 s with a 2-MHz oscillator. It can count system clocks to provide real-time control or it can count carrier clocks for self-clocked protocols. It can either gate the carrier onto the modulator output (TIME), control the logic level of the modulator output (baseband) or directly route the carrier to the modulator output while providing a signal to switch the carrier generator between high/low time register buffers (FSK). See 9.5 Modulator. The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated on to the IRO pin when the modulator/carrier generator is enabled. Otherwise, the IRO pin is controlled by the state of the IRO latch, which is directly accessible to the CPU by means of bit 7 of the carrier generator data registers CHR1 and CLR1. The IRO latch can be written to on either edge of the internal bus clock (fosc/2), allowing for IR waveforms which have a resolution of twice the bus clock frequency (fosc). See 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2).
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT) General Release Specification 67
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED 9.4 Carrier Generator
The carrier signal is generated by counting a predetermined number of input clocks (500 ns for a 2-MHz oscillator) for both the carrier high time and the carrier low time. The period is determined by the total number of clocks counted. The duty cycle is determined by the ratio of high time clocks to total clocks counted. The high and low time values are user programmable and are held in two registers. An alternate set of high/low count values is held in another set of registers to allow the generation of dual frequency FSK (frequency shift keying) protocols without CPU intervention. The MCGEN bit in the MCSR must be set and the BASE bit in the MCSR must be cleared to enable carrier generator clocks. The block diagram is shown in Figure 9-2.
AGREEMENT
SECONDARY HIGH COUNT REGISTER PRIMARY HIGH COUNT REGISTER
COUNT REGISTER SELECT CONTROL
=? fOSC CLOCK AND OUTPUT CONTROL
MODE
NON-DISCLOSURE
BASE MODULATOR/ CARRIER GENERATOR ENABLE
CLK CLR
6-BIT UP COUNTER
PRIMARY/ SECONDARY SELECT
CARRIER OUT
=?
SECONDARY LOW COUNT REGISTER PRIMARY LOW COUNT REGISTER
Figure 9-2. Carrier Generator Block Diagram
General Release Specification 68 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Carrier Generator
9.4.1 Time Counter The high/low time counter is a 6-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register. When this value is reached, the counter is reset and the compare is redirected to the other count value register. Assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low. The counter will continue to increment and when reaching the value stored in the selected low count value register, it will be cleared and will cause the carrier output to be driven high. The cycle repeats, automatically generating a periodic signal which is directed to the modulator. The lowest frequency (maximum period) and highest frequency (minimum period) which can be generated are defined below. fmin = fosc / (2 x (26 - 1)) Hz fmax = fosc / (2 x 1) Hz In the general case, the carrier generator output frequency is: fout = fosc / (Highcount + Lowcount) Hz Where: 0 < Highcount < 64 and 0 < Lowcount < 64
NOTE:
These equations assume the DIV2 bit (bit 6) of the MCSR is clear. When the DIV2 bit is set, the carrier generator frequency will be half of what is shown in these equations.
The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period.
Highcount Duty Cycle = --------------------------------------------------------------Highcount + Lowcount
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 69
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) The carrier generator contains two, 7-bit data registers: primary high time (CHR1), primary low time (CLR1); and two, 6-bit data registers: secondary high time (CHR2) and secondary low time (CLR2). Bit 7 of CHR1 and CHR2 is used to read and write the IRO latch.
Address: $0010 Bit 7 6 0 0 5 PH5 U 4 PH4 U 3 PH3 U 2 PH2 U 1 PH1 U Bit 0 PH0 U
AGREEMENT
Read: IROLN Write: Reset: 0 U = Unaffected
Figure 9-3. Carrier Generator Data Register CHR1
Address:
$0011 Bit 7 6 0 0 5 PL5 U 4 PL4 U 3 PL3 U 2 PL2 U 1 PL1 U Bit 0 PL0 U
Read:
NON-DISCLOSURE
IROLP Write: Reset: 0 U = Unaffected
Figure 9-4. Carrier Generator Data Register CLR1
Address:
$0012 Bit 7 6 0 0 5 SH5 U 4 SH4 U 3 SH3 U 2 SH2 U 1 SH1 U Bit 0 SH0 U
Read: 0 Write: Reset: 0 U = Unaffected
Figure 9-5. Carrier Generator Data Register CHR2
General Release Specification 70 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Carrier Generator
Address:
$0013 Bit 7 6 0 0 5 SL5 U 4 SL4 U 3 SL3 U 2 SL2 U 1 SL1 U Bit 0 SL0 U
Read: 0 Write: Reset: 0 U = Unaffected
PH0-PH5 and PL0-PL5 -- Primary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is always selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control of the modulator. The primary carrier high and low time values are undefined out of reset. These bits must be written to non-zero values before the carrier generator is enabled to avoid spurious results.
NOTE:
Writing to CHR1 to update PH0-PH5 or to CLR1 to update PL0-PL5 will also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear, the IRO latch value appears on the IRO output pin. Care should be taken that bit 7 of the data to be written to CHR1 or CHL1 should contain the desired state of the IRO latch.
SH0-SH5 and SL0-SL5 -- Secondary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is never selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 71
NON-DISCLOSURE
AGREEMENT
Figure 9-6. Carrier Generator Data Register CLR2
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
of the modulator. The secondary carrier high and low time values are undefined out of reset. These bits must be written to non-zero values before the carrier generator is enabled when operating in FSK mode. IROLN and IROLP -- IRO Latch Control Reading IROLN or IROLP reads the state of the IRO latch. Writing IROLN updates the IRO latch with the data being written on the negative edge of the internal processor clock (fosc/2). Writing IROLP updates the IRO latch on the positive edge of the internal processor clock; for example, one fosc period later. The IRO latch is clear out of reset.
AGREEMENT
NOTE:
Writing to CHR1 to update IROLN or to CLR1 to update IROLP will also update the primary carrier high and low data values. Care should be taken that bits 5-0 of the data to be written to CHR1 or CHL1 should contain the desired values for the primary carrier high or low data.
9.5 Modulator
The modulator consists of a 12-bit down counter with underflow detection which is loaded from the modulation mark period from the mark buffer register, MBUFF. When this counter underflows, the modulator gate is closed and a 12-bit comparator is enabled which continually compares the logical complement of the contents of the (still) decrementing counter with the contents of the modulation space period register, SREG. When a match is obtained, the modulator control gate is opened again. Should SREG = 0, the match will be immediate and no space period will be generated (for instance, for FSK protocols which require successive bursts of different frequencies). When the match occurs, the counter is reloaded with the contents of MBUFF, SREG is reloaded with the contents of its buffer, SBUFF, and the cycle repeats. The MCGEN bit in the MCSR must be set to enable the modulator timer. The 12-bit MBUFF and SBUFF registers are accessed through three 8-bit modulator period registers, MDR1, MDR2, and MDR3.
NON-DISCLOSURE
General Release Specification 72 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Modulator
The modulator can operate in two modes, time or FSK. In time mode the modulator counts clocks derived from the system oscillator and modulates a single-carrier frequency or no carrier (baseband). In FSK mode, the modulator counts carrier periods and instructs the carrier generator to alternate between two carrier frequencies whenever a modulation period (mark + space counts) expires.
0
MBUFF 8 CLOCK CONTROL 13-BIT DOWN COUNTER * COUNTER 12 LOAD MBUFF/SBUFF . MODULATOR GATE MODULATOR OUT . CARRIER OUT fOSC
=?
12 SREG *
SYSTEM CONTROL PRIMARY/SECONDARY SELECT EXTENDED SPACE EOC FLAG SET
SBUFF 12 BITS MODULATOR CONTROL/STATUS REGISTER
EOC FLAG EOC INTERRUPT ENABLE MODE BASE
* DENOTES HIDDEN REGISTER
DIV2
Figure 9-7. Modulator Block Diagram
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 73
NON-DISCLOSURE
MODULATOR/ CARRIER GENERATOR. ENABLE
AGREEMENT
12 BITS
MS BIT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
9.5.1 Time Mode When the modulator operates in time mode, the modulation mark and space periods consist of zero or an integer number of fosc / 8 clocks (= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 s and a maximum mark and space periods of about 16 ms (each). However, to prevent carrier glitches which could affect carrier spectral purity, the modulator control gate and carrier clock are synchronized. The carrier signal is activated when the modulator gate opens. The modulator gate can only close when the carrier signal is low (the output logic level during space periods is low). If the carrier generator is in baseband mode (BASE bit in MCSR is high), the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the duration of a space period. See Figure 9-8. The mark and space time equations are:
( MBUFF + 1 ) x 8 t mark = --------------------------------------------- sec s f osc SBUFF x 8 t space = ----------------------------- sec s f osc
NON-DISCLOSURE
AGREEMENT
Setting the DIV2 bit in the MCSR will double mark and space times.
General Release Specification 74 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Modulator
fOSC / 8
CARRIER FREQUENCY
MODULATOR GATE
MARK
SPACE
MARK
SPACE
MARK
TIME MODE OUTPUT
BASEBAND OUTPUT
Figure 9-8. CMT Operation in Time Mode
9.5.2 FSK Mode When the modulator operates in FSK mode, the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero). When the mark period expires, the space period is transparently started (as in time mode); however, in FSK mode the carrier switches between data registers in preparation for the next mark period. The carrier generator toggles between primary and secondary data register values whenever the modulator mark period expires. The space period provides an interpulse gap (no carrier), but if SBUFF = 0, then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches (zero space). Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode can automatically generate a phase-coherent, dual-frequency FSK signal with programmable burst and interburst gaps.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 75
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
The mark and space time equations for FSK mode are: MBUFF + 1 t mark = ------------------------------- sec s fcg SBUFF t space = -------------------- sec s f cg Where fcg is the frequency output from the carrier generator, setting the DIV2 bit in the MCSR will double mark and space times.
AGREEMENT
9.5.3 Extended Space Operation In either time or FSK mode, the space period can be made longer than the maximum possible value of SBUFF. Setting the EXSPC bit in the MCSR will force the modulator to treat the next modulation period (beginning with the next load of MBUFF/SBUFF) as a space period equal in length to the mark and space counts combined. Subsequent modulation periods will consist entirely of these extended space periods with no mark periods. Clearing EXSPC will return the modulator to standard operation at the beginning of the next modulation period. To calculate the length of an extended space in time mode, use the equation:
NON-DISCLOSURE
texspace =
((SBUFF1)+(MBUFF2+1+SBUFF2) +... (MBUFFn+1+SBUFFn)) x 8
fosc
secs
Where: the subscripts 1, 2, ... n refer to the modulation periods that elapsed while the EXSPC bit was set.
General Release Specification 76 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Modulator
Similarly, to calculate the length of an extended space in FSK mode, use the equation:
texspace =
((SBUFF1)+(MBUFF2+1+SBUFF2)+... (MBUFFn+1+SBUFFn)) fcg
secs
Where: fcg is the frequency output from the carrier generator. For an example of extended space operation, see Figure 9-9.
SET EXSPC
CLEAR EXSPC
Figure 9-9. Extended Space Operation 9.5.3.1 End Of Cycle (EOC) Interrupt At the end of each cycle (when the counter is reloaded from MBUFF), the end of cycle (EOC) flag is set. If the interrupt enable bit was previously set, an interrupt will also be issued to the CPU. The EOC interrupt provides a means for the user to reload new mark/space values into the MBUFF and SBUFF registers. As the EOC interrupt is coincident with reloading the counter, MBUFF does not require additional buffering and may be updated with a new value for the next period from within the EOC interrupt service routine (ISR). To allow both mark and space period values to be updated from within the same ISR, SREG is buffered by SBUFF. The contents written to SBUFF are transferred to the active register SREG at the end of every cycle regardless of the state of the EOC flag. The EOC flag is cleared by a read of the modulator control and status register (MCSR) followed by an access of MDR2 or MDR3. The EOC flag must be cleared within the ISR to prevent another interrupt being generated after exiting the ISR. If the EOC interrupt is not being used (IE = 0), the EOC flag need not be cleared.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 77
NON-DISCLOSURE
AGREEMENT
NOTE:
The EXSPC feature can be used to emulate a zero mark event.
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
9.5.3.2 Modulator Control and Status Register The modulator control and status register (MCSR) contains the modulator and carrier generator enable (MCGEN), interrupt enable (IE), mode select (MODE), baseband enable (BASE), extended space (EXSPC), and external interrupt mask (EIMSK) control bits, divide-by-two prescaler (DIV2) bit, and the end of cycle (EOC) status bit.
Address: $14 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 EOC DIV2 EIMSK EXSPC BASE MODE IE MCGEN 6 5 4 3 2 1 Bit 0
AGREEMENT
Unimplemented
Figure 9-10. Modulator Control and Status Register (MCSR) EOC -- End Of Cycle Status Flag EOC is set when a match occurs between the contents of the space period register, SREG, and the down counter. This is recognized as the end of the modulation cycle. At this time, the counter is initialized with the (possibly new) contents of the mark period buffer, MBUFF, and the space period register, SREG, is loaded with the (possibly new) contents of the space period buffer, SBUFF. This flag is cleared by a read of the MCSR followed by an access of MDR2 or MDR3. The EOC flag is cleared by reset. 1 = End of modulator cycle (counter = SBUFF) has occurred 0 = Current modulation cycle in progress DIV2 -- Divide-by-two prescaler The divide-by-two prescaler causes the CMT to be clocked at the bus rate when enabled; 2 x the bus rate when disabled (fosc). This bit is not double buffered and so should not be set during a transmission. 1 = Divide-by-two prescaler enabled 0 = Divide-by-two prescaler disabled
NON-DISCLOSURE
General Release Specification 78 Carrier Modulator Transmitter (CMT)
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Modulator
EIMSK -- External Interrupt Mask The external interrupt mask bit is used to mask IRQ and keyscan interrupts. This bit is cleared by reset. 1 = IRQ and keyscan interrupts masked 0 = IRQ and keyscan interrupts enabled EXSPC -- Extended Space Enable For a description of the extended space enable bit, see 9.5.3 Extended Space Operation. This bit is cleared by reset. 1 = Extended space enabled 0 = Extended space disabled BASE -- Baseband Enable When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission. 1 = Baseband enabled 0 = Baseband disabled MODE -- Mode Select For a description of CMT operation in time mode, see 9.5.1 Time Mode. For a description of CMT operation in FSK mode, see 9.5.2 FSK Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission. 1 = CMT operates in FSK mode. 0 = CMT operates in time mode. IE -- Interrupt Enable A CPU interrupt will be requested when EOC is set if IE was previously set. If IE is clear, EOC will not request a CPU interrupt. 1 = CPU interrupt enabled 0 = CPU interrupt disabled
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 79
NON-DISCLOSURE
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED
MCGEN -- Modulator and Carrier Generator Enable Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. Once enabled, the carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator output is forced low. The user should initialize all data and control registers before enabling the system to prevent spurious operation. This bit is cleared by reset. 1 = Modulator and carrier generator enabled 0 = Modulator and carrier generator disabled
NON-DISCLOSURE
General Release Specification 80 Carrier Modulator Transmitter (CMT)
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Carrier Modulator Transmitter (CMT) Modulator
9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) The 12-bit MBUFF and SBUFF registers are accessed through three 8-bit registers: MDR1, MDR2, and MDR3. MDR2 and MDR3 contain the least significant eight bits of MBUFF and SBUFF respectively. MDR1 contains the two most significant nibbles of MBUFF and SBUFF. In many applications, periods greater than those obtained by eight bits will not be required. Dividing the registers in this manner allows the user to clear MDR1 and generate 8-bit periods with just two data writes.
Address: $0015 Bit 7 Read: MB11 Write: Reset: Unaffected by Reset MB10 MB9 MB8 SB11 SB10 SB9 SB8 6 5 4 3 2 1 Bit 0
Figure 9-11. Modulator Period Data Register MDR1
Address:
$0016 Bit 7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 Bit 0 MB0
MB7 Write: Reset:
Unaffected by Reset
Figure 9-12. Modulator Period Data Register MDR2
Address:
$0017 Bit 7 6 SB6 5 SB5 4 SB4 3 SB3 2 SB2 1 SB1 Bit 0 SB0
Read: SB7 Write: Reset: Unaffected by Reset
Figure 9-13. Modulator Period Data Register MDR3
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Carrier Modulator Transmitter (CMT)
General Release Specification 81
NON-DISCLOSURE
Read:
AGREEMENT
REQUIRED
Carrier Modulator Transmitter (CMT) REQUIRED NON-DISCLOSURE
General Release Specification 82 Carrier Modulator Transmitter (CMT)
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 10. EPROM
10.1 Contents
10.2 10.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
10.4 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.4.1 Bootloader Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 10.4.2 Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 10.4.3 Mask Option Registers (MOR1 and MOR2) . . . . . . . . . . . .87
10.2 Introduction
This section describes erasable programmable read-only memory (EPROM) programming.
10.3 EPROM
The user EPROM consists of 15,936 bytes of EPROM from $0180 to $3FAF and 14 bytes of user vectors from $3FF2 to $3FFF. The bootloader ROM and vectors are located from $3FB0 to $3FEF. Ten of the user vectors, $3FF6-$3FFF, are dedicated to reset and interrupt vectors. The four remaining locations, $3FF2-$3FF5, are general-purpose user EPROM locations. The mask option registers (MOR1 and MOR2) are located at $3FF0 and $3FF1.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA EPROM
General Release Specification 83
NON-DISCLOSURE
AGREEMENT
REQUIRED
EPROM REQUIRED 10.4 Bootloader
This program (contained in an on-chip boot ROM) handles copying of user code from an external EPROM into the on-chip EPROM. The bootloader function does not have to be done from an external EPROM, but can be done from a host.
10.4.1 Bootloader Functions Two pins are used to select the bootloader function. These pins are PC1 and PB5. PC1 is normally a SYNC pin, which is used to synchronize the MCU to an off-chip source that is driving EPROM data into the MCU. The programmer/host interface is shown in Figure 10-1.
DATA READ CLK (OUT)
AGREEMENT
SYNC (IN)
DATA IN
Figure 10-1. Programmer Interface to Host
NON-DISCLOSURE
If an external EPROM is used, this pin (PC1) must be connected to VSS. PB5 is used to select between program/verify or verify-only modes. Two other pins, PB2 and IRO, are used to drive the VERF LED and the PROG LED respectively. The programming modes are shown in Table 10-1. Table 10-1. Bootloader Functions
PC1
SYNC SYNC
PB5
1 0
Mode
Program/Verify Verify Only
The bootloader programming board shown in Figure 10-2 uses an external 12-bit counter to address the memory device containing the code to be copied. This counter requires a clock and a reset function. The 12-bit counter can address up to 4 Kbytes of memory, which means that two port pins have to be used to address the extra memory space.
General Release Specification 84 EPROM MC68HC705RC16 -- Rev. 3.0 MOTOROLA
EPROM Bootloader
NOTE:
The user code must be a one-to-one correspondence with the internal EPROM addresses.
VPP 1 IRQ/VPP OSC1 PA0 PA1 PA2 PA3 PA4 PA5 VDD PB0 PB1 LPRST 20 22 CE OE PA6 PA7 11 12 D0 VDD 27 28 A0 10 9 Q1 7 Q2 6 Q3 5 Q4 3 Q5 2 Q6 4 Q7 13 Q8 12 Q9 14 Q10 15 Q11 1 Q12 RST 11 VDD 16
4 MHz OSC2 10 MW 15 pF 15 pF
D1 13 D2 15 D3 16 17 18 D4 D5
2764
D6 19 D7
VDD VDD RESET VSS VDD PB3 VDD
8 CLK 10
A13 14
1 KW PB4 VDD PROG IRO 390 W VERF PB2 390 W 1 2 3 4 5 6 7 PC1 (SYNC) PB5 VDD 74LS04 14 13 12 11 10 9 8 PB7 PC0
NOTE: All resistors are 10 k unless specified otherwise.
Figure 10-2. MC68HC705RC16 Programming Circuit
MC68HC705RC16 -- Rev. 3.0 MOTOROLA EPROM
General Release Specification 85
NON-DISCLOSURE
VDD
AGREEMENT
9 A1 8 A2 7 A3 6 A4 5 A5 4 A6 3 A7 25 A8 24 A9 21 A10 23 A11 A12 2
MC14040B
REQUIRED
EPROM REQUIRED
10.4.2 Programming Register This register is used to program the EPROM array. Only the LATCH and EPGM bits are available in user mode. To program a byte of EPROM, set LATCH, then write data to the desired address, then set EPGM for tEPGM.
Address: $001E Bit 7 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 LATCH 0 1 R 0 Bit 0 EPGM 0
AGREEMENT
Read: R Write: Reset: 0 R
Figure 10-3. Programming Register (PROG) LATCH -- EPROM Latch Control READ: Any time WRITE: Any time 1 = EPROM address and data bus configured for programming. Causes address and data bus to be latched when a write to EPROM is done. EPROM cannot be read if LATCH = 1. 0 = EPROM address and data bus configured for normal reads EPGM -- EPROM Program Control READ: Any time WRITE: Any time security is not set 1 = VPP switched on to the EPROM array. If LATCH = 1, EPGM switches programming power to the EPROM array. 0 = Programming power switched off the EPROM array
NON-DISCLOSURE
General Release Specification 86 EPROM
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
EPROM Bootloader
10.4.3 Mask Option Registers (MOR1 and MOR2) The mask option registers contain programmable EPROM bits to control mask options. The MOR register is latched at the end of reset and refreshed periodically depending on how often the EPROM is read.
Address: $3FF0 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 6 5 4 3 SECUR 2 IRQ 1 STOP Bit 0 COP
= Unimplemented
Figure 10-4. Mask Option Register 1 (MOR1)
Address:
$3FF1 Bit 7 6 PB6PU 0 5 PB5PU 0 4 PB4PU 0 3 PB3PU 0 2 PB2PU 0 1 PB1PU 0 Bit 0 PB0PU 0
Read: PB7PU Write: Reset: 0
Figure 10-5. Mask Option Register 2 (MOR2) PBXPU -- Port B Pullup (X is 7-0) When set, the PBPU bit enables the pullup on the corresponding port B pin. If the PBPU bit is cleared, the pullup devices are disabled. The erased state of the PBPU bit is to be cleared, thereby disabling the pullup devices.
NOTE:
The MOR registers are reset to zero during reset. This causes the port B pullup devices to become inactive until reset is completed.
SECUR -- SECURITY Enable 1 = This bit secures the EPROM by disabling a read of the EPROM in all modes other than user. This bit also disables writes to the MOR registers and the programming register. 0 = The EPROM can be read in all modes.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA EPROM
General Release Specification 87
NON-DISCLOSURE
AGREEMENT
REQUIRED
EPROM REQUIRED
STOP -- STOP Enable 1 = This bit enables the STOP instruction. 0 = A STOP instruction is equivalent to a WAIT instruction. COP -- COP Enable 1 = This bit enables the COP watchdog timer. 0 = The COP is disabled. IRQ -- IRQ sensitivity 1 = This bit selects the edge- and level-sensitive IRQ. 0 = IRQ is edge-only sensitive.
AGREEMENT
NOTE:
The port B keyscan interrupt sensitivity will match that of the IRQ sensitivity. (See 4.7 External Interrupt (IRQ/Port B Pullup) for more information.)
NON-DISCLOSURE
General Release Specification 88 EPROM
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 11. Instruction Set
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .94 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .95 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .96 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .98 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 89
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set REQUIRED 11.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator.
AGREEMENT
11.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
NON-DISCLOSURE
General Release Specification 90
MC68HC705RC16 -- Rev. 3.0 Instruction Set MOTOROLA
Instruction Set Addressing Modes
11.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
11.3.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
11.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.
11.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 91
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set REQUIRED
11.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location.
AGREEMENT
11.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
NON-DISCLOSURE
11.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
General Release Specification 92 Instruction Set MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Instruction Set Instruction Types
11.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.
11.4 Instruction Types
The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 93
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set REQUIRED
11.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 11-1. Register/Memory Instructions
Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
AGREEMENT
Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator
NON-DISCLOSURE
General Release Specification 94
MC68HC705RC16 -- Rev. 3.0 Instruction Set MOTOROLA
Instruction Set Instruction Types
11.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 11-2. Read-Modify-Write Instructions
Instruction Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 95
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set REQUIRED
11.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register.
NON-DISCLOSURE
General Release Specification 96 Instruction Set
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Instruction Set Instruction Types
Table 11-3. Jump and Branch Instructions
Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL
BRCLR BRN BRSET BSR JMP JSR
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 97
NON-DISCLOSURE
BRA
AGREEMENT
REQUIRED
Instruction Set REQUIRED
11.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 11-4. Bit Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
AGREEMENT
Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set
NON-DISCLOSURE
General Release Specification 98 Instruction Set
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Instruction Set Instruction Types
11.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 11-5. Control Instructions
Instruction Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA
WAIT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 99
NON-DISCLOSURE
AGREEMENT
REQUIRED
Instruction Set REQUIRED 11.5 Instruction Set Summary
Table 11-6. Instruction Set Summary
Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
H I NZC
Add with Carry
A (A) + (M) + (C)
--
AGREEMENT
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL
ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----
NON-DISCLOSURE
ff dd
Arithmetic Shift Right
b7 b0
C
----
ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- ---------- ---------- REL REL REL REL REL REL
BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 PC (PC) + 2 + rel ? C = 0
General Release Specification 100 Instruction Set
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Cycles
Effect on CCR
Operand
Address Mode
Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Opcode Source Form
BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Operation
Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
H I NZC
---------- ----------
REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL
2F 2E A5 B5 C5 D5 E5 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
rr rr ii dd hh ll ee ff ff rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
Cycles
3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 2 2
Effect on CCR
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? C Z = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1
---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if Bit n Clear
PC (PC) + 2 + rel ? Mn = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSET n opr
Set Bit n
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0
----------
REL
AD
rr
CLC CLI
Clear Carry Bit Clear Interrupt Mask
-------- 0 -- 0 ------
INH INH
98 9A
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 101
NON-DISCLOSURE
AGREEMENT
REQUIRED
Operand
Address Mode
Instruction Set REQUIRED
Table 11-6. Instruction Set Summary (Continued)
Opcode Source Form
CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
Operation
Description
M $00 A $00 X $00 M $00 M $00
H I NZC
Clear Byte
---- 0 1 --
DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX
3F 4F 5F 6F 7F
dd
ff
AGREEMENT
Compare Accumulator with Memory Byte
(A) - (M)
----
ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
ff
Compare Index Register with Memory Byte
(X) - (M)
----
ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5
NON-DISCLOSURE
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
ff
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5
Increment Byte
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
----
--
ff
Unconditional Jump
PC Jump Address
----------
BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2
General Release Specification 102 Instruction Set
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Cycles
5 3 3 6 5
Effect on CCR
Operand
Address Mode
Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Opcode Source Form
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X
Operation
Description
H I NZC
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address
Jump to Subroutine
----------
DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX
BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
Negate Byte (Two's Complement)
----
ff
No Operation
----------
Logical OR Accumulator with Memory
A (A) (M)
----
--
Rotate Byte Left through Carry Bit
C b7 b0
----
ff
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 103
NON-DISCLOSURE
ff
AGREEMENT
Load Accumulator with Memory Byte
A (M)
----
--
Cycles
Effect on CCR
REQUIRED
Operand
Address Mode
Instruction Set REQUIRED
Table 11-6. Instruction Set Summary (Continued)
Opcode Source Form
ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
H I NZC
Rotate Byte Right through Carry Bit
b7 b0
C
----
DIR INH INH IX1 IX INH
36 46 56 66 76 9C
dd
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
AGREEMENT
RTI
Return from Interrupt

INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
81
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
NON-DISCLOSURE
Store Accumulator in Memory
M (A)
----
--
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
Subtract Memory Byte from Accumulator
A (A) - (M)
----
ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3
SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
10
TAX
Transfer Accumulator to Index Register
INH
97
General Release Specification 104 Instruction Set
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Cycles
5 3 3 6 5 2 9 6 2
Effect on CCR
Operand
Address Mode
Instruction Set Instruction Set Summary
Table 11-6. Instruction Set Summary (Continued)
Opcode Source Form
TST opr TSTA TSTX TST opr,X TST ,X TXA WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
Operation
Description
H I NZC
Test Memory Byte for Negative or Zero
(M) - $00
----
--
DIR INH INH IX1 IX INH INH
3D 4D 5D 6D 7D 9F 8F
dd
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
A (X)
---------- -- 0------
2
Cycles
4 3 3 5 4 2
Effect on CCR
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Instruction Set
General Release Specification 105
NON-DISCLOSURE
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
AGREEMENT
REQUIRED
Operand
Address Mode
NON-DISCLOSURE
106 Instruction Set MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification
AGREEMENT
REQUIRED Instruction Set
Table 11-7. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2
DIR 3
Read-Modify-Write INH INH IX1 4 5 6
IX 7
Control INH INH 8
9 RTI INH 6 RTS INH
IMM A
2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2
DIR B
Register/Memory EXT IX2 C
4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3
IX1 E
4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1
IX F
3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA IX 3 EOR IX 3 ADC IX 3 ORA IX 3 ADD IX 2 JMP IX 5 JSR IX 3 LDX IX 4 STX IX MSB LSB
0
1
9
D
5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2
0 1 2 3 4 5 6 7 8 9 A B C D E F
5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BSET7 BIL 3 DIR 2 DIR 2 REL 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1
2 2 2
10 SWI INH
2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2
2 STOP INH 2 2 WAIT TXA INH 1 INH
6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB
3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3
0 1 2 3 4 5 6 7 8 9 A B C D E F
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal
0
5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode
General Release Specification -- MC68HC705RC16
Section 12. Electrical Specifications
12.1 Contents
12.2 12.3 12.4 12.5 12.6 12.7 12.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .109 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 DC Electrical Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . .110 DC Electrical Characteristics (3.3 Vdc). . . . . . . . . . . . . . . . . .111 Control Timing (5.0 Vdc and 3.3 Vdc). . . . . . . . . . . . . . . . . . .112
12.2 Introduction
This section contains the electrical and timing specifications.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Electrical Specifications
General Release Specification 107
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 12.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating Supply Voltage Bootloader Mode (IRQ/VPP Pin Only) Current Drain Per Pin Excluding VDD and VSS Operating Junction Temperature Storage Temperature Range Symbol VDD VIN I TJ Tstg Value -0.3 to +7.0 VSS -0.3 to 2 x VDD + 0.3 25 +150 -65 to +150 Unit V V mA C C
AGREEMENT
NON-DISCLOSURE
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 12.6 DC Electrical Characteristics (5.0 Vdc) and 12.7 DC Electrical Characteristics (3.3 Vdc) for guaranteed operating conditions.
General Release Specification 108 Electrical Specifications
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Electrical Specifications Operating Temperature Range
12.4 Operating Temperature Range
Characteristic Operating Temperature Range Standard Symbol TA Value TL to TH 0 to +70 Unit C
12.5 Thermal Characteristics
Characteristic Thermal Resistance Plastic Dual In-Line Package Small Outline Intergrated Circuit Package Plastic Leaded Chip Carrier Package Symbol Value 60 60 60 Unit
JA
C/W
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Electrical Specifications
General Release Specification 109
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specifications REQUIRED 12.6 DC Electrical Characteristics (5.0 Vdc)
Characteristic Output Voltage ILOAD = 10.0 A ILOAD = -10.0 A Output High Voltage (ILOAD -2.0 mA) Port A, Port B, Port C (1-7) (ILOAD -15 mA) IRO (ILOAD -4.0 mA) Port C (Bit 0) Output Low Voltage (ILOAD = 3.0 mA) Port A, Port B, Port C (1-7) (ILOAD = 25.0 mA) IRO (ILOAD = 20.0 mA) Port C (Bit 0) Input High Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 Input Low Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 EPROM Programming Voltage Supply Current (see Notes) Run Wait Stop 25 oC 0 to +70 oC I/O Ports Hi-Z Leakage Current Port A, Port B, Port C Input Current RESET, LPRST, IRQ, OSC1 PB0-PB7 with Pullups Enabled (VIN = 0.2 x VDD)8 PB0-PB7 with Pullups Enabled (VIN = 0.7 x VDD) Capacitance Ports (as Input or Output) RESET, LPRST, IRQ Symbol VOL VOH VOH Min -- VDD- 0.1 VDD -0.8 VDD -0.7 VDD -0.8 -- -- -- 0.7 x VDD VSS 14.5 -- -- -- -- IOZ -10 -1 IIN -100 -50 COUT CINT -- -- Typ -- -- VDD -0.2 VDD -0.2 VDD -0.2 0.2 0.2 0.2 -- -- -- 3.8 0.5 03 0.3 -- -- -330 -120 -- -- Max 0.1 -- -- -- -- 0.4 0.8 0.4 VDD 0.2 x VDD 15.5 5.0 1.2 15 30 10 1 -700 -300 12 8 pF A Unit V
V
AGREEMENT
VOL
V
VIH VIL V
V V V mA mA A A A
IDD
NON-DISCLOSURE
NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25 C, only represent average measurements 3. Wait IDD: only core timer active 4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source (fOsc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 5. Wait, Stop IDD: port A and port C configured as inputs, port B configured as outputs. VIL = 0.2 V, VIH = VDD -0.2 V 6. Stop IDD is measured with OSC1 = VSS. 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. Pullups are designed to be capable of pulling to VIH within 1 s for a 100 pF, 4-k load
General Release Specification 110 Electrical Specifications
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Electrical Specifications DC Electrical Characteristics (3.3 Vdc)
12.7 DC Electrical Characteristics (3.3 Vdc)
Characteristic Output Voltage ILOAD = 10.0 A ILOAD = -10.0 A Output High Voltage (ILOAD -0.6 mA) Port A, Port B, Port C (1-7) (ILOAD -10.0 mA) IRO (ILOAD -1.2 mA) Port C (Bit 0) Output Low Voltage (ILOAD = 1.0 mA) Port A, Port B, Port C (1-7) (ILOAD = 8.0 mA) IRO (ILOAD = 7.0 mA) Port C (Bit 0) Input High Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 Input Low Voltage Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 EPROM Programming Voltage Supply Current (see Notes) Run Wait Stop 25 oC 0 to +70 oC I/O Ports Hi-Z Leakage Current Port A, Port B, Port C Input Current RESET, LPRST, IRQ, OSC1 PB0-PB7 with pullups enabled (VIN = 0.4 x VDD) 8 PB0-PB7 with pullups enabled (VIN = 0.7 x VDD) Capacitance Ports (as Input or Output) RESET, LPRST, IRQ Symbol VOL VOH VOH Min -- VDD- 0.1 VDD- 0.3 VDD- 0.7 VDD- 0.3 -- -- -- 0.7 x VDD VSS 14.5 -- -- -- -- IOZ -4 -0.4 IIN -25 -15 COUT CINT -- -- Typ -- -- VDD- 0.1 VDD- 0.1 VDD- 0.1 0.1 0.1 0.1 -- -- -- 1.8 0.33 0.1 0.1 -- -- -80 -50 -- -- Max 0.1 -- -- -- -- 0.3 0.8 0.3 VDD 0.4 x VDD 15.5 3.0 0.8 4.0 8.0 4 0.4 -105 -65 12 8 pF A Unit V
V
VIH VIL V
V V V mA mA A A A
IDD
NOTES: 1. VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TL = 0 C to +70 C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25 C, only represent average measurements. 3. Wait IDD: only core timer active 4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source (fOsc = 4.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 5. Wait, Stop IDD: port A and port C configured as inputs, port B configured as outputs. VIL = 0.2 V, VIH = VDD -0.2 V 6. Stop IDD is measured with OSC1 = VSS. 7. Wait IDD is affected linearly by the OSC2 capacitance. 8. Pullups are designed to be capable of pulling to VIH within 25 s for a 100 pF, 4-k load
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Electrical Specifications
General Release Specification 111
NON-DISCLOSURE
AGREEMENT
VOL
V
REQUIRED
Electrical Specifications REQUIRED 12.8 Control Timing (5.0 Vdc and 3.3 Vdc)
Characteristic Frequency of Operation Crystal External Clock Internal Operating Frequency Crystal (fOSC /2) External Clock (fOSC /2) Cycle Time Symbol fosc Min -- dc -- dc 480 -- -- 1.5 125 Note 2 90 -- Max 4.2 4.2 2.1 2.1 -- 100 100 -- -- -- -- 10.0 Unit MHz
fop tcyc tOXOV tILCH tRL tILIH tILIL tOH, tOL tEPGM
MHz ns ms ms tcyc ns tcyc ns ms
AGREEMENT NON-DISCLOSURE
Crystal Oscillator Startup Time Stop Recovery Startup Time (Crystal Oscillator) RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width EPROM Byte Programming Time
NOTES: 1. VDD = 3.0 to 5.5 Vdc, VSS = 0 Vdc, TA = 0 oC to +70 oC, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC.
General Release Specification 112 Electrical Specifications
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 13. Mechanical Specifications
13.1 Contents
13.2 13.3 13.4 13.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 28-Pin Plastic Dual In-Line Package (Case 710-02) . . . . . . .114 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . .114 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02). . . . . . . . . . . . . . . . . . . . . . . . . . .115
13.2 Introduction
This section describes the dimensions of the dual-in-line package (DIP), small outline integrated circuit (SOIC) MCU package, and the plastic leaded chip carrier (PLCC) package. The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, contact one of the following: * * Local Motorola Sales Office Motorola Mfax - Phone 602-244-6609 - EMAIL rmfax0@email.sps.mot.com Worldwide Web (wwweb) at http://design-net.com
*
Follow Mfax or wwweb on-line instructions to retrieve the current mechanical specifications.
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Mechanical Specifications
General Release Specification 113
NON-DISCLOSURE
AGREEMENT
REQUIRED
Mechanical Specifications REQUIRED 13.3 28-Pin Plastic Dual In-Line Package (Case 710-02)
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
28
15
B
1 14
AGREEMENT
A N
C
L
H
G F D
K
SEATING PLANE
M
J
13.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04)
-A28 15 14X
NON-DISCLOSURE
-B1 14
P 0.010 (0.25)
M
B
M
28X D
0.010 (0.25)
M
T
A
S
B
S
M R X 45
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8 0 0.395 0.415 0.010 0.029
-T26X
C G K -TSEATING PLANE
F J
General Release Specification 114 Mechanical Specifications
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Mechanical Specifications 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02)
13.5 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02)
-NY BRK D B 0.007(0.180) M T U L-M S NS NS
0.007(0.180) M T
L-M S
Z -L-M-
V
44 1
W
D
X VIEW D-D
G1 0.010 (0.25) S T L-M S NS
A R Z
0.007(0.180) M T 0.007(0.180) M T
L-M S L-M S
NS NS H 0.007(0.180) M T L-M S NS
J E C G -TG1 0.010 (0.25) S T L-M S NS VIEW S VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOLDERS EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF THE MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMINSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTUSION(S) SHALL NOT CAUSE THE H DIMINSION TO BE GREATER THAN 0.037 (0.940116). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635).
K1 0.004 (0.10)
SEATING PLANE K
F 0.007(0.180) M T L-M S NS
INCHES DIM A B C E F G H J K R U V W X Y Z G1 K1 MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.610 0.630 0.040
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 0.50 2 10 15.50 16.00 1.02
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Mechanical Specifications
General Release Specification 115
NON-DISCLOSURE
AGREEMENT
REQUIRED
Mechanical Specifications REQUIRED NON-DISCLOSURE
General Release Specification 116 Mechanical Specifications
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
General Release Specification -- MC68HC705RC16
Section 14. Ordering Information
14.1 Contents
14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
14.2 Introduction
This section contains ordering instructions for the MC68HC705RC16.
14.3 Ordering Information
Table 14-1 provides information in determing order numbers. Table 14-1. MC Order Numbers
Package Type 28-Pin Plastic Dual In-Line Package (DIP) 28-Pin Small Outline Integrated Circuit Package (SOIC) 44-Lead Plastic Leaded Chip Carrier Package (PLCC) Operating Temperature Range 0 to 70 C 0 to 70 C 0 to 70 C MC Order Number
MC68HC705RC16P MC68HC705RC16DW MC68HC705RC16FN
MC68HC705RC16 -- Rev. 3.0 MOTOROLA Ordering Information
General Release Specification 117
NON-DISCLOSURE
AGREEMENT
REQUIRED
Ordering Information REQUIRED NON-DISCLOSURE
General Release Specification 118 Ordering Information
AGREEMENT
MC68HC705RC16 -- Rev. 3.0 MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-800-441-2447 or 303-675-2140 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
Mfax is a trademark of Motorola, Inc. (c) Motorola, Inc., 1997
HC705RC16GRS/D

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