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19-2864; Rev 0; 4/03
Programmable DC-Balance 21-Bit Deserializers
General Description
The MAX9210/MAX9212/MAX9214/MAX9216 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a separate supply, allowing 1.8V to 5V output logic levels. The MAX9210/MAX9212/MAX9214/MAX9216 feature programmable DC balance, which allows isolation between serializer and deserializer using AC-coupling. A deserializer decodes data transmitted by a MAX9209/MAX9211/MAX9213/MAX9215 serializer. When DC balance is not programmed, the deserializers are compatible with non-DC-balanced 21-bit deserializers like the DS90CR216A and DS90CR218A. Two frequency versions and two DC-balance default conditions are available for maximum replacement flexibility and compatibility with popular non-DC balanced serializers. The transition time of the single-ended outputs is increased on the low-frequency version parts (MAX9210/MAX9212) for reduced EMI. The MAX9210/MAX9212/MAX9214/MAX9216 are available in TSSOP and space-saving thin QFN packages, and operate over the -40C to +85C temperature range.
Features
o Programmable DC Balance or Non-DC Balance o DC Balance Allows AC-Coupling for Wider Input Common-Mode Voltage Range o As Low as 8MHz Operation (MAX9210/MAX9212) o Slower Output Transitions for Reduced EMI (MAX9210/MAX9212) o High-Impedance Outputs when PWRDWN Is Low Allow Output Busing o Pin Compatible with DS90CR216A/DS90CR218A o Fail-Safe Inputs in Non-DC-Balanced Mode o 5V Tolerant PWRDWN Input o PLL Requires No External Components o Up to 1.785Gbps Throughput o Separate Output Supply Pins Allow Interface to 1.8V, 2.5V, 3.3V, and 5V Logic o LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD Requirements o LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS Standard o Low-Profile 48-Lead TSSOP and Space-Saving QFN Packages o +3.3V Main Supply o -40C to +85C Operating Temperature Range
MAX9210/MAX9212/MAX9214/MAX9216
Applications
Automotive Navigation Systems Automotive DVD Entertainment Systems Digital Copiers Laser Printers
PART MAX9210ETM* MAX9210EUM* MAX9212ETM* MAX9212EUM* MAX9214ETM* MAX9214EUM MAX9216ETM* MAX9216EUM*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 48 Thin QFN-EP** 48 TSSOP 48 Thin QFN-EP** 48 TSSOP 48 Thin QFN-EP** 48 TSSOP 48 Thin QFN-EP** 48 TSSOP
*Future product--contact factory for availability. **EP = Exposed pad.
Functional Diagram and Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.5V to +4.0V VCCO to GND.........................................................-0.5V to +6.0V RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V PWRDWN to GND .................................................-0.5V to +6.0V DCB/NC to GND.........................................-0.5V to (VCC + 0.5V) RxOUT_, RxCLK OUT to GND .................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70C) 48-Pin TSSOP (derate 16mW/C above +70C) ........ 1282mW 48-Lead Thin QFN (derate 26.3mW/C above +70C) .2105mW Storage Temperature Range..............................-65C to +150C Junction Temperature ......................................................+150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) All Pins to GND ................................................................5kV IEC 61000-4-2 (RD = 330, CS = 150pF) Level 4 Contact Discharge LVDS Inputs (RxIN_, RxCLK IN_) to GND .............................................................................8kV Air Discharge LVDS Inputs (RxIN_, RxCLK IN_) to GND ...........................................................................15kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID/2 to 2.4V - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID = 0.2V, VCM = 1.25V, TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL PWRDWN High-Level Input Voltage Low-Level Input Voltage Input Current Input Clamp Voltage VIH VIL IIN VCL VIN = high or low, PWRDWN = high or low ICL = -18mA VCCO 0.1 V IOH = -2mA Low-Level Output Voltage High-Impedance Output Current Output Short-Circuit Current Note: Short one output at a time. LVDS INPUTS Differential Input High Threshold Differential Input Low Threshold VTH VTL -50 50 mV mV VOL IOZ IOS IOL = 100A IOL = 2mA PWRDWN = low, VOUT_ = -0.3V to VCCO + 0.3V VCCO = 3.0V to 3.6V, VOUT = 0V VCCO = 4.5V to 5.5V, VOUT = 0V -20 -10 -28 VCCO 0.25 0.1 0.2 +20 -40 -75 V A mA DCB/NC CONDITIONS MIN 2.0 2.0 -0.3 -20 TYP MAX 5.5 VCC + 0.3 +0.8 +20 -1.5 V V A V UNITS
SINGLE-ENDED INPUTS (PWRDWN, DCB/NC)
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT) IOH = -100A High-Level Output Voltage VOH
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Programmable DC-Balance 21-Bit Deserializers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.05V to 1.2V, input common-mode voltage VCM = VID/2 to 2.4V - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID = 0.2V, VCM = 1.25V, TA = +25C.) (Notes 1, 2)
PARAMETER Input Current Power-Off Input Current Input Resistor 1 Input Resistor 2 POWER SUPPLY CL = 8pF, worst-case pattern, DC-balanced mode; VCC = VCCO = 3.0V to 3.6V, Figure 2 Worst-Case Supply Current ICCW CL = 8pF, worst-case pattern, non-DCbalanced mode; VCC = VCCO = 3.0V to 3.6V, Figure 2 PWRDWN = low 16MHz 34MHz 66MHz 20MHz 33MHz 40MHz 66MHz 85MHz 52 86 152 53 72 81 127 159 63 106 177 64 85 99 149 186 50 A mA SYMBOL IIN+, IINIINO+, IINORIN1 RIN2 CONDITIONS PWRDWN = high or low VCC = VCCO = 0V or open, DCB/NC, PWRDWN = 0V or open PWRDWN = high or low (Figure 1) VCC = VCCO = 0V or open (Figure 1) PWRDWN = high or low (Figure 1) VCC = VCCO = 0V or open (Figure 1) MIN -25 -25 42 246 TYP MAX +25 +25 78 410 UNITS A A k k
MAX9210/MAX9212/MAX9214/MAX9216
Power-Down Supply Current
ICCZ
AC ELECTRICAL CHARACTERISTICS
(VCC = VCCO = +3.0V to 3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.1V to 1.2V, input common-mode voltage VCM = VID/2 to 2.4V - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID = 0.2V, VCM = 1.25V, TA = 25C.) (Notes 3, 4, 5)
PARAMETER Output Rise Time Output Fall Time SYMBOL CLHT CHLT CONDITIONS 0.1VCCO to 0.9VCCO, Figure 3 0.9VCCO to 0.1VCCO, Figure 3 DC-balanced mode, Figure 4 (Note 6) RxIN Skew Margin RSKM Non-DC-balanced mode, Figure 4 (Note 6) MAX9214/ MAX9216 MAX9214/ MAX9216 16MHz 34MHz 66MHz 20MHz 40MHz 85MHz MIN 2.2 1.3 2560 900 330 2500 960 330 TYP 3.15 2.12 3137 1327 685 3300 1448 685 ps MAX 3.9 2.9 UNITS ns ns
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCCO = +3.0V to 3.6V, 100mVP-P at 200kHz supply noise, CL = 8pF, PWRDWN = high, DCB/NC = high or low, differential input voltage VID = 0.1V to 1.2V, input common-mode voltage VCM = VID/2 to 2.4V - VID/2, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = VCCO = +3.3V, VID = 0.2V, VCM = 1.25V, TA = 25C.) (Notes 3, 4, 5)
PARAMETER RxCLK OUT High Time RxCLK OUT Low Time RxOUT Setup to RxCLK OUT RxOUT Hold from RxCLK OUT RxCLK IN to RxCLK OUT Delay Deserializer Phase-Locked Loop Set Deserializer Power-Down Delay SYMBOL RCOH RCOL RSRC RHRC RCCD RPLLS RPDD Figure 5 Figure 5 Figure 5 Figure 5 Figure 6 Figure 7 Figure 8 CONDITIONS MIN 0.35 x RCOP 0.35 x RCOP 0.30 x RCOP 0.45 x RCOP 4.9 TYP 0.4 x RCOP 0.44 x RCOP 0.35 x RCOP 0.48 x RCOP 6.17 8.1 32800 x RCIP 100 MAX UNITS ns ns ns ns ns ns ns
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 4: CL includes probe and test jig capacitance. Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP. Note 6: RSKM measured with 150ps cycle-to-cycle jitter on RxCLK IN.
Typical Operating Characteristics
(VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage VID = 0.2V, input common-mode voltage VCM = 1.2V, unless otherwise noted.)
WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY
MAX9210 toc01
WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY
MAX9210 toc02
OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9214 NON-DC-BALANCED MODE OUTPUT TRANSITION TIME (ns) 4 tR 3 tF 2
MAX9210 toc03
160 140 SUPPLY CURRENT (mA) 120 100 80 60 40 5 20 35 50 65 MAX9214 DC-BALANCED MODE
180 160 SUPPLY CURRENT (mA) 140 120 100 80 60 40 MAX9214 NON-DC-BALANCED MODE
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1 15 35 55 FREQUENCY (MHz) 75 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT SUPPLY VOLTAGE (V)
80
FREQUENCY (MHz)
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Programmable DC-Balance 21-Bit Deserializers
Pin Description
PIN TSSOP 1, 2, 4, 5, 45, 46, 47 3, 25, 32, 38, 44 QFN 39, 40, 41, 43, 44, 46, 47 19, 26, 32, 38, 45 NAME RxOUT14- RxOUT20 GND FUNCTION Channel 2 Single-Ended Outputs Ground LVTTL/LVCMOS DC-Balance Programming Input: MAX9210: pulled up to VCC MAX9212: pulled down to GND MAX9214: pulled up to VCC MAX9216: pulled down to GND See Table 1. LVDS Ground Inverting Channel 0 LVDS Serial Data Input Noninverting Channel 0 LVDS Serial Data Input Inverting Channel 1 LVDS Serial Data Input Noninverting Channel 1 LVDS Serial Data Input LVDS Supply Voltage Inverting Channel 2 LVDS Serial Data Input Noninverting Channel 2 LVDS Serial Data Input Inverting LVDS Parallel Rate Clock Input Noninverting LVDS Parallel Rate Clock Input PLL Ground PLL Supply Voltage 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are high impedance when PWRDWN = low or open. Parallel Rate Clock Single-Ended Output Channel 0 Single-Ended Outputs Output Supply Voltage Channel 1 Single-Ended Outputs Digital Supply Voltage Exposed Paddle. Solder to ground.
MAX9210/MAX9212/MAX9214/MAX9216
6
48
DCB/NC
7, 13, 18 8 9 10 11 12 14 15 16 17 19, 21 20 22 23 24, 26, 27, 29, 30, 31, 33 28, 36, 48 34, 35, 37, 39, 40, 41, 43 42 --
1, 7, 12 2 3 4 5 6 8 9 10 11 13, 15 14 16 17 18, 20, 21, 23, 24, 25, 27 22, 30, 42 28, 29, 31, 33, 34, 35, 37 36 EP
LVDS GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS VCC RxIN2RxIN2+ RxCLK INRxCLK IN+ PLL GND PLL VCC PWRDWN RxCLK OUT RxOUT0- RxOUT6 VCCO RxOUT7- RxOUT13 VCC EP
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
VCC
Table 1. DC-Balance Programming
DEVICE DCB/NC High or open OPERATING MODE DC balanced Non-DC balanced DC balanced Non-DC balanced DC balanced Non-DC balanced DC balanced Non-DC balanced OPERATING FREQUENCY (MHz) 8 to 34 10 to 40 8 to 34 10 to 40 16 to 66 20 to 85 16 to 66 20 to 85
RIN2
RxIN_ + OR RxCLK IN+ VCC - 0.3V RIN1
RxIN_ + OR RxCLK IN+
MAX9210
Low High
RIN1 1.2V
MAX9212
Low or open High or open
RIN1
RIN1
MAX9214
RxIN_ - OR RxCLK INNON-DC-BALANCED MODE RxIN_ - OR RxCLK INDC-BALANCED MODE
Low High
MAX9216
Low or open
Figure 1. LVDS Input Circuits
Detailed Description
The MAX9210/MAX9212 operate at a parallel clock frequency of 8MHz to 34MHz in DC-balanced mode and 10MHz to 40MHz in non-DC-balanced mode. The MAX9214/MAX9216 operate at a parallel clock frequency of 16MHz to 66MHz in DC-balanced mode and 20MHz to 85MHz in non-DC-balanced mode. The transition times of the single-ended outputs are increased on the MAX9210/MAX9212 for reduced EMI. DC-balanced or non-DC-balanced operation is controlled by the DCB/NC pin (see Table 1 for DCB/NC default settings and operating modes). In non-DC-balanced mode, each channel deserializes 7 bits every cycle of the parallel clock. In DC-balanced mode, 9 bits are deserialized every clock cycle (7 data bits + 2 DCRCIP RxCLK OUT
ODD RxOUT EVEN RxOUT
Figure 2. Worst-Case Test Pattern
90%
90%
RxOUT_ OR RxCLK OUT
RxOUT_ OR RxCLK OUT 8pF
10%
10%
CLHT
CHLT
Figure 3. Output Load and Transition Times
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
2V
IDEAL SERIAL BIT TIME 1.3V
PWRDWN 3V
1.1V RSKM IDEAL MIN MAX RSKM IDEAL
VCC RPLLS
RxCLK IN
INTERNAL STROBE
Figure 4. LVDS Receiver Input Skew Margin
RxCLK OUT
HIGH-Z
RCIP RxCLK OUT 0.8V 2.0V 0.8V RCOL RSRC RxOUT_ 2.0V SETUP 2.0V RCOH RHRC 2.0V HOLD 2.0V
Figure 7. Phase-Locked Loop Set Time
PWRDWN
0.8V
Figure 5. Output Setup/Hold and High/Low Times
RxCLK IN RxCLK IN VID = 0 RCCD 1.5V RxCLK OUT RxOUT_ RxCLK OUT HIGH-Z
RPDD
Figure 6. Clock-IN to Clock-OUT Delay
Figure 8. Power-Down Delay
balance bits). The highest data rate in DC-balanced mode for the MAX9214 or MAX9216 is 66MHz x 9 = 594Mbps. In non-DC-balanced mode, the maximum data rate is 85MHz x 7 = 595Mbps.
DC Balance
Data coding by the MAX9210/MAX9212/MAX9214/ MAX9216 serializers (which are companion devices to the MAX9209/MAX9211/MAX9213/MAX9215 deserializers) limits the imbalance of ones and zeros transmitted on each channel. If +1 is assigned to each binary 1 transmitted and -1 is assigned to each binary 0 transmitted, the variation in the running sum of assigned values is called the digital sum variation (DSV). The maximum DSV for the data channels is 10. At most, 10 more zeros
than ones, or 10 more ones than zeros, are transmitted. The maximum DSV for the clock channel is five. Limiting the DSV and choosing the correct coupling capacitors maintains differential signal amplitude and reduces jitter due to droop on AC-coupled links. To obtain DC balance on the data channels, the serializer parallel data is inverted or not inverted, depending on the sign of the digital sum at the word boundary. Two complementary bits are appended to each group of 7 parallel input data bits to indicate to the MAX9210/ MAX9212/MAX9214/MAX9216 deserializers whether the data bits are inverted (see Figures 9 and 10). The deserializer restores the original state of the parallel data. The LVDS clock signal alternates duty cycles of 4/9 and 5/9, which maintain DC balance.
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be eliminated by increasing the receiver common-mode voltage range by AC-coupling. AC-coupling increases the common-mode voltage range of an LVDS receiver to nearly the voltage rating of the capacitor. The typical LVDS driver output is 350mV centered on an offset voltage of 1.25V, making single-ended output voltages of 1.425V and 1.075V. An LVDS receiver accepts signals from 0V to 2.4V, allowing approximately 1V common-mode difference between the driver and receiver on a DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V). Common-mode voltage differences may be due to ground potential variation or common-mode noise. If there is more than 1V of difference, the receiver is not guaranteed to read the input signal correctly and may cause bit errors. AC-coupling filters low-frequency ground shifts and common-mode noise and passes high-frequency data. A common-mode voltage difference up to the voltage rating of the coupling capacitor (minus half the differential swing) is tolerated. DC-balanced coding of the data is required to maintain the differential signal amplitude and limit jitter on an ACcoupled link. A capacitor in series with each output of the LVDS driver is sufficient for AC-coupling. However, two capacitors--one at the serializer output and one at the deserializer input--provide protection in case either end of the cable is shorted to a high voltage.
+ RxCLK IN CYCLE N - 1 TxIN15 RxIN2 TxIN14 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 CYCLE N + 1 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
TxIN8 RxIN1
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN1 RxIN0
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN_ IS DATA FROM THE SERIALIZER.
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
+ RxCLK IN CYCLE N - 1 DCA2 RxIN2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N TxIN17 TxIN16 TxIN15 TxIN14 DCA2 DCB2 TxIN20 TxIN19 TxIN18 CYCLE N + 1 TxIN17 TxIN16 TxIN15 TxIN14
DCA1 RxIN1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA1
DCB1
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
DCA0 RxIN0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
DCA0
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
Figure 10. Deserializer Serial Input in DC-Balanced Mode 8 _______________________________________________________________________________________
Programmable DC-Balance 21-Bit Deserializers
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols causes signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the LVDS receiver termination resistor (RT), the LVDS driver output resistor (RO), and the series AC-coupling capacitors (C). The RC time constant for two equal-value series capacitors is (C x (RT + RO))/2 (Figure 12). The RC time constant for four equal-value series capacitors is (C x (RT + RO))/4 (Figure 13). RT is required to match the transmission line impedance (usually 100) and RO is determined by the LVDS driver design (the minimum differential output resistance of 78 for the MAX9209/MAX9211/MAX9213/ MAX9215 serializers is used in the following example). This leaves the capacitor selection to change the system time constant. In the following example, the capacitor value for a droop of 2% is calculated. Jitter due to this droop is then calculated assuming a 1ns transition time: C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1) where: C = AC-coupling capacitor (F) tB = bit time (s) DSV = digital sum variation (integer) ln = natural log D = droop (% of signal amplitude) RT = termination resistor () RO = output resistance () Equation 1 is for two series capacitors (Figure 12). The bit time (tB) is the period of the parallel clock divided by 9. The DSV is 10. See equation 3 for four series capacitors (Figure 13). The capacitor for 2% maximum droop at 8MHz parallel rate clock is: C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100 + 78)) C = 0.0773F
MAX9210/MAX9212/MAX9214/MAX9216
MAX9209 MAX9211 MAX9213 MAX9215
TxOUT 7 7:1
TRANSMISSION LINE RxIN
MAX9210 MAX9212 MAX9214 MAX9216
7 100 1:7
7 TxIN 7:1 100 1:7
7 RxOUT
7 7:1 100 1:7
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 3:21 DESERIALIZER 100 PLL
PWRDWN RxCLK OUT
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode _______________________________________________________________________________________ 9
Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
MAX9209 MAX9211 MAX9213 MAX9215
HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS CAN ALSO BE PLACED AT THE SERIALIZER INSTEAD OF THE DESERIALIZER. TxOUT 7 (7 + 2):1 100 1:(9 - 2) RxIN 7
MAX9210 MAX9212 MAX9214 MAX9216
7 TxIN (7 + 2):1 100 1:(9 - 2)
7 RxOUT
7 (7 + 2):1 100 1:(9 - 2)
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 3:21 DESERIALIZER 100 PLL
PWRDWN RxCLK OUT
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
Jitter due to droop is proportional to the droop and transition time: tJ = tT x D (Eq 2) where: tJ = jitter (s) tT = transition time (s) (0% to 100%) D = droop (% of signal amplitude) Jitter due to 2% droop and assumed 1ns transition time is: tJ = 1ns x 0.02 tJ = 20ps The transition time in a real system depends on the frequency response of the cable driven by the serializer. The capacitor value decreases for a higher frequency parallel clock and for higher levels of droop and jitter. Use high-frequency, surface-mount ceramic capacitors. Equation 1 altered for four series capacitors (Figure 13) is: C = - (4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Fail-Safe
The MAX9210/MAX9212/MAX9214/MAX9216 have failsafe LVDS inputs in non-DC-balanced mode (Figure 1). Fail-safe drives the outputs low when the corresponding LVDS input is open, undriven and shorted, or undriven and parallel terminated. The fail-safe on the LVDS clock input drives all outputs low. Fail-safe does not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting LVDS inputs are internally connected to +1.2V through 42k (min) to provide biasing for AC-coupling (Figure 1). A frequency-detection circuit on the clock input detects when the input is not switching, or is switching at low frequency. In this case, all outputs are driven low. To prevent switching due to noise when the clock input is not driven, bias the clock input to differential +15mV by connecting a 10k 1% pullup resistor between the noninverting input and VCC, and a 10k 1% pulldown resistor between the inverting input and ground. These bias resistors, along with the 100 1% tolerance termination resistor, provide +15mV of differential input. However, the +15mV bias causes degradation of
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Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
MAX9209 MAX9211 MAX9213 MAX9215
HIGH-FREQUENCY, CERAMIC SURFACE-MOUNT CAPACITORS
MAX9210 MAX9212 MAX9214 MAX9216
RxIN 7
TxOUT 7 (7 + 2):1 100
1:(9 - 2)
7 TxIN (7 + 2):1 100 1:(9 - 2)
7 RxOUT
7 (7 + 2):1 100 1:(9 - 2)
7
PWRDWN PLL TxCLK IN TxCLK OUT 21:3 SERIALIZER RxCLK IN 3:21 DESERIALIZER 100 PLL
PWRDWN RxCLK OUT
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
RSKM proportional to the slew rate of the clock input. For example, if the clock transitions 250mV in 500ps, the slew rate of 0.5mV/ps reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data inputs open. In non-DC balanced mode, the input failsafe circuit drives the corresponding outputs low and no pullup or pulldown resistors are needed. In DC-balanced mode, at each unused LVDS data input, pull the inverting input up to VCC using a 10k resistor, and pull the noninverting input down to ground using a 10k resistor. Do not connect a termination resistor. The pullup and pulldown resistors drive the corresponding outputs low and prevent switching due to noise.
trolled by PWRDWN. Wait 100ns between disabling one deserializer (driving PWRDWN low) and enabling the second one (driving PWRDWN high) to avoid contention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the application or reapplication of the parallel rate clock (RxCLK IN) relative to PWRDWN, or to a power-supply ramp for proper PLL lock. The PLL lock time is set by an internal counter. The maximum time to lock is 32,800 clock periods. Power and clock should be stable to meet the lock time specification. When the PLL is locking, the outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital circuits, outputs, PLL, and LVDS inputs. Bypass each VCC, VCCO, PLL VCC, and LVDS VCC pin with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
PWRDWN
Driving PWRDWN low puts the outputs in high impedance, stops the PLL, and reduces supply current to 50A or less. Driving PWRDWN high drives the outputs low until the PLL locks. The outputs of two deserializers can be bused to form a 2:1 mux with the outputs con-
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11
Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
Cables and Connectors
Interconnect for LVDS typically has a differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degradation of the serial data sampling setup and hold times by sources other than the deserializer. The deserializer sampling uncertainty is accounted for and does not need to be subtracted from RSKM. The main outside contributors of jitter and skew that subtract from RSKM are interconnect intersymbol interference, serializer pulse position uncertainty, and pair-to-pair path skew.
VCCO Output Supply and Power Dissipation
The outputs have a separate supply (VCCO) for interfacing to systems with 1.8V to 5V nominal input logic levels. The DC Electrical Characteristics table gives the maximum supply current for VCCO = 3.6V with 8pF load at several switching frequencies with all outputs switching in the worst-case switching pattern. The approximate incremental supply current for VCCO other than 3.6V with the same 8pF load and worst-case pattern can be calculated using: II = CTVI 0.5FC x 21 (data outputs) + CTVIFC x 1 (clock output)..... where: II = incremental supply current CT = total internal (CINT) and external (CL) load capacitance VI = incremental supply voltage FC = output clock switching frequency The incremental current is added to (for VCCO > 3.6V) or subtracted from (for VCCO < 3.6V) the DC Electrical Characteristics table maximum supply current. The internal output buffer capacitance is CINT = 6pF. The worst-case pattern switching frequency of the data outputs is half the switching frequency of the output clock.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input signals separated to prevent crosstalk. A four-layer PC board with separate layers for power, ground, LVDS inputs, and digital signals is recommended.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard specifies ESD tolerance for electronic systems. The IEC 61000-4-2 model (Figure 14) specifies a 150pF capacitor that is discharged into the device through a 330 resistor. The MAX9210/MAX9212/MAX9214/MAX9216 LVDS inputs are rated for IEC 61000-4-2 level 4 (8kV contact discharge and 15kV air discharge). IEC 61000-4-2 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. The HBM (Figure 15) specifies a 100pF capacitor that is discharged into the device through a 1.5k resistor. All pins are rated for 2kV HBM.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to GND. DCB/NC is not 5V tolerant. The input voltage range for DCB/NC is nominally ground to V CC . Normally, DCB/NC is tied to VCC or ground.
R1 50 TO 100 CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 150pF
R2 330k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
R1 1M CHARGE-CURRENT LIMIT RESISTOR CS 100pF
R2 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit 12
Figure 15. Human Body ESD Test Circuit
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Programmable DC-Balance 21-Bit Deserializers
In the following example, the incremental supply current is calculated for VCCO = 5.5V, FC = 34MHz, and CL = 8pF: VI = 5.5V - 3.6V = 1.9V CT = CINT + CL = 6pF + 8pF = 14pF where: II = CTVI 0.5FC x 21 (data outputs) + CTVIF x 1 (clock output) II = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x 34MHz) II = 9.5mA + 0.9mA = 10.4mA The maximum supply current in DC-balanced mode for VCC = VCCO = 3.6V at F = 34MHz is 106mA (from the DC Electrical Characteristics table). Add 10.4mA to get the total approximate maximum supply current at VCCO = 5.5V and VCC = 3.6V. If the output supply voltage is less than VCCO = 3.6V, the reduced supply current can be calculated using the same formula and method. At high switching frequency, high supply voltage, and high capacitive loading, power dissipation can exceed the package power dissipation rating. Do not exceed the maximum package power dissipation rating. See the Absolute Maximum Ratings for maximum package power dissipation capacity and temperature derating.
RxIN0+ RxIN0LVDS DATA RECEIVER 1 RxIN1+ RxIN1LVDS DATA RECEIVER 2 RxIN2+ RxIN2LVDS CLOCK RECEIVER RxCLK IN+ RxCLK INDCB/NC PWRDWN 7X/9X PLL REFERENCE CLOCK GENERATOR STROBE STROBE STROBE
Functional Diagram
LVDS DATA RECEIVER 0 DATA CHANNEL 0 SERIAL-TOPARALLEL CONVERTER DATA CHANNEL 1 SERIAL-TOPARALLEL CONVERTER DATA CHANNEL 2 SERIAL-TOPARALLEL CONVERTER RxOUT14-20 RxOUT7-13 RxOUT0-6
MAX9210/MAX9212/MAX9214/MAX9216
RxCLK OUT
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13
Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
Pin Configurations
TOP VIEW
RxOUT17 1 RxOUT18 2 GND 3 RxOUT19 4 RxOUT20 5 DCB/NC 6 LVDS GND 7 RxIN0- 8 RxIN0+ 9 RxIN1- 10 RxIN1+ 11 LVDS VCC 12 LVDS GND 13 RxIN2- 14 RxIN2+ RxCLK INRxCLK IN+ 15 16 17
48 47 46 45 44 43 42 41
VCCO RxOUT16 RxOUT15 RxOUT14 GND RxOUT20 RxOUT19 GND RxOUT18 RxOUT17 VCCO RxOUT16 RxOUT15 RxOUT14 GND
39 38
VCC RxOUT12 RxOUT11 RxOUT10 GND RxOUT9 VCCO RxOUT8 RxOUT7 RxOUT6 GND RxOUT5 LVDS GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS VCC LVDS GND RxIN2RxIN2+ RxCLK INRxCLK IN+ LVDS GND
1 2 3 4 5 6 7 8 9 10 11 12
48
DCB/NC
RxOUT13
47
46
45
44
43
42
41
40
MAX9210 MAX9212 MAX9214 MAX9216
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
37 36 35 34 33 32 31 30 29 28 27 26 25
RxOUT13
VCC RxOUT12 RxOUT11 RxOUT10 GND RxOUT9 VCCO RxOUT8 RxOUT7 RxOUT6 GND RxOUT5
MAX9210 MAX9212 MAX9214 MAX9216
EXPOSED PAD
LVDS GND 18 PLL GND 19
13
14
15
16
17
18
19
20
21
22
23
RxOUT4 RxOUT3 VCCO RxOUT2 RxOUT1 GND
PLL VCC
PLL GND PWRDWN RxCLK OUT RxOUT0 GND
RxOUT1 RxOUT2
PLL VCC 20 PLL GND 21
PWRDWN 22 RxCLK OUT 23
PLL GND
QFN
RxOUT0 24
TSSOP
Chip Information
MAX9210 TRANSISTOR COUNT: 10,248 MAX9212 TRANSISTOR COUNT: 10,248 MAX9214 TRANSISTOR COUNT: 10,248 MAX9216 TRANSISTOR COUNT: 10,248 PROCESS: CMOS
14
______________________________________________________________________________________
VCCO RxOUT3 RxOUT4
24
Programmable DC-Balance 21-Bit Deserializers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
48L TSSOP.EPS
E H
MAX9210/MAX9212/MAX9214/MAX9216
321
N
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
b A1 A2 e D
SEATING PLANE
;
A
C L
c b
SIDE VIEW
END VIEW
WITH PLATING
b1
(;
)
PARTING LINE BASE METAL
c1
c
0.25
DETAIL A
SECTION C-C
NOTES: 1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE. 3. CONTROLLING DIMENSION: MILLIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED. 5. "N" REFERS TO NUMBER OF LEADS. 6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 48L TSSOP, 6.1mm BODY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0155
1 2
A
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15
Programmable DC-Balance 21-Bit Deserializers MAX9210/MAX9212/MAX9214/MAX9216
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
D2 D D/2 k
C L
b D2/2
E/2 E2/2 (NE-1) X e
C L
E
E2
k L DETAIL A e (ND-1) X e
C L
C L
L
L
e
e
A1
A2
A
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
1 2
B
16
______________________________________________________________________________________
32, 44, 48L QFN .EPS
Programmable DC-Balance 21-Bit Deserializers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
MAX9210/MAX9212/MAX9214/MAX9216
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED. TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 32, 44, 48L QFN THIN, 7x7x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
2 2
B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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