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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
March 2001
LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
General Description
The LM2633 is a feature-rich IC that combines three regulator controllers - two current mode synchronous buck regulator controllers and a linear regulator controller. The two switching regulator controllers operate 180 out of phase. This feature reduces the input ripple RMS current, resulting in a smaller input filter. The first switching controller (Channel 1) features an Intel mobile CPU compatible precision 5-bit digital-to-analog converter which programs the output voltage from 0.925V to 2.00V. It is also compatible with the dynamic VID requirements. The second switching controller (Channel 2) is adjustable between 1.25V to 6.0V. Use of synchronous rectification and pulse-skip operation at light load achieves high efficiency over a wide load range. Fixed-frequency operation can be obtained by disabling the pulse-skip mode. Current-mode feedback control assures excellent line and load regulation and a wide loop bandwidth for good response to fast load transient events. Current mode control is achieved through sensing the Vds of the top FET and thus an external sense resistor is not necessary. A power good signal is available to indicate the general health of the output voltages. A unique feature is the analog soft-start for the switching controllers is independent of the slew rate of the input voltage. This will make the soft start behavior more predictable and controllable. An internal 5V rail is available externally for boot-strap circuitry (only) when no 5V is available from other sources. Current limit for either of the two switching channels is achieved through sensing the top FET VDS and the value is adjustable. The two switching controllers have under-voltage and over-voltage latch protections, and the linear regulator has under-voltage latch protection. Under-voltage latch can be disabled or delayed by a programmable amount of time. The input voltage for the switching channels ranges from 5V to 30V, which makes possible the choice of different battery chemistries and options.
Features
GENERAL n Three regulated output voltages n 4.5V to 30V input range n Power good function n Input under-voltage lockout n Thermal shutdown n Tiny TSSOP package SWITCHING SECTION n Two channels operating 180 out of phase n Separate on/off control for each channel n Current mode control without sense resistor n Skip-mode operation available n Adjustable cycle-by-cycle current limit n Negative current limit n Analog soft start independent of input voltage slew rate n Power ground pins separate n Output UVP and OVP n Programmable output UVP delay n 250kHz switching frequency (for Vin < 17V) n Channel 1 output from 0.925V to 2.00V n 1.5% DAC accuracy from 0C to 125C n 1.5% initial tolerance for Channel 2 n Dynamic VID change ready n Power good flags VID changes n Channel 2 output from 1.3V to 6.0V LINEAR SECTION n Output voltage adjustable n 50mA maximum driving current n Output UVP n 2% initial tolerance
Applications
n Power supply for CPUs of notebook PCs that require the SpeedStepTM technique n Power supply for information appliances n General low voltage DC/DC buck regulators
SpeedStepTM is a trademark of Intel Corporation.
(c) 2001 National Semiconductor Corporation
DS200008
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LM2633
Connection Diagram
TOP VIEW
PGOOD (Pin 13): : A constant monitor on the output voltages. It indicates the general health of the regulators. For more information, see Power Good Truth Table (Table 2) and Power Good Function in Operation Descriptions. GND (Pin 16-17): Low-noise analog ground. G3 (Pin 18): Connect to the base or gate of the linear regulator pass transistor. OUT3 (Pin 19): Connect to the output of the linear regulator. FB3 (Pin 21): The feedback input for the linear regulator, connected to the center of the external resistor divider. COMP2 (Pin 22): Channel 2 compensation network connection (it's the output of the voltage error amplifier). FB2 (Pin 23): The feedback input for Channel 2. Connect to the center of the output resistor divider. SENSE2 (Pin 24): Remote sense pin of Channel 2. This pin is used for skip-mode operation. ILIM2 (Pin 25): Current limit threshold setting for Channel 2. It sinks at a constant 10 A current. A resistor is connected between this pin and the top MOSFET drain. The voltage across this resistor is compared with the VDS of the top MOSFET to determine if an over-current condition has occurred in Channel 2. KS2 (Pin 27): The Kelvin sense for the drain of the top MOSFET of Channel 2. SW2 (Pin 29): Switch-node connection for Channel 2, which is connected to the source of the top MOSFET. HDRV2 (Pin 30): Top gate-drive output for Channel 2. HDRV2 is a floating drive output that rides on SW2 voltage. CBOOT2 (Pin 31): Bootstrap capacitor connection for Channel 2 top gate drive. It is the positive supply rail for Channel 2 top gate drive. VDD2 (Pin 32): The supply rail for Channel 2 bottom gate drive. LDRV2 (Pin 33): Bottom gate-drive output for Channel 2. PGND2 (Pin 34): Power ground for Channel 2. VIN (Pin 35): The regulator input voltage supply. VLIN5 (Pin 36): The output of the internal 5V linear regulator. Bypass to the ground with a 1UF ceramic capacitor. When regulator input voltage is 5V, this pin can be tied to VIN pin to improve light-load efficiency. PGND1 (Pin 38-39): Power ground for Channel 1. LDRV1 (Pin 40-41): Bottom gate-drive output for Channel 1. VDD1 (Pin 42): The supply rail for the Channel 1 bottom gate drive. CBOOT1 (Pin 43): Bootstrap capacitor connection for Channel 1 top gate drive. It is the positive supply rail for Channel 1 top gate drive. HDRV1 (Pin 44): Top gate-drive output for Channel 1. HDRV1 is a floating drive output that rides on SW1 voltage. SW1 (Pin 45): Switch-node connection for Channel 1, which is connected to the source of the top MOSFET. KS1 (Pin 46): The Kelvin sense for the drain of the top MOSFET of Channel 1. ILIM1 (Pin 48): Current limit threshold setting for Channel 1. It sinks at a constant 10 A current. A resistor is connected between this pin and the top MOSFET drain. The voltage across this resistor is compared with the VDS of the top MOSFET to determine if an over-current condition has occurred in Channel 1.
20000801
48-Lead TSSOP (MTD) Order Number LM2633MTD See NS Package Number MTD48
Pin Descriptions
FB1 (Pin 1):The feedback input for Channel 1. Connect to the load directly. COMP1 (Pin 2): Channel 1 compensation network connection (connected to the output of the voltage error amplifier). NC (Pins 3, 14, 15, 20, 26, 28, 37 and 47): No internal connection. ON/SS1 (Pin 4): Adding a capacitor to this pin provides a soft-start feature which minimizes inrush current and output voltage overshoot; A lower than 0.8V input (open-collector type) at this pin turns off Channel 1; also if both ON/SS1 and ON/SS2 pins are below 0.8V, the whole IC goes into shut down mode. ON/SS2 (Pin 5): Adding a capacitor to this pin provides a soft-start feature which minimizes inrush current and output voltage overshoot; A lower than 0.8V input (open-collector type) at this pin turns off Channel 2; also if both ON/SS1 and ON/SS2 pins are below 0.8V, the whole IC goes into shut down mode. VID4-0 (Pins 6-10): Voltage identification code. Each pin has an internal pull-up. They can accept open collector compatible 5-bit binary code from the CPU. The code table is shown in Table 3. UV_ DELAY (Pin 11): A capacitor from this pin to ground adjusts the delay for the output under-voltage lockout. FPWM (Pin 12): When FPWM is low, pulse-skip mode operation at light load is disabled. The regulator is forced to operate in constant frequency mode.
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Block Diagram
LM2633
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LM2633
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20000803
Block Diagram
(Continued)
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LM2633
TABLE 1. Shut Down Latch Truth Table Input ovp1 1 1 1 1 1 =1 All other combinations
Note 1: '=1' means at least one variable is high. Note 2: 'Fault' is the logic OR of UVLO and thermal shutdown. Note 3: 'Cap' means the pin has a capacitor of appropriate value between it and ground. Note 4: Positive logic is used. Note 5: For meanings of the variables, refer to the block diagrams. Note 6: A blank value means 'don't care'.
Output ch2 on fault 0 0 0 1 0 0 =1 1 1 cap cap cap ssto1 ssto2 uv_delay latch off 1 1 1 1 1 0
ovp2
uvp1
uvp2
uvplr
new vid 0 0
ch1 on
=1 =1 1
TABLE 2. Power Good Truth Table Input ovp1 1 1 1 1 1 1 =0 1 1 All other combinations
Note 7: = 0 means at least one variable is low. Note 8: Positive logic is used. Note 9: A blank value means 'don't care'. Note 10: For meanings of the variables, refer to the block diagrams.
Output ch1 on ch2 on fault latch off PGOOD 0 0 0 0 0 0 0 0 0 1
ovp2
uvpg1
uvpg2
uvpglr
new vid
TABLE 3. VID Code and DAC Output VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DAC Voltage (V) No CPU*
0.925
0.950 0.975 1.000 1.025 1.050 1.075
1.100
1.125 1.150 1.175 1.200 1.225
5
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LM2633
TABLE 3. VID Code and DAC Output (Continued) VID4 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DAC Voltage (V) 1.250 1.275 No CPU
1.30 1.35 1.40
1.45
1.50 1.55 1.60
1.65 1.70 1.75 1.80 1.85 1.90 1.95
2.00
*This code is set to 0.900V for convenience.
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LM2633
Absolute Maximum Ratings
(Note 11)
ESD Rating (Note 14) Ambient Storage Temperature Range
2kV -65C to +150C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltages from the indicated pins to GND/PGND: VIN, KS1, KS2, SW1, SW2 ILIM1, ILIM2 VID0-VID4 VLIN, VDD1, VDD2, PGOOD FB1, FB2, SENSE2, G3, FB3, OUT3 CBOOT1 CBOOT2 ON/SS1, ON/SS2 FPWM Power Dissipation (TA = 25C), (Note 12) Junction Temperature -0.3V to 31V -0.3V to 31V -0.3V to 5V -0.3V to 6V -0.3V to 6V -0.3V to SW1+ 7V -0.3V to SW2+ 7V -0.3V to 5V -0.3V to 7V 1.56W +150C
Soldering Dwell Time, Temperature (Note 13) Wave 4 sec, 260C Infrared 10sec, 240C Vapor Phase 75sec, 219C
Operating Ratings(Note 11)
VIN (VIN and VLIN5 tied together) VIN (VIN and VLIN5 separate) Junction Temperature 1 Junction Temperature 2 VDD1, VDD2 4.5V to 5.5V 5.0V to 30V 0C to +125C -40C to +125C 4.5V to 5.5V
Electrical Characteristics
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over 0C to +125C. Symbol SYSTEM Vout1_load Vout2_load Vfb Ivin Channel 1 Load Regulation (Note 17) Channel 2 Load Regulation (Note 17) Line Regulation (for the two switching regulators) Input Supply Current with the Switching Channels ON Input Supply Current with the IC Shut Down VLIN5 Output Voltage Currentr Limit Comparator Offset ILIM1 and ILIM2 Pins Sink Current Negative Current Limit (SWx vs PGNDx voltage) Soft Start Charge Current Soft Start Sink Current Soft Start ON Threshold Soft Start Timeout Threshold UV_DELAY Threshold UV_DELAY Source Current (Note 20) VLIN5 = 5V (Note 21) 1.0 In UVLO or thermal shutdown 0.5 8 VCOMP1 moves from 0.5V to 1.5V, VID4:0=01101 VCOMP2 moves from 0.5V to 1.5V 5.0V VIN 30V, VID4:0=01101 VFB = 0.9V, no VLIN5 DC Current (Note 18) VON/SS1 = VON/SS2 = 0V (Note 19) IVLIN5 = 0 to 25mA, 5.5V < VIN < 30V 4.7 0 1.5 2 mV mV mV Parameter Conditions Min Typ Max Units
1.5
2.4
mA
Ivin_sd Vvlin5 Vcl Iilim_pos Vilim_neg
10 5.0 tbd 10
18 5.3
A V mV
12
A
45
mV
Iss_sc Iss_sk Vss_on Vssto Vuvd Idelay
2.25 2 1.2 3.5 2.1 5
4
A A V V V
9.0
A
7
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LM2633
Electrical Characteristics
Symbol SYSTEM Ivid Vuvlo_thr VID4:0 Internal Pull Up Current VIN Under-voltage Lockout (UVLO) Threshold VIN UVLO Hysteresis Channel 1 VOUT Under-voltage Shutdown Latch Threshold (Measured at the FB1) Channels 2 and 3 VOUT Undervoltage Shutdown Latch Threshold (Measured at the FB2 and FB3) VOUT Overvoltage Shutdown Latch Threshold for Channel 1 (Measured at the FB1) VOUT Overvoltage Shutdown Latch Threshold for Channel 2 (Measured at the FB2) VOUT Low Regulation Comparator Enable Threshold for Channels 1 and 2 Hysteresis of Low Regulation Comparator Regulator Window Detector Thresholds (PGOOD from High to Low) Regulator Window Detector Thresholds (PGOOD from Low to High) CBOOT Leakage Current HDRV1 Source Current HDRV1 Sink Current LDRV1 Source Current LDRV1 Sink Current HDRV1 High-Side FET On-Resistance LDRV1 High-Side FET On-Resistance Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over 0C to +125C. Conditions Min Typ Max Units
6 Rising Edge 4.2 300 VID4:0 = 01100 73 80
13
A
4.5
V mV
Vuvlo_hys Vuvp1
83
%VOUT
Vuvp2, 3
VID4:0 = 01100 76 80 86 %VOUT
Vovp1
110
114
119
%VOUT
Vovp2
109
112
115
%VOUT
Vlreg_thr
91.5
%VOUT
Vlreg_hys Vpwrbad
7 85 (Note 22) 110 88
%VOUT
%VOUT 112 119
Vpwrgd
90
93
97
%VOUT
Gate Drive (For Channel 1 Switching Regulator Controller) Iboot1 VCBOOT1 = 7V VHDRV1 = VSW1 =0V, VCBOOT1 = 5V VHDRV1 = 5V VLDRV1 = 0V VLDRV1 = 5V 100 1.3 tbd 1.2 3 1.84 tbd nA A A A A
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LM2633
Electrical Characteristics
Symbol SYSTEM LDRV1 Low-Side FET On-Resistance Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over 0C to +125C. Conditions Min Typ Max Units
0.5
Gate Drive (For Channel 2 Switching Regulator Controller) Iboot2 CBOOT Leakage Current HDRV2 Source Current HDRV2 Sink Current LDRV2 Source Current LDRV2 Sink Current HDRV2 FET On-Resistance LDRV2 FET On-Resistance Oscillator Fosc Toff_min Ton_min Ifb1 Ifb2 Ifb3 Icomp1, Icomp2 Vcomp_max Gm Vdac Oscillator Frequency Minimum Off-Time Minimum On-Time Feedback Input Bias Current, Channel 1 Feedback Input Bias Current, Channel 2 Feedback Input Bias Current, Channel 3 COMP Output Sink Current COMP Pin Maximum Voltage Transconductance Channel 1 DAC Output Voltage Accuracy VCOMP1 = 1V, DAC codes from 1.3V to 1.6V VCOMP1 = 1V, DAC codes from 0.925V to 1.25V and from 1.65V to 2.00V Vfb2 Channel 2 DC Output Voltage Accuracy Channel 3 DC Output Voltage Accuracy G3 Sink Current G3 Minimum Source Current G3 Maximum Voltage COMP2 pin from 0.5V to 1.8V VFB1 = 2.4V VFB2 = 1.36V VFB3 = 1.36V VFB1 = 150% of measured 1.4V DAC, VFB2 = 150% of measured bandgap, VCOMP1 = VCOMP2 = 1V tbd 225 250 400 220 275 kHz ns ns VCBOOT2 = 7V VHDRV2 = VSW2 =0V, VCBOOT2 = 5V VHDRV2 = 5V VLDRV2 = 0V VLDRV2 = 5V 100 tbd tbd tbd tbd tbd tbd nA A A A A
Error Amplifier 55 18 70 A nA nA
60
A
1.96 576
V mho
DAC Output and VFB2 -1.5 1.5 % -1.7 1.7
1.217
1.238
1.259
V
Linear Regulator Controller Vfb3 Vg3_sk Ig3_sc Vg3_max 1.215 1.24 20 20 3.6 1.265 V A mA V
Logic Inputs and Outputs
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LM2633
Electrical Characteristics
Symbol SYSTEM Vih Minimum High Level Input Voltage (FPWM, VID0-VID4) Maximum Low Level Input Voltage (FPWM, ON/SS1, ON/SS2, VID0-VID4) PGOOD Output High Current PGOOD Output Low Voltage Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over 0C to +125C. Conditions Min Typ Max Units
2.0
V
Vil
0.8
V
Ioh_pg Vol_pg
PGOOD = 5.7V (Note 23) PGOOD Sinking 20 A
5 0.3
A V
Electrical Characteristics
VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over -40C to +125C. Symbol SYSTEM Vout1_load Vout2_load Vfb Ivin Channel 1 Load Regulation (Note 17) Channel 2 Load Regulation (Note 17) Line Regulation (for the two switching regulators) Input Supply Current with the Switching Channels ON Input Supply Current with the IC Shut Down VLIN5 Output Voltage Currentr Limit Comparator Offset ILIM1 and ILIM2 Pins Sink Current Negative Current Limit (SWx vs PGNDx voltage) Soft Start Charge Current Soft Start Sink Current Soft Start ON Threshold Soft Start Timeout Threshold UV_DELAY Threshold UV_DELAY Source Current VID4:0 Internal Pull Up Current (Note 20) VLIN5 = 5V (Note 21) 1.0 In UVLO or thermal shutdown 0.5 7 VCOMP1 moves from 0.5V to 1.5V, VID4:0=01101 VCOMP2 moves from 0.5V to 1.5V 5.0V VIN 30V, VID4:0=01101 VFB = 0.9V, no VLIN5 DC Current (Note 18) VON/SS1 = VON/SS2 = 0V (Note 19) IVLIN5 = 0 to 25mA, 5.5V < VIN < 30V 4.7 0 1.5 2 mV mV mV Parameter Conditions Min Typ Max Units
1.5
2.5
mA
Ivin_sd Vvlin5 Vcl Iilim_pos Vilim_neg
10 5.0 tbd 10
18 5.3
A V mV
13
A
45
mV
Iss_sc Iss_sk Vss_on Vssto Vuvd Idelay Ivid
2.25 2 1.2 3.5 2.1 5 6
4
A A V V V
9.0 13
A A
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LM2633
Electrical Characteristics
Symbol SYSTEM Vuvlo_thr VIN Under-voltage Lockout (UVLO) Threshold VIN UVLO Hysteresis Channel 1 VOUT Under-voltage Shutdown Latch Threshold (Measured at the FB1) Channels 2 and 3 VOUT Undervoltage Shutdown Latch Threshold (Measured at the FB2 and FB3) VOUT Overvoltage Shutdown Latch Threshold for Channel 1 (Measured at the FB1) VOUT Overvoltage Shutdown Latch Threshold for Channel 2 (Measured at the FB2) VOUT Low Regulation Comparator Enable Threshold for Channels 1 and 2 Hysteresis of Low Regulation Comparator Regulator Window Detector Thresholds (PGOOD from High to Low) Regulator Window Detector Thresholds (PGOOD from Low to High) CBOOT Leakage Current HDRV1 Source Current HDRV1 Sink Current LDRV1 Source Current LDRV1 Sink Current HDRV1 High-Side FET On-Resistance LDRV1 High-Side FET On-Resistance LDRV1 Low-Side FET On-Resistance Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over -40C to +125C. Conditions Rising Edge 4.2 300 VID4:0 = 01100 72 80 84 %VOUT 4.6 V mV Min Typ Max Units
Vuvlo_hys Vuvp1
Vuvp2, 3
VID4:0 = 01100 75 80 87 %VOUT
Vovp1
109
114
120
%VOUT
Vovp2
108
112
116
%VOUT
Vlreg_thr
91.5
%VOUT
Vlreg_hys Vpwrbad
7 84 (Note 22) 109 88
%VOUT
%VOUT 112 120
Vpwrgd
89
93
98
%VOUT
Gate Drive (For Channel 1 Switching Regulator Controller) Iboot1 VCBOOT1 = 7V VHDRV1 = VSW1 =0V, VCBOOT1 = 5V VHDRV1 = 5V VLDRV1 = 0V VLDRV1 = 5V 100 1.3 tbd 1.2 3 1.84 tbd 0.5 nA A A A A
Gate Drive (For Channel 2 Switching Regulator Controller)
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LM2633
Electrical Characteristics
Symbol SYSTEM Iboot2 CBOOT Leakage Current HDRV2 Source Current HDRV2 Sink Current LDRV2 Source Current LDRV2 Sink Current HDRV2 FET On-Resistance LDRV2 FET On-Resistance Oscillator Fosc Toff_min Ton_min Ifb1 Ifb2 Ifb3 Icomp1, Icomp2 Vcomp_max Gm Vdac Oscillator Frequency Minimum Off-Time Minimum On-Time Feedback Input Bias Current, Channel 1 Feedback Input Bias Current, Channel 2 Feedback Input Bias Current, Channel 3 COMP Output Sink Current COMP Pin Maximum Voltage Transconductance Channel 1 DAC Output Voltage Accuracy Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over -40C to +125C. Conditions VCBOOT2 = 7V VHDRV2 = VSW2 =0V, VCBOOT2 = 5V VHDRV2 = 5V VLDRV2 = 0V VLDRV2 = 5V Min Typ Max Units
100 tbd tbd tbd tbd tbd tbd
nA A A A A
225
250 400 220
275
kHz ns ns
Error Amplifier VFB1 = 2.4V VFB2 = 1.36V VFB3 = 1.36V VFB1 = 150% of measured 1.4V DAC, VFB2 = 150% of measured bandgap, VCOMP1 = VCOMP2 = 1V tbd 55 18 70 A nA nA
91
A
1.96 576
V mho
DAC Output and VFB2 VCOMP1 = 1V, DAC codes from 1.3V to 1.6V VCOMP1 = 1V, DAC codes from 0.925V to 1.25V and from 1.65V to 2.00V Vfb2 Channel 2 DC Output Voltage Accuracy Channel 3 DC Output Voltage Accuracy G3 Sink Current G3 Minimum Source Current G3 Maximum Voltage Minimum High Level Input Voltage (FPWM, VID0-VID4) COMP2 pin from 0.5V to 1.8V -2.0 2.0 % -2.2 2.2
1.212
1.238
1.264
V
Linear Regulator Controller Vfb3 Vg3_sk Ig3_sc Vg3_max Vih 1.209 1.24 20 20 3.6 1.271 V A mA V
Logic Inputs and Outputs 2.2 V
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LM2633
Electrical Characteristics
Symbol SYSTEM Vil Maximum Low Level Input Voltage (FPWM, ON/SS1, ON/SS2, VID0-VID4) PGOOD Output High Current PGOOD Output Low Voltage Parameter
(Continued) VCC = +15V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over -40C to +125C. Conditions Min Typ Max Units
0.7
V
Ioh_pg Vol_pg
PGOOD = 5.7V (Note 23) PGOOD Sinking 20 A
5 0.3
A V
Note 11: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table. Note 12: Maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/JA, where TJMAX is the maximum junction temperature, TA is the ambient temperature and JA is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150C, 25C, and 80C/W for TJMAX, TA, and JA respectively. A JA of 90C/W represents the worst-case condition of no heat sinking of the 48-pin TSSOP. Heat sinking allows the safe dissipation of more power. The Absolute Maximum power dissipation should be derated by 12.5mW per C above 25C ambient. The LM2633 actively limits its junction temperature to about 150C. Note 13: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation. Note 14: Except for ILIM1 and ILIM2 pins, which are 1.5kV. For testing purposes, ESD was applied using the human-body model, a 100pF capacitor discharged through a 1.5k resistor. Note 15: A typical is the center of characterization data taken with TA = TJ = 25C. Typical data are not guaranteed. Note 16: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 17: This test simulates heavy load condition by changing COMP pin voltage. Note 18: This parameter indicates how much current the LM2633 is drawing from the input supply when it is functioning but not driving external MOSFETs or a bipoloar transistor. Note 19: This parameter indicates how much current the LM2633 is drawing from the input supply when it is completely shut off. Note 20: When ON/SS1,2 pins are charged above this voltage, the under voltage protection feature is enabled. Note 21: Above this voltage, the under-voltage protection is enabled. Note 22: This is the same as over-voltage protection threshold. Note 23: This is the amount of current PGOOD sinks when PGOOD is high and is forced to the voltage indicated
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LM2633
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20000804
Typical Application
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LM2633
Operation Descriptions
General The LM2633 is a combination of three voltage regu-lator controllers. Among them, two are switching regulator controllers and one is a linear regulator controller. The two switching controllers, Channel 1 and Channel 2, operate 180 out of phase. They can be independently enabled and disabled. The linear controller, or Channel 3, cannot be disabled but can be left unused. Channel 1 output voltage is set by an internal DAC, which accepts a 5-bit VID code from pins 6 through 10. Channels 2 and 3 output voltages are adjusted with a voltage divider. Both switching channels are synchronous and em-ploy peak current mode control scheme. Protection features include over-voltage protection (Ch1 and 2), under-voltage protection (all channels), and positive and negative peak current limit (Ch1 and 2). UVP function can be delayed by an arbitrary amount of time. Input voltage to the switching regulators can range from 4.5V to 30V. The linear regulator typically takes a 3.3V input voltage and its output volt-age can go up to 3.8V. The power good function always monitors all three output voltages. Soft Start If the ON/SSx pin is connected to ground instead of to a capacitor, the corresponding channel is turned off and will not start up. Assume the ON/SSx pin is connected to a capacitor and the rest of the circuit is set up correctly. When the input voltage rises above the 4.2V threshold, the internal circuitry is powered on, the ON/SSx pin should be held at 1.1V, and a 2A current starts to charge the capacitor connected between the ON/SSx pin and ground. When the ON/SSx pin voltage exceeds 1.2V, the corresponding channel is turned on. A MIN_ON_TIME comparator generates the soft start PWM pulses. As the ON/SSx pin voltage ramps up, the duty cycle grows, causing the output voltage to ramp up. During this time, the error amplifier output voltage is clamped at 0.8V, and the duty cycle generated by the PWM comparator is ignored. When the corresponding output voltage exceeds 99% of the set target voltage, the mode of the channel transitions from soft start to operating. As a result, the high clamp at the output of the error amplifier is switched to 2V. Beyond this point, once the PWM pulses generated by the PWM comparator are wider than that generated by the MIN_ON_TIME comparator, the PWM comparator takes over and starts to regulate the output voltage. That is, peak current mode control now takes place. The speed at which the duty cycle grows depends on the capacitance of the soft start capacitor. The higher the capacitance, the slower the speed. However, that speed is independent of how fast the input voltage grows. That is because the ramp signal used to generate the soft start duty cycle has a peak value proportional to input voltage, making the product of duty cycle and input voltage a value that is independent of input voltage. This feature makes the soft start process more predictable and reliable because whether the input power supply goes through a soft start process or is applied abruptly does not affect the LM2633 soft start. During soft start, under-voltage protection is disabled. But over-voltage protection and current limit are in place. When the ON/SSx pin voltage exceeds 3.5V, a soft start time out signal (sstox) will be issued. This signal enables the under-voltage protection. See the Under-Voltage Protection section.
Shutdown Mode If both ON/SSx pins are pulled low, the IC will be in shut down mode. Both top gate-drives of the two switching channels are turned off while both bottom gate-drives remain on. The linear channel is also disabled. The same thing happens to the gate drives when the input voltage is below the UVLO threshold. Turning Off a Switching Channel A switching channel can be turned off by pulling its ON/SSx pin below about 1.1V. Upon detecting a low level on ON/SSx pin, the corresponding top gate-drive will be turned off and the bottom gate-drive will be turned on. In a high current application, it may be necessary to take special measures to make sure that the output voltage does not go too negative during shutdown. One of those measures is to add a Schottky diode in parallel with output capacitors. Another measure is to fine tune the power stage parameters such as inductance and capacitance values. Fault State Whenever the input voltage becomes too low (less than 3.9V), or the IC is too hot and enters thermal shut down mode, a 'fault' signal will be generated internally. This signal will discharge the capacitor connected between the ON/SSx pin and ground with 3mA of current until the pin reaches 1.1V. The switching channels will be turned off upon seeing this signal. In the fault state, OVP and UVP are disabled Force-PWM Mode This mode applies to both switching channels simultaneously. The force-PWM mode is activated by pulling the FPWM pin to logic low. In this mode, the top FET and the bottom FET gate signals are always complementary to each other. The 0-CROSSING / NEGATIVE CURRENT LIMIT comparator detects the negative current limit. In force-PWM mode, the regulator always operates in Continuous Conduction Mode (CCM) and its duty cycle (approximately VOUT / VIN is almost independent of load. The force-PWM mode is good for applications where fixed switching frequency is required. In force-PWM mode, the top FET has to be turned on for a minimum of 220ns each cycle. However, when the required duty cycle is less than the minimum value, the skip comparator will be activated and pulses will be skipped to maintain regulation. Skip Comparator Whenever the COMPx pin voltage goes below the 0.5V threshold, the PWM cycles will be 'skipped' until that voltage again exceeds the threshold. Pulse-Skip Mode This mode is activated by pulling the FPWM pin to a TTL-compatible logic high and applies to both switching channels simultaneously. In this mode, the 0-CROSSING / NEGATIVE CURRENT LIMIT comparator detects the bottom FET current. Once the bottom FET current flows from source to drain, the bottom FET will be turned off. This prevents negative inductor current. In force-PWM operation, the inductor current is allowed to go negative, so the regulator is always in Continuous Conduction Mode (CCM), no matter what the load is. In CCM, duty cycle is almost independent of the load, and is roughly Vout divided by VIN. In pulse-skip
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LM2633
Operation Descriptions
(Continued)
mode, the regulator enters Discontinuous Conduction Mode (DCM) under light load. Once the regulator enters DCM, its duty cycle droops as the load current decreases. The regulator operates in DCM PWM mode until its duty cycle falls below 85% of the CCM duty cycle, when the MIN_ON_TIME comparator takes over. It forces 85% CCM duty cycle which causes the output voltage to continuously rise and COMPx pin voltage (error amplifier output voltage) to continuously droop. When the COMPx pin voltage hits the 0.5V level, the CYCLE_SKIP comparator toggles, causing the present switching cycle to be 'skipped', i.e., both FETs remain off during the whole cycle. As long as the COMPx pin voltage is below 0.5V, no switching of the FETs will happen. As a result, the output voltage will droop, and the COMPx pin voltage will rise. When the COMPx pin goes above the 0.5V level, the CYCLE_SKIP comparator flips and allows a 85% CCM duty cycle pulse to happen. If the load current is so small that this single pulse is enough to bring output voltage up to such a level that the COMPx pin drops below 0.5V again, the pulse skipping will happen again. Otherwise it may take a number of consecutive pulses to bring the COMPx pin voltage down to 0.5V again. As the load current increases, it takes more and more consecutive pulses to discharge the COMPx voltage to 0.5V. When the load
current is so high that the duty cycle exceeds the 85% CCM duty cycle, then pulse-skipping disappears. In pulse-skip mode, the frequency of the switching pulses decreases as the load current decreases. The LM2633 needs to sense the output voltages directly in the pulse-skip mode operation. For Channel 1 this is realized through the FB1 pin. For Channel 2, it is realized by connecting SENSE2 pin to the output. The LM2633 pulse-skip mode helps the light load efficiency for two reasons. First, it does not turn on the bottom FET, this eliminates circulating energy and reduces gate drive power loss. Second, the top FET is only turned on when necessary, rather than every cycle, also reduces gate drive power loss. Current Sensing and Current Limiting Sensing of the inductor current for feedback control is accomplished through sensing the drain-source voltage of the top FET when it is turned on. There is a leading edge blanking circuitry that forces the top FET to be on for at least 160ns. Beyond this mini-mum on time, the output of the PWM comparator is used to turn off the top FET. The blanking circuitry is being used to blank out the noise associated with the turning on of the top FET. Current limit is implemented using the same Vds information. See Figure 1.
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FIGURE 1. Current Limit Method There is a 10mA current sink on the ILIMx pin. When an external resistor is connected between ILIMx pin and top FET drain, a DC voltage is established be-tween the two nodes. When the top FET is turned on, the voltage across the FET is proportional to the inductor current. If the inductor current is too high, SWx pin voltage will be lower than the ILIMx voltage, causing the comparator to toggle and thus the top FET will be turned off immediately. The comparator is disabled when the top FET is turned off and dur-ing the leading edge blanking time. Negative Current Limit The negative current limit is put in place to ensure that the inductor will not saturate during a negative current flow and cause excessive current to flow through the bottom FET. The negative current limit is realized through sensing the bottom FET Vds. An internal reference voltage is used to compare with the bottom FET Vds when it is on. Upon seeing too high a Vds, the bottom FET will be turned off. The negative current limit is activated in force PWM mode, or also in the case of Channel 1, whenever there is a dynamic VID change. Active Frequency Control As the input / output voltage differential increases, the on time of the top FET as regulated by the feed-back control circuitry may approach the minimum value, i.e. the blanking time. That will cause unst-ble operations such as pulse skipping and uneven duty cycles. To avoid such an issue, the LM2633 is designed in such a way that when input voltage rises above about 17V, the PWM frequency starts to droop. The on time of the top FET will remain roughly the same as input voltage increases and frequency droops, so that the duty cycle gets lower and lower. The main impact of this shift in PWM frequency is the inductor ripple current and output voltage ripple. Regulator design should take this into account.
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LM2633
Operation Descriptions
Shutdown Latch State
(Continued)
Power Good Function The power good function is a general indication of the health of the regulators. The function is realized through an internal MOSFET tied from the PGOOD pin to ground. Power good signal is asserted by turning off that MOSFET. The internal power good MOSFET will not be turned on unless at least one of the following occurs: 1. There is an output over voltage event in at least one of the switching channels. 2. The output voltage of any of the three channels is below the power good lower limit, regardless of ON/SSx pin voltage level. 3. Whenever Channel 1 is going through a dynamic VID change. 4. System is in the shut down mode. 5. System is in the fault state. 6. System is in the shut down latch state. Power good higher limit is the same as that of the OVP function. In cases 2 and 3 above, if the corresponding output voltage(s) recovers, PGOOD will be asserted again. But there is a built-in hysteresis. See Vpwrgd in the Electrical Characteristics table. The above information is also available in Power Good Truth Table. When the internal power good MOSFET is turned on, the PGOOD pin will be pulled to ground. When it is turned off, the PGOOD pin is floating (open-drain). The on resistance of the power good MOSFET is about 15k. Dynamic VID Change During normal operation, if Channel 1 sees a change in the VID pattern, a NEW VID signal will be issued. Upon seeing the NEW VID signal, power good will be deasserted, UVP and OVP of Channel 1 will be disabled temporarily, and Channel 1 goes through a special step to quickly ramp the output voltage to the new value. If the new output voltage is higher than the old voltage, Channel 1 will rely on the control loop to change the output voltage. If the new value is lower than the old one, the top FET is going to remain off while the bottom FET is going to remain on. This will cause the output capacitor to discharge through the inductor. The 0-CROSSING / NEGATIVE CURRENT LIMIT comparator will detect for negative over current, even if the LM2633 is in pulse-skip mode. When the negative current limit is reached, bottom FET will be turned off, forcing the inductor current to flow through the body diode of the top FET to the input supply. When next clock cycle comes, the bottom FET will be turned on again, and it will not be turned off until the negative current limit is reached again. During this process, if the output voltage goes below the new voltage, the NEW VID signal will be deasserted. At this time, power good function will be released, OVP and UVP will be enabled and the bottom FET will be turned off. The normal control loop takes over after the output voltage droops below the new DAC voltage. Internal 5V Supply The internal 5V supply is generated from the VIN voltage through an internal linear regulator. This 5V supply is mainly for internal circuitry use, but can also be used externally (through the VLIN5 pin) for convenience. A typical use of this 5V is supplying the bootstrap circuitry for top drivers and supplying the voltage needed by the bottom drivers (through the VDDx pins). But since this 5V is generated by a linear
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This state is typically caused by an output under voltage or over voltage event. In this state, both switching channels have their top FETs turned off, and their bottom FETs turned on. The linear channel is not affected unless the error event is caused by it. There are two methods to release the system from the latch state. One is to create a fault state (see the corresponding section) by either bringing down the input voltage to below 3.9V UVLO threshold and then bringing it back to above 4.2V, or somehow by causing the system to enter thermal shut down. Another method is to pull both ON/SSx pins below 1V and then release them. After the latch is released, the two switching chan-nels will go through the normal soft start process. The linear channel output voltage will not be affected unless the UVLO method is used to release the latch or unless the error event is caused by the linear channel. Over-voltage Protection This protection feature is implemented in the two switching channels and not the linear channel. Refer to Table 1. As long as there is at least one switching channel enabled, and the LM2633 is not in fault state, any over voltage event at any of the two switching channels' output will cause system to enter the shut down latch state. However, if the over voltage event happens only on Channel 1 after a dynamic VID change signal is issued and before the change completes, the system will not enter the shut down latch state. See the Dynamic VID Change section. Under-voltage Protection The UVP feature is implemented in all three channels. If the UV_DELAY pin is pulled to ground, then the under-voltage protection feature is disabled. Otherwise, if a capacitor is connected between the UV_DELAY pin and ground, the UVP is enabled. Assume UVP is enabled and the system is not in fault state. If a switching channel is enabled, and its soft start time out signal (sstox, see soft start section) is asserted, then an under voltage event at the output of that channel will cause the system to enter the shut down latch state. However, if the under voltage event happens only on Channel 1 after a dynamic VID change signal is issued and before the change completes, the system will not enter the shut down latch state. See the Dynamic VID Change section. For the linear channel, if there is at least one switching channel on, and at least one soft start time out signal has been issued, and if the system is not in fault state, then an under voltage event at the linear regulator output will cause the system to enter shut down latch state. When the system reacts on an under voltage event, a 5mA current will be charging the capacitor con-nected to the UV_DELAY pin and when its voltage exceeds 2.1V, the system immediately enters shut down latch state. For details, see the block diagram and Shut Down Latch Truth Table.
LM2633
Operation Descriptions
(Continued)
General
Designing a power supply involves many tradeoffs. A good design is usually a design that makes good tradeoffs. Today's synchronous buck regulators typically run at a 200kHz to 300kHz switching frequency. Beyond this range, switching loss becomes excessive, and below this range, inductor size becomes unnecessarily large. The LM2633 has a fixed operating frequency of 250kHz when VIN voltage is below about 17V, and has decreased frequency when VIN voltage exceeds 17V. See Active Frequency Control section. In a mobile CPU application, both the CPU core and the GTL bus exhibit large and fast load current swings. The load current slew rate during such a transient is usually well beyond the response speed of the regulator.To meet the regulation specification, special considerations should be given to the component selection. For example, the total combined ESR of the output capacitors must be lower than a certain value. Also because of the tight regulation specification, only a small budget can be assigned to ripple voltage, typically less than 20mV. It is found that starting from a given output voltage ripple will often result in fewer design iterations. The design procedures that follow are generally appropriate for both the CPU core and the GTL bus power supplies, although emphasis is placed on the former. When there is a difference between the two, it will be pointed out.
regulator, it may hurt the light load efficiency, especially when VIN voltage is high. So if there is a separate 5V available that is generated by a switching power supply, it may be a good idea to use that 5V to power the bootstrap circuitry and the VDDx pins for better efficiency and less thermal stress on the LM2633. In shut down mode, the VLIN5 pin will go to 5.5V. So it is recommended not to use this voltage for purposes other than the bootstrap circuitry and VDDx pins. When the power stage input voltage can be guaranteed to be within 4.5V to 5.5V, the VLIN5 pin can be tied to the VIN pin directly. In this mode, all 5V currents are directly coming from power stage input rail VIN and power loss due to the internal linear regulation is no longer an issue.
Design Procedures
CPU Core / GTL Bus Power Supply Nomenclature ESR - Equivalent Series Resistance. Loading transient - a load transient when the load current goes from minimum load to full load. Unloading transient - a load transient when the load current goes from full load to minimum load. Cmin - minimum allowed output capacitance. Cmax - maximum allowed output capacitance. D - duty cycle. f - switching frequency. Inlim - negative current limit level. Iilim - positive current limit (ILIM1)pin current. Iirrm - maximum input current ripple RMS value. Iload - load current. Irip - output inductor peak-to-peak ripple current.
Output Capacitor Selection
Type of output capacitors Different type of capacitors often have different combinations of capacitance and ESR. High-capacitance multi-layer ceramic capacitors (MLCs) have very low ESR, typically 12m, but also relatively low capacitance - up to 100F. Tantalum capacitors can have fairly low ESR, such as 18m, and pretty high capacitance - up to 1mF. Aluminum capacitors can have very high capacitance and fairly low ESR. OSCON capacitors can achieve ESR values that are even lower than those of MLCs' and with higher capacitance. Tutorial on load transient response Skip to the next subsection when a quick design is desired. The control loop of the LM2633 can be made fast enough so that when a worst-case load transient happens, duty cycle will saturate (meaning it jumps to either 0% or Dmax). If the control loop is fast enough, the worst situation for a load transient will be that the transient happens when the following three are also happening. One, present PWM pulse has just finished. Two, input voltage is the highest. Three, the load current goes from maximum down to minimum (referred to as an unloading transient). Figure 2 shows how inductor current changes during a worst-case load transient. The reasons are as follows. In a mobile CPU application, the input/output voltage differential, which is applied across the inductor during a loading transient, is higher than the output voltage, which is applied across the inductor during an unloading transient.
% - CPU core voltage regulation window. e% - LM2633 initial DAC tolerance.
Vc_s - maximum allowed CPU core voltage excursion during a load transient, as derived from CPU specifications. Ic_s - maximum load current change, as specified by the CPU manufacturer. Re - total combined ESR of output capacitors. Re_s - maximum allowed total combined ESR of the output capacitors, as derived from CPU load transient specifications. Rilim - current limit adjustment resistance. See current sensing and current limiting. tmax - maximum allowed dynamic VID transition time. tpeak - time for the CPU core voltage to reach its peak value during an unloading transient. Vin - input voltage to the switching regulators. Vn - nominal output voltage. Vold - nominal CPU core voltage before dynamic VID change. Vnew - nominal CPU core voltage after dynamic VID change. Vrip - peak-to-peak output ripple voltage. L - inductance of the output inductor.
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LM2633
Output Capacitor Selection
(Continued)
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FIGURE 4. Delta Output Voltage Components During a load transient, the delta output voltage Vc has two changing components. One is the delta voltage across the ESR (Vr), the other is the delta voltage caused by the gained charge (Vq). Both delta voltages change with time. For Vr, the equation is:
FIGURE 2. Worst-case Load Transient That means the inductor current changes slower during an unloading transient than during a loading transient. The slower the inductor current changes during a load transient, the higher output capacitance is needed. That is why an unloading transient is the worst case. If the load transient happens when the present PWM pulse has just finished, the inductor current will be the highest, which means highest initial charging current for the output capacitors. Finally, the higher the input voltage, the higher the inductor ripple current and the higher the initial charging current for the output capacitors.
(1) and for Vq, the equation is:
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(2) The total change in output voltage during such a load transient is: Vc = Vr + Vq (3) From Figure 4 it can be told that Vc will reach its peak value at some point in time and then it is going to decrease. The larger the output capacitance is, the earlier the peak will happen. If the capacitance is large enough, the peak will occur at the beginning of the transient. In other words, Vc will decrease monotonically after the transient happens. To find the peak position, let the derivative of Vc go to zero, and the result is:
FIGURE 3. Load Transient Spec. Violation Because the response speed of the regulator is slow compared to a typical CPU load transient, the regulator has to rely heavily on the output capacitors to handle the load transient. The initial overshoot or undershoot is caused by the ESR of the output capacitors. How the output voltage recovers after that initial excursion depends on how fast the output in-ductor current ramps and how large the output capacitance is. See Figure 3. If the total combined ESR of the output capacitors is not low enough, the initial output voltage excursion will violate the specification, see Vc1. If the ESR is low enough, but there is not enough output capacitance, output voltage will have too much an extra excursion and travel outside the specification window, before it returns to its nominal value, see Vc2.
(4) The target is to find the capacitance value that will yield, at tpeak, a Vc that equals Vc_s. By plugging tpeak expression into the VC expression and equating the latter to Vc_s, the following formula is obtained:
(5) Notice it is already assumed the total ESR is no greater than Re_s otherwise the term under the square root will be a negative value.
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LM2633
Output Capacitor Selection
(Continued) (8) Notice it is already assumed the total ESR is no greater than Re_s, otherwise the term under the square root will be a negative value. Example: Re = 6m, Vn = 1.35V, Vc_s = 72mV, Ic_s = 10A, L = 2H
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FIGURE 5. Re = Re_s vs Re < Re_s There are two scenarios when calculating the Cmin. See Figure 5. One is that Re is equal to Re_s so there is absolutely no room for Vq, which means tpeak = 0s. The other is that Re is smaller than Re_s so there is some room for Vq, which means tpeak is greater than zero. However, it is not necessary to differentiate between the two scenarios when figuring out the Cmin by above formula. Allowed transient voltage excursion The allowed output voltage excursion during a load transient is: Generally speaking, Cmin decreases with decreasing Re, Ic_s, and L, but with increasing Vn and Vc_s. Maximum capacitance calculation This subsection applies to Channel 1 / CPU core power supply only. If there is a need to change the CPU core voltage dynamically (see Dynamic VID Change), there will be a maximum output capacitance restriction. If the output capacitance is too large, it will take too much time for the CPU core voltage to ramp to the new value, violating the maximum transition time specification. The worst-case dynamic VID change is one that takes the largest step down at no load. The maximum capacitance as determined by the way LM2633 implements the VID change can be calculated as follows:
(6) Example: Vn = 1.35V, % = 7.5%, e = 1.4%, Vrip = 20mV
Since the ripple voltage is included in the calculation of Vc_s, the inductor ripple current should not be included in the worst-case load current excursion. That is, the worst-case load current excursion should be simply Ic_s. Maximum ESR calculation No matter how much capacitance there is, if the total combined ESR is not less than a certain value, the load transient requirement will not be met. The maximum allowed total combined ESR is:
(9) Example: tmax = 100s, Inlim = 20A, Vold = 1.6V, Vnew = 1.35V, Iload = 0.
Generally speaking, Cmax decreases with decreasing tmax, Inlim and Iload, but with increasing voltage step.
Output Inductor Selection
The size of the output inductor can be determined from the assigned output ripple voltage budget and the impedance of the output capacitors at switching frequency. The equation to determine the minimum inductance value is as follows:
(7) Example: Vc_s = 72mV, Ic_s = 10A. Then Re_s = 7.2m. Maximum ESR criterion can be used when the capacitance is high enough, otherwise more capacitors than the number determined by this criterion should be used. Minimum capacitance calculation In a CPU core or a GTL bus power supply, the minimum output capacitance is typically dictated by the load transient requirement. If there is not enough capacitance, the output voltage excursion will exceed the maximum allowed value even if the maximum ESR requirement is met. The worst-case load transient is an unloading transient that happens when the input voltage is the highest and when the present switching cycle has just finished. The corresponding minimum capacitance is calculated as follows:
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(10) where min(Vin_max, 17V) means the smaller of Vin_max and 17V. The reason this term is not simply Vin_max is that the switching frequency droops with increasing Vin when Vin is higher than 17V. See Active Frequency Control. In the above equation, Re is used in place of the impedance of the output capacitors. This is because in most cases, the impedance of the output capacitors at the switching frequency is very close to Re. In the case of ceramic capacitors, replace Re with the true impedance.
LM2633
Output Inductor Selection
(Continued)
Example 1: Vin_max = 21V, Vn = 1.6V, Vrip = 26mV, Re = 6m, f = 250kHz.
resistance. The less the on resistance, the less the power loss. The equation for the maximum allowed on resistance at room temperature for a given FET package, is:
Example 2: Vin_max = 18V, Vn = 1.35V, Vrip = 20mV, Re = 6m, f = 250kHz. (12) where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the maximum ambient temperature, Rja is the junction-to-ambient thermal resistance of the FET, and TC is the temperature coefficient of the on resistance which is typically 4000ppm/C. If the calculated on resistance is smaller than the lowest value available, multiple FETs can be used in parallel. If the design criterion is to use the highest Rds FET, then the Rds_max of a single FET can be increased due to reduced current. In the case of two FETs in parallel, multiply the calculated on resis-tance by 4 to obtain the on resistance for each FET. In the case of three FETs, that number is 9. Since efficiency is very important in a mobile PC, having the lowest on resistance is usually more important than fully utilizing the thermal capacity of the package. So it is probably better to find the lowest Rds FET first, and then determine how many are needed. Example: Tj_max = 100C, Ta_max = 60C, Rja = 60C/W, Vin_max = 21V, Vn = 1.6V, and Iload_max = 10A.
The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest CPU core voltages and their load transient requirements should be considered. If an inductance value larger than Lmin is selected, make sure the Cmin requirement is not violated. Priority should be given to parameters that are not flexible or more costly. For example, if there are very few types of capacitors to choose from, it may be a good idea to adjust the inductance value so that a requirement of 3.2 capacitors can be reduced to 3 capacitors. Inductor ripple current is often the criterion for selecting an output inductor. However, in the CPU core or GTL bus application, it is usually of less priority. That is partly because the stringent output ripple voltage requirement automatically limits the inductor ripple current level. It is nevertheless a good idea to double check the ripple current. The equation is:
(11) where min(Vin_max, 17V) means the smaller of Vin_max and 17V. What is more important is the ripple content, which is defined by Irip_max / Iload_max. Generally speaking, a ripple content of less than 50% is ok. Too high a ripple content will cause too much loss in the inductor. Example: Vin_max = 21V, Vn = 1.6V, f = 250kHz, L = 1.7H.
If the lowest on resistance FET has a Rds_max of 10m, then two can be used in parallel. The temperature rise on each FET will not go to Tj_max because each FET is now dissipating only half of the total power. Alternatively, two 22m FETs can be used in parallel, with each FET reaching Tj_max. This may lower the FET cost, but will double the power loss. Top FET Selection The top FET has two types of losses - the switching loss and the conduction loss. The switching loss mainly consists of the cross-over loss and the bottom diode reverse recovery loss. It is rather difficult to estimate the switching loss. A general starting point is to allot 60% of the top FET thermal capacity to switching loss. The best way to find out is still to test it on bench. The equation for calculating the on resistance of the top FET is thus:
If the maximum load current is 14A, then the ripple content is 4.3A / 14A = 30%. When choosing the inductor, the saturation current should be higher than the maximum peak inductor current. The RMS current rating should be higher than the maximum load current.
MOSFET Selection
Bottom FET Selection During normal operations, the bottom FET is turned on and off at almost zero voltage. So only conduction loss is present in the bottom FET. The bottom FET power loss peaks at the maximum input voltage and load current. The most important parameter when choosing the bottom FET is the on
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(13)
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LM2633
MOSFET Selection
(Continued)
where Tj_max is the maximum allowed junction temperature in the FET, Ta_max is the maximum ambient temperature, Rja is the junction-to-ambient thermal resistance of the FET, and TC is the temperature coefficient of the on resistance which is typically 4000ppm/C. Example: Tj_max = 100C, Ta_max = 60, Rja = 60C/W, Vin_min = 14V, Vn = 1.6V, and Iload_max = 10A.
ripple current seen by the input capacitors. That will help extend input capacitor life span and result in a more efficient system. In a mobile CPU application, both the CPU core and GTL bus voltages are rather low compared to the input voltage. The corresponding duty cycles are therefore less than 50%, which means there will be no over-lapping between the two channels' input current pulses. The equation for calculating the maximum total input ripple RMS current is therefore:
Since the switching loss usually increases with bigger FETs, choosing a top FET with a much smaller on resistance sometimes may not yield noticeable lower temperature rise and better efficiency.
(15) where I1 is maximum load current of Channel 1, I2 is the maximum load current of Channel 2, D1 is the duty cycle of Channel 1, and D2 is the duty cycle of Channel 2. Example: Iload_max_1 = 6.8A, Iload_max_2 = 2A, D1 = 0.09, and D2 = 0.1.
Current Limit Setting
What is actually monitored and limited is the peak drain-source voltage of the top FET. The equation for current limit resistor is as follows: Choose input capacitors that can handle 1.97A ripple RMS current at highest ambient temperature. The input capacitors should also meet the voltage rating requirement. In this case, a SANYO OSCON capacitor 25SP33M, or a Taiyo Yuden ceramic capacitor TMK325BJ475, will meet both requirements. Comparison: If the two channels are operating in phase, the ripple RMS value would be 2.52A. The equation for calculating ripple RMS current takes the same form as the one above but the meanings of the variables change. I1 is the sum of the maximum load currents, D1 is the small duty cycle of the two, D2 is the difference between the two duty cycles, and I2 is the maximum load current of the channel that has larger duty cycle.
(14) where Iload_lim is the desired load current limit level and Iilim_min is the minimum current sink level at the ILIM1 pin. This calculated Rilim value guarantees that the minimum current limit will not be less than Iload_lim. Example: Iload_lim = 16A, Irip_max = 4.3A, Rds_max = 18m, Tj_max = 100C, Iilim_min = 8A
Figure 6 shows how the reduction of input ripple RMS current brought by the 2-phase operation varies with load current ratio and duty cycles. From the plots, it can be seen that the benefit of the 2-phase operation tends to maximize when the two load currents tend to be equal. Another conclusion is that the ratio increases rapidly when one channel's duty cycle is catching up with the other channel's and then becomes almost flat when the former exceeds the latter. So the absolute optimal operating point in terms of input ripple is at D1 = D2 = 0.5 and Iload_max_1 = Iload_max_2, when the input ripple current is zero for 2-phase operation.
It is recommended that a 1% tolerant resistor be used and its resistance should not be lower than the calculated value.
Input Capacitor Selection
The fact that the two switching channels of the LM2633 are 180 out of phase will help reduce the RMS value of the
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LM2633
Input Capacitor Selection
(Continued)
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FIGURE 6. Input Ripple RMS Current Ratio: 2-phase vs. In-phase
Control Loop Design
Samll Signal Model The buck regulator small signal model is shown in Figure 7. The model is obtained by applying the current-controlled PWM switch derived by Vorperian and by omitting portions that are irrelevant in a buck topology.
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FIGURE 7. Small Signal Model of Buck Regulators In the model, the DC output conductance of the PWM switch is:
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LM2633
Control Loop Design
(Continued)
For a reasonable design, the output filter has large attenuations at large complex frequencies (i.e. large s values). At s values where 1/sC is smaller than Re, the transfer function can be re-written as: (16)
Where D' = 1-D (17) (30) Where (18) Se = Vm *f (19) (31)
(20) Rj = Rds * (21) Se is the correction ramp slope, Sn is the on-time slope of the current sense waveform, Vm is the peak-peak value of the correction ramp, f is the PWM frequency, Vin is input voltage, Ri is the transfer function from inductor current to ramp voltage, Rds is the top FET on resistance and r is the gain of the current sense amplifier. The coefficient of the first current source is:
(32) Since the denominator of the control-output transfer function is a third-order polynomial, and its coefficients are positive real numbers, the transfer function either has one real pole and two complex poles that are complex conjugates or has three real poles. Thus it can be approximately written in the following format:
(22) and the coefficient of the second current source is:
(33) Where
(23) The output capacitance of the PWM switch is: and
(34)
(24) The DC resistance of the FET switches and of the inductor is not included here because its value is usually much smaller than the load resistance. Control-Output Transfer Function The control voltage in a peak-current mode scheme such as that of the LM2633 is the current command. At any instant that voltage determines the level of the inductor current (from an average-model point of view). The control-output transfer function is obtained by letting the small signal component of the input voltage be zero (i.e. .). The expression for the control-output transfer function is:
(35) where
(36) and
(25) Where = LCsC(R + Re) = goLC(R + Re) + Cs(CRRe + L) = C(R + Re) + go(CRRe + L) + CsR = 1 + goR
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(37) The value of fp can be determined by comparing the denominators of Equation (21) and Equation (25). The result is:
(26) (27) (28) (29)
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(38)
LM2633
Control Loop Design
(Continued)
From the above expressions, it can be seen that the control-output transfer function has three poles and one zero. Of the three poles, one is a real pole (fp) that is located at low frequency, the other two are either complex conjugates that are located at half the switching frequency (fn), or are separated real poles, depending on the Q value. When Q value is less than 0.5, the two high frequency poles will become two real poles. From Equation (24) it can be told that Q will become negative when mc < 1/(2D'). A negative Q value means an unstable system because the control-output transfer function will have a right-half-plane pole.
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FIGURE 8. Example Control-Output Transfer Function Bode Plot Rj = 10m x 5 = 50m Se = 0.25V x 250kHz = 62.5mV/s It should be noted that load resistance only changes the low frequency gain. This is because the location of the low frequency pole changes with load. Frequency Compensation Design The general purpose to compensate the loop is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked for small-signal performance. Loop gain is equal to the product of control-output transfer function (or so-called 'plant') and the output-control transfer function (i.e. the compensation network transfer function). Different compensation schemes result in different trade-offs among static accuracy, transient response speed and degree of stability, etc. Generally speaking it is a good idea to have a loop gain slope that is -20dB/decade from a very low frequency to well beyond cross-over frequency. The cross-over frequency should not exceed one-fifth of the switching frequency, i.e. 50kHz in the case of LM2633. The higher the bandwidth, the potentially faster the load transient speed. However, if the duty cycle saturates during the load transient, then further increasing the small signal bandwidth will not help. In the context of CPU core or GTL bus power supply, a small-signal bandwidth of 20kHz to 30kHz should be sufficient if output capacitors are not just MLCs. Since the control-output transfer function usually has very limited low frequency gain (see Figure 8), it is a good idea to place a pole in the compensation at zero frequency, so that the low frequency gain especially the DC gain will be very large. A large DC gain means high DC regulation accuracy (i.e. DC voltage changes little with load or line variations). The rest of the compensation scheme depends highly on the plant shape. If a typical shape such a that shown in Figure 8 is assumed, then the following can be done to create a -20dB/decade roll-off of the loop gain. Place the first zero at fp, the second pole at fz, and the second zero at fn, then the resulting loop gain plot will be of -20dB/dec slope from zero frequency up to fn (half the switching frequency).
fn = 250kHz / 2 = 125kHz
The resulting gain plot is shown in Figure 8 as the asymptotic plot. The plots of the actual gain and phase as computed by Equation (25) are also shown.
Figure 9 shows the gain plot of such a two-pole two-zero (more accurately, a lag-lag) compensation network, where fz1, fz2 and fp2 are the first zero, second zero and second pole frequencies. The first pole fp1 is located at zero frequency.
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LM2633
Control Loop Design
VID4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VDAC (V) 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 NO CPU 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1. 075 1.050 1.025 1.000 0.975 0.95 0.925 0.900 R1 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 25k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k
(Continued)
TABLE 4. R1 and R2 Values vs. VID R2 17.1k 18.4k 17.4k 21.4k 19.3k 22.0k 22.1k 30.0k 24.5k 27.3k 26.0k 34.6k 29.3k 36.0k 36.4k 64.3k 23.2k 25.7k 24.5k 32.1k 27.5k 33.3k 33.6k 56.2k 39.6k 47.4k 43.4k 75.0k 53.7k 81.8k 83.7k r= R2/(R1+R2) 0.41 0.42 0.41 0.46
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0.43 0.47 0.47 0.55 0.49 0.52 0.51 0.58 0.54 0.59 0.59 0.72 0.65 0.67 0.66 0.72 0.69 0.73 0.73 0.82 0.76 0.79 0.78 0.86 0.81 0.87 0.87 1 (40) To determine the component values in Figure 10, the following equations can be used:
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FIGURE 9. 2-Pole 2-Zero (lag-lag) Network Asymptotic Gain Plot To achieve the gain shape in Figure 9, Zc in Figure 7 should take the form of two RC branches in parallel, as shown in Figure 10. In the scheme, C1 and R3 form the first zero fz1, C2 and R3 form the second pole fp2, and C2 and R4 form the second zero fz2.
FIGURE 10. Compensation Network The gain of the compensation network can be calculated as the following. If the ESR zero frequency fz is higher than the low frequency pole fp, then there should be a -20dB/decade section from fp to fz in the plant gain plot, such as shown in Figure 8. Find the frequency where this section (or the extension of this section) crosses 0dB by using the following equation: fc_o = M *fp (39) If the desired loop transfer function cross-over frequency is fc_c, then the gain of the compensation network at fp should be:
The signal path from output voltage to control voltage is the feedback path. It typically contains a voltage divider, an error amplifier and a compensation network. Those are shown In Figure 7 as R1, R2, the gm amplifier, and Zc. For Channel 1 of the LM2633, since an R-2R ladder network is used, R1 and R2 values change with the VID setting. For information regarding their values and ratios, refer to Table 4. For Channel 2, R1 and R2 are simply the external voltage divider resistors.
(41) where B is the desired gain at fz1, and gm is the transconductance of the error amplifier.
(42)
(43)
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LM2633
Control Loop Design
(Continued)
(44) Back to the example. Let B = K, fz1 = fp, fp2 = fz, fz2 = fn, then: fc_o = 5.1 x 310Hz = 1581Hz
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FIGURE 12. Example Loop Transfer Function The power stage component selection can be significantly different from the example values. Figure 13 shows how the two high frequency poles of a current-mode-control buck regulator change with the Q value.
The corresponding Bode plots of the compensation network and the loop transfer function are shown in Figure 11 and Figure 12 respectively.
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FIGURE 13. How Control Output Transfer Function Changes with Q Values When Q is higher than 0.5, there will be a double-pole at half the switching frequency fn. When Q is lower than 0.5, the double-pole is damped and becomes two separate poles. The lower the Q value is, the farther apart the two poles are. When Q is too low (such as Q = 0.05 or lower), one of the two high frequency poles may move well into the low frequency region. When Q is too high (such as Q = 5 or higher), there will be significant peaking at half the switching frequency and the phase will rapidly go to -180 near it. This typically results in a lower cross-over frequency so that the peaking in the loop gain is well below the 0dB line. Q is a function of duty cycle and the deepness of the ramp compensation (mc). See Equation (32). The larger the duty cycle, the higher the Q value. The deeper the ramp compensation, the lower the Q value. When the inductor current ramp is too much smaller than the compensation ramp, one of the two high frequency poles will move far into the low frequency region and form a double-pole with the existing low frequency pole fp. That makes a voltage-mode control. The ramp compensation becomes deeper when inductance is increased, or input voltage is decreased, or sense resistance is decreased. In the case of Channel 1 of LM2633, if L = 1 to 3H, Vin = 5 to 24V, Vo = 0.925 to 2V, Rds = 5 to 20m, the Q value will be between 0.65 and 0.2.
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FIGURE 11. Example Compensation Transfer Function It can be seen from Figure 12 that the crossover frequency is 20kHz, and the phase margin is about 84 degrees. One thing that should be pointed out is this Bode plot is only for the 0.4 load. That is, when load current is 4A. If load current is lower than 4A, the portion of the gain plot from fp to 310Hz will be -40dB/dec. If load current is higher than 4A, then the portion of the gain plot from 310Hz to fp will be flat. However, this usually does not have much effect on the cross-over frequency and phase margin because it happens at low frequencies.
LM2633
Control Loop Design
Audio Susceptibility
(Continued)
Audio susceptibility is the transfer function from input to output. In a typical power supply design, it is desirable to have as much attenuation in that transfer function as possible so that noise appearing at the input has little effect on the output. The open-loop audio susceptibility given by the model in Figure 7 is:
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(45) The closed-loop audio susceptibility is simply:
FIGURE 14. Example Audio Susceptibility Gain The open-loop and closed-loop audio susceptibility of the previous example is shown in Figure 14. It can be told, both from the model and from Equation (45), that open-loop gain of audio susceptibility is just a level shift of the loop gain. Closed-loop audio susceptibility starts to depart from its open-loop counterpart when frequency drops below the cross-over frequency.
(46) where H(s) is the compensation transfer function defined by:
PCB Layout Guidelines
(47) It can be seen from Equation (45) that if mc is equal to 1/(2D')+0.5, then the open-loop audio susceptibility is zero. Unfortunately, the transfer function is rather sensitive to the value of mc around the critical value and thus this phenomenon is of little value. It is extremely important to follow the guidelines below to ensure a clean and stable operation. 1. Use a four-layer PCB. 2. Keep the FETs as close to the IC as possible. 3. Keep the power components on the right side (pins 25 through 48) of the IC and small signal components on the left side. 4. Analog ground and power ground should be separate planes and should be connected at a single point. 5. The VDDx pin decoupling capacitor should be connected to the power ground plane. 6. Input ceramic capacitors should be placed very close to the FETs and their connections to the drain of the top FET and to the source of the bottom FET should be as short as possible and should not go through power plane or ground plane. 7. HDRVx, SWx traces should be as close to each other as possible to minimize noise emission. If these two traces are longer than 2 centimeters, they should be fairly wide, such as 50mil. 8. Keep KSx trace as short as possible. Otherwise, use a trace of 50mil or wider. 9. ILIMx trace should be kept away from noisy nodes such as the switch node. 10. It is preferable to have a shorter and wider FBx trace than a longer and narrower one. 11. VLIN5 pin decoupling capacitor should be connected to the local analog ground. 12. Compensation components should be placed close to the IC, within 1 to 2 centimeters. An example of the power stage layout is shown in Figure 15.
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LM2633
PCB Layout Guidelines
(Continued)
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FIGURE 15. PCB Layout Example
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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
Physical Dimensions
unless otherwise noted
inches (millimeters)
48-Lead TSSOP Package Order Number LM26333MTD NS Package Number MTD48
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