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User's Guide
SLLU091 - January 2006
ISO721EVM
1 2
Contents Introduction .......................................................................................... 1 EVM Setup and Operation ........................................................................ 3 List of Figures
1 2 3 4 5 6
The ISO721 and ISO721M Pinout................................................................ The ISO721 and ISO721M EVM Schematic .................................................... ISO721 and ISO721M EVM, Top ................................................................ ISO721 and ISO721M EVM, Bottom ............................................................ Basic EVM Operation .............................................................................. Typical Input and Output Waveforms ............................................................ List of Tables
2 2 3 3 4 4
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EVM Connections
..................................................................................
2
1
Introduction
This user's guide details the evaluation module (EVM) operation of the ISO721 and ISO721M digital isolators. The same EVM board is used for each device. Configuration requirements are presented as well as user optional I/O loads. This document is intended to aid designers with isolator parameter performance evaluation within a particular system.
1.1
Overview
The ISO721 and ISO721M digital isolators have a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, and then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 s, the input is assumed to be unpowered or not functional, and the fail-safe circuit drives the output to a logic-high state.
CAUTION
Note that although these devices provide galvanic isolation of up to 4000 V, this EVM cannot be used for isolation voltage testing. It is designed for the examination of device operating parameters only and will be damaged if high voltage (> 5.5 V) is applied anywhere in the circuit.
SLLU091 - January 2006
ISO721EVM
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Introduction
1.2
Functional Configuration of the ISO721 and ISO721M
The EVM is configured for the pinout displayed in Figure 1. The additional I/Os on the EVM are provided for future development.
ISO721 ISO721M
IN 2 VCC1 3 GND1 4
ISOLATION
VCC1 1
8 VCC2 7 GND2 6 OUT 5 GND2
Figure 1. The ISO721 and ISO721M Pinout The ISO721 has TTL input thresholds and a input noise filter that prevents transient pulses of up to 2 ns in duration from being passed to the output of the device. The ISO721M has a CMOS Vcc/2 input threshold and does not have the noise filter and the additional propagation delay. These features of the ISO721M also provide for a 0-Mbps to 150-Mbps signaling rate rather than the ISO721's 0-Mbps to 100-Mbps signaling rate.
1.3
EVM Signal Paths of the ISO721 and ISO721M Isolators
This multifunctional EVM is designed with signal paths shown in Figure 2 for the analysis of the ISO721 and ISO721M, as well as future isolator configurations.
V CC1 (Banana Jack P 1) V CC2 (Banana Jack P 2)
C2
C3
C4
C5
C6
C11
C10
C9
C8
C7
INPUT J3
SMA
0W
ISO 721 or ISO 721M 1
50 W
8
2 IN 7 6 3 OUT 4 5
0W
OUTPUT J2
SMA
GND 1 (Banana Jack P 3)
GND 2 (Banana Jack P 4)
Figure 2. The ISO721 and ISO721M EVM Schematic Table 1. EVM Connections
Connection J1 J2 J3 J4 P1 P2 P3 P4 VCC1 VCC2 GND1 GND2 Label Description SMA connector (unused) SMA connector to the output pin 6 SMA connector to the input pin 2 SMA connector (unused) Input power supply banana jack Output power supply banana jack Input power ground connection banana jack Output power ground connection banana jack
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ISO721EVM
SLLU091 - January 2006
www.ti.com
EVM Setup and Operation
Table 1. EVM Connections (continued)
Connection JMP1 JMP2 JMP3 JMP4 Label Description 3-pin jumper (unused) 3-pin jumper (unused) 3-pin jumper - VCC1, input, GND1 3-pin jumper (unused)
1.4
The EVM Configuration
The ISO721EVM configuration has an SMA connector J3 set up as the input to pin 2, the IN pin of the ISO721 in Figure 1 and Figure 2. A 0- input series resistor, R8, is located next to the J3 input connector, and a 50- R5 from the input to ground is located on the bottom of the board.
R8 IN
OUT
R4
Figure 3. ISO721 and ISO721M EVM, Top The output channel configuration of the ISO721EVM has the OUT pin (pin 6) of Figure 1 and Figure 2 connected to SMA connector J2 through a 0- series resistor R4.
R5
OUT
IN
Figure 4. ISO721 and ISO721M EVM, Bottom The 0603 footprint pads for R3, C12, and C13 are available on the bottom of the EVM for varied loading conditions if desired by a user.
2
EVM Setup and Operation
This section includes the setup and operation of the EVM for parameter performance evaluation. Typical waveforms are included.
SLLU091 - January 2006
ISO721EVM
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EVM Setup and Operation
2.1
Overview
The basic setup in Figure 5 has the two power supplies required to evaluate isolator performance with 3.3-V on one side and 5-V on the other. If both sides are to be evaluated at the same supply voltage, only one power supply is required and can be used to power both sides of the EVM.
CAUTION
Note that this EVM is for operating parameter performance evaluation only and not designed for isolation voltage testing. Any voltage applied above the 5.5-V maximum recommended operating voltage of the ISO721 will damage the EVM.
Power Supply
Power Supply
Tektronix HFS9009 Pattern Generator
P1 J3
P3
P2
P4
Tektronix 784D Scope J2 OUTPUT
Vcc 1 GND 1 INPUT
Vcc 2 GND 2
Figure 5. Basic EVM Operation The input to the EVM is a 20-MHz pulse displayed on channel 1 in Figure 6. The output of the EVM is channel 2.
Figure 6. Typical Input and Output Waveforms
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ISO721EVM
SLLU091 - January 2006
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