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Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
FEATURES
* 1 differential LVDS output pair designed to meet or exceed the requirements of ANSI TIA/EIA-644, 1 differential feedback output pair * Differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Output frequency range: 31.25MHz to 700MHz * Input frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 * Cycle-to-cycle jitter: 30ps (maximum) * Output skew: 35ps (maximum) * Static phase offset: 25ps 125ps * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8745B-21 is a highly versatile 1:1 LVDS Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8745B-21 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clock. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
ICS
BLOCK DIAGRAM
PLL_SEL
/1, /2, /4, /8, /16, /32, /64
PIN ASSIGNMENT
0 1 Q nQ QFB nQFB CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q nQ VDDO
CLK nCLK
PLL
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
FB_IN nFB_IN
ICS8745B-21
20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View
SEL0 SEL1 SEL2 SEL3 MR
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7, 11 8, 9 10, 14 12, 13 15 16 17 18 19 20 Name CLK nCLK MR nFB_IN FB_IN SEL 2 VDDO GND nQ, Q SEL 3 VDDA PLL_SEL VDD SEL0 SEL1 Input Input Input Input Input Input Power Power Output Input Power Input Power Input Input Pullup Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pullup Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Output supply pins. Differential feedback outputs. LVDS interface levels. Power supply ground. Differential clock outputs. LVDS interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Analog supply pin. Selects between the PLL and reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. Core supply pin.
nQFB, QFB Output
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Outputs PLL_SEL = 1 PLL Enable Mode Q , nQ /1 /1 /1 /1 /2 /2 /2 /4 /4 /8 x2 x2 x2 x4 x4 x8
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference Frequency Range (MHz)* 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 250 - 700 125 - 350 62.5 - 175 250 -700 125 - 350 250 - 700 125 - 350 62.5 - 175 31.25 - 87.5 62.5 - 175 31.25 - 87.5 31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
8745BM-21
SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Outputs PLL_SEL = 0 PLL Bypass Mode Q , nQ /4 /4 /4 /8 /8 /8 / 16 / 16 / 32 / 64 /2 /2 /4 /1 /2 /1
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Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5V 10mA 15mA 46.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 125 17 59 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH Input High Voltage Input Low Voltage Input High Current CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL CLK_SEL, MR, SEL0, SEL1, SEL2, SEL3 PLL_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP VCMR Input High Current Input Low Current CLK, FB_IN nCLK, nFB_IN CLK, FB_IN nCLK, nFB_IN Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 GND + 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum 320 1.05 Typical 440 0 1.2 Maximum 550 50 1.35 25 Units mV mV V mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter Input Frequency CLK, nCLK Test Conditions PLL_SEL = 1 PLL_SEL = 0 Minimum 31.25 Typical Maximum 700 700 Units MHz MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Static Phase Offset; NOTE 2, 5 Output Skew; NOTE 3, 5 Cycle-to-Cycle Jitter ; NOTE 5, 6 Phase Jitter ; NOTE 4, 5, 6 Output Duty Cycle PLL Lock Time 46 50 PLL_SEL = 0V, f 700MHz PLL_SEL = 3.3V 3.1 -100 3. 4 25 Test Conditions Minimum Typical Maximum 700 3. 7 150 35 30 52 54 1 70 0 Units MHz ns ps ps ps ps % ms ps
tsk(O) tsk(o) tjit(cc) tjit()
odc tL
tR / tF Output Rise/Fall Time; NOTE 7 200 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
3.3V
VDD
SCOPE
Qx
nCLK
3.3V5% Power Supply Float GND + -
LVDS
nQx
V
CLK
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLK CLK nFB_IN FB_IN
t(O)
VOH VOL VOH VOL
nQx Qx nQy Qy
tsk(o)
tjit(O) = t(O) -- t(O) mean = Phase Jitter t(O) mean = Static Phase Offset
(where t(O) is any random sample, and t(O) mean is the average of the sampled cycles measured on controlled edges)
PHASE JITTER
AND
STATIC PHASE OFFSET
OUTPUT SKEW
nQ, nQFB 80% Q, QFB
80% VOD
tcycle
n
tcycle n+1
Clock Outputs
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYLE-TO-CYCLE JITTER
8745BM-21
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. B MARCH 18, 2005
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ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
nCLK CLK nQ, nQFB Q, QFB
tPD
nQ, nQFB Q, QFB
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
VDD

DC Input
LVDS
out
out
VOS/ VOS
DC Input
LVDS
100
VOD/ VOD out
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 100 Ohm Differential Transmission Line Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8745B-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
8745BM-21
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
depend on the selected component types and the density of the P.C. board.
LAYOUT GUIDELINE
The schematic of the ICS8745B-21 layout example is shown in Figure 5A. The ICS8745B-21 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will
3.3V
(155.52 MHz)
Zo = 50 Ohm
U1 1 2 3 4 5 6 7 8 9 10 CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND SEL1 SEL0 VDDI PLL_SEL VDDA SEL3 GND Q nQ VDDO 20 19 18 17 16 15 14 13 12 11 SEL1 SEL0 VDD PLL_SEL VDDA SEL3 C1 0.1uF R7 10 C11 0.01u VDDO C16 10u VDD
Zo = 50 Ohm 3.3V PECL Driv er R8 50 R9 50 R2 100 R10 50 SEL2 VDDO
ICS8745B-21
SP = Space (i.e. not intstalled)
VDD
(77.76 MHz)
RU3 1K
RU4 1K
RU5 SP
RU6 1K
RU7 SP PLL_SEL SEL0 SEL1 SEL2 SEL3
+
Bypass capacitors located near the power pins
(U1-7)
VDDO
R4 100
(U1-11)
VDD=3.3V VDDO=3.3V
-
LVDS_input
C4 0.1uF RD3 SP RD4 SP RD5 1K RD6 SP RD7 1K
C2 0.1uF
Zo = 100 Ohm Dif f erential
SEL[3:0] = 0101, Divide by 2
FIGURE 5A. ICS8745B-21 LVDS ZERO DELAY BUFFER SCHEMATIC EXAMPLE
8745BM-21
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. * The 100 differential output traces should have equal length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The series termination resistors should be located as close to the driver pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the
U1 ICS8745B-21
GND VDDO
C1
VDD
C16
VDDA
C11
C4
VIA
R7
100 Ohm Differential Traces
C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS845B-21
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8745B-21 is: 2772
8745BM-21
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ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
20 LEAD SOIC
PACKAGE OUTLINE - M SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
8745BM-21
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REV. B MARCH 18, 2005
Integrated Circuit Systems, Inc.
ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8745BM-21 ICS8745BM-21T ICS8745BM-21LF ICS8745BM-21LFT Marking ICS8745BM-21 ICS8745BM-21 TBD TBD Package 20 Lead SOIC 20 Lead SOIC 20 Lead "Lead-Free" SOIC 20 Lead "Lead-Free" SOIC Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8745BM-21
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ICS8745B-21
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change LVDS DC Characteristics Table - modified VOS 0.90V min. to 1.05V min, 1.15V typical to 1.2V typical, and 1.4V max. to 1.35V max. Features Section - delete bullet, "Industrial temperature available upon request." Added Lead-Free bullet. Ordering Information Table -added Lead-Free par t number and note. Date 3/17/04 3/18/05
Rev B B
Table T4D
Page 5 1
T9
14
8745BM-21
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