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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FEATURES
* 4 differential LVDS outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 800MHz * Translates any single ended input signal to LVDS levels with resistor bias on nCLK input * Output skew: 40ps (maximum) * Part-to-part skew: 500ps (maximum) * Propagation delay: 2.6ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8543 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK OE GND VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3
CLK_SEL
ICS8543
20-Lead TSSOP 4.4mm x 6.5mm x 0.92mm body package G Package Top View
OE
8543BG
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Type Power Input Pullup Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects PCLK, nPCLK inputs. When LOW selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential clock input. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Output enable. Controls enabling and disabling of outputs Q0, nQ0 through Q3, nQ3. When logic HIGH, the outputs are active. When logic LOW, the outputs are in high impedance state. LVCMOS/ LVTTL interface levels. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 9, 13 2 Name GND CLK_EN
3 4 5 6 7 8 10, 18 11, 12 14, 15 16, 17 19, 20
CLK_SEL CLK nCLK PCLK nPCLK OE VDD nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0
Input Input Input Input Input Input Power Output Output Output Output
Pulldown Pulldown Pullup Pulldown Pullup Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Inputs Outputs CLK_SEL X 0 1 0 CLK, nCLK PCLK, nPCLK CLK, nCLK Selected Source Q0:Q3 Hi Z Disabled; Low Disabled; Low Enabled nQ0:nQ3 Hi Z Disabled; High Disabled; High Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
OE 0 1 1 1
CLK_EN X 0 0 1
1 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK, PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK, nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
8543BG
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ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL, OE CLK_EN, CLK_SEL, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL -150 -5 Test Conditions Minimum 2 Typical Maximum 3.765 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 1.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS VOH VOL Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current Output Voltage High Output Voltage Low 0.9 -10 -20 1 -3.5 -3.5 1.34 1.06 1.125 Test Conditions Minimum 200 Typical 280 0 1.25 5 Maximum 360 40 1.375 25 +10 +20 -5 -5 1.6 Units mV mV V mV A A mA mA V V
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA=0C TO 70C
Symbol fMAX t PD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 150 150 f 800MHz 1.7 Test Conditions Minimum Typical Maximum 800 2.6 40 500 350 350 55 Units MHz ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 45 50 All parameters measured at 500MHz. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V VDD
SCOPE
Qx
3.3V5% Power Supply Float GND + -
nCLK, nPCLK
LVDS
nQx
V
CLK, PCLK
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
DIFFERENTIAL INPUT LEVEL
nQx Qx
nQ0:nQ3
nQy
V
Q0:Q3
OD
Cross Points
Qy
tsk(o)
V
OS
GND
DIFFERENTIAL OUTPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
OUTPUT SKEW
80% Clock Outputs
tsk(pp)
80% VOD
20% tR tF
20%
PART-TO-PART SKEW
nQ0:nQ3 Q0:Q3
OUTPUT RISE/FALL TIME
nCLK, nPCLK
Pulse Width t
PERIOD
CLK, PCLK nQ0:nQ3 Q0:Q3
tPD
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8543BG
PROPAGATION DELAY
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
VDD
VDD
out
DC Input
LVDS
out
VOS/ VOS
DC Input
LVDS
100
VOD/ VOD out
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
VDD
out
IOZ DC Input
DC Input
out
3.3V5% POWER SUPPLY
+
Float GND
_
LVDS
IOZ
LVDS
out
out
HIGH IMPEDANCE LEAKAGE CURRENT SETUP
DIFFERENTIAL OUTPUT SHORT CIRCUIT SETUP
VDD out
IOS
DC Input
LVDS
IOSB out
LVDS
IOFF
OUTPUT SHORT CIRCUIT CURRENT SETUP
8543BG
POWER OFF LEAKAGE SETUP
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out
IOSD
VDD
Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8543BG
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8543BG
BY
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ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
3.3V
3.3V 3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 4F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver in-
3.3V
3.3V
LVDS_Driv er
+
R1 100
-
100 100 Ohm Differential Transmission Line Differiential Transmission Line
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8543 is: 636
8543BG
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
Symbol N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
8543BG
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Integrated Circuit Systems, Inc.
ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8543BG ICS8543BGT ICS8543BGLF ICS8543BGLFT Marking ICS8543BG ICS8543BG ICS8543BGLF ICS8543BGLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8543BG
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ICS8543
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
REVISION HISTORY SHEET Description of Change In the VOL row, 1.06 has been moved to the Typical column from the maximum column. Updated Figure 1, CLK_EN Timing Diagram. Updated Figure 1, CLK_EN Timing Diagram. Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL. Udated Parameter Measurment Information figures. AC Characteristics table - revised Output Frequency from 650MHz to 800MHz. Features - deleted bullet "Designed to meet or exceed the requirements of ANSI TIA/EIA-644". LVDS Table - changed VOD typical value from 350mV to 280mV. Pin Characteristics - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Added LVDS Driver Termination section. Updated format throughout data sheet. Pin Description table - added function description to the OE pin. Updated LVPECL CLock Input Interface section. Added Lead Free par t number to Ordering Information table. Date 9/18/01 10/17/01 11/2/01 5/6/02 6/5/02 9/19/02
Rev A A A A B C
Table T4E
Page 5 3 3 1 6-10 5 1 5 2 4 9 10 11 2 10 13
T5
T4E T2 D
12/31/03
D D
T1 T8
4/7/04 6/16/04
8543BG
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