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| PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION FEATURES * High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer * Single LVDS output * 4 selectable PCLK, nPCLK inputs with internal termination * PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz * Part-to-part skew: TBD * Propagation delay: 725ps (typical) * 2.5V operating supply * -40C to 85C ambient operating temperature GENERAL DESCRIPTION The ICS854057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz and is a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The PCLK, nPCLK pairs can accept most standard differential input levels. Internal termination is provided on each differential input pair. The ICS854057 operates using a 2.5V supply voltage. The fully differential architecture and low propagation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the internal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). ,&6 BLOCK DIAGRAM VT0 50 PCLK0 nPCLK0 VT1 50 PCLK1 nPCLK1 00 VT2 50 PCLK2 nPCLK2 VT3 50 PCLK3 nPCLK3 50 SEL1 SEL0 50 01 10 11 Q0 nQ0 50 50 PIN ASSIGNMENT VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PCLK3 VT3 nPCLK3 Q0 nQ0 PCLK2 VT2 nPCLK2 GND ICS854057 20-Lead TSSOP 4.40mm x 6.50mm x 0.90mm body package G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854057AG www.icst.com/products/hiperclocks.html REV. A JUNE 30, 2003 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION Type Power Input Input Input Input Input Input Input Input Power Input Input Input Output Input Input Input Pulldown Pulldown Description Positive supply pins. Non-inver ting LVPECL differential clock input. Termination input. For LVDS input, leave floating. 50 termination to VT0. Inver ting LVPECL differential clock input. 50 termination to VT0. Clock select input. LVCMOS / LVTTL interface levels. Clock select input. LVCMOS / LVTTL interface levels. Non-inver ting LVPECL differential clock input. Termination input. For LVDS input, leave floating. 50 termination to VT1. Inver ting LVPECL differential clock input. 50 termination to VT1. Power supply ground. Inver ting LVPECL differential clock input. 50 termination to VT2. Termination input. For LVDS input, leave floating. 50 termination to VT2. Non-inver ting LVPECL differential clock input. Differential output pairs. LVDS interface levels. Inver ting LVPECL differential clock input. 50 termination to VT3. Termination input. For LVDS input, leave floating. 50 termination to VT3. Non-inver ting LVPECL differential clock input. TABLE 1. PIN DESCRIPTIONS Number 1, 20 2 3 4 5 6 7 8 9 10, 11 12 13 14 15, 16 17 18 19 Name VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND nPCLK2 VT2 PCLK2 nQ0, Q0 nPCLK3 VT3 PCLK3 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLDOWN RT Parameter Input Capacitance Input Pulldown Resistor Input Termination Resistor 50 50 Test Conditions Minimum Typical Maximum TBD Units pF K TABLE 3. CONTROL INPUT FUNCTION TABLE Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Clock Out PCLK PCLK0, nPCLK0 PCLK1, nPCLK1 PCLK2, nPCLK2 PCLK3, nPCLK3 854057AG www.icst.com/products/hiperclocks.html 2 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION 4.6V -0.5V to VDD + 0.5 V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 55 Maximum 2.625 Units V mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current SEL0, SEL1 SEL0, SEL1 SEL0, SEL1 SEL0, SEL1 VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A TABLE 4C. DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol Parameter PCLK0, PCLK1, PCLK2, PCLK3 Test Conditions VDD = VIN = 2.625V Minimum Typical Maximum Units A A A A V V nPCLK0, nPCLK1, VDD = VIN = 2.625V nPCLK2, nPCLK3 PCLK0, PCLK1, VDD = 2.625V, VIN = 0V PCLK2, PCLK3 IIL Input Low Current nPCLK0, nPCLK1, VDD = 2.625V, VIN = 0V nPCLK2, nPCLK3 Peak-to-Peak Voltage 0.15 VPP Common Mode Input Voltage; VCMR GND + 1.2 NOTE 1, 2 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V. IIH Input High Current 854057AG www.icst.com/products/hiperclocks.html 3 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION Test Conditions Minimum 250 1.125 Typical 350 4 1.25 5 Maximum 450 35 1.375 25 Units mV mV V mV TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5%, TA = -40C TO 85C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle Isolation 20% to 80% Test Conditions Minimum Typical >2 725 TBD 160 50 Maximum Units GHz ps ps ps % dB tsk(pp) tR / tF odc muxISOLATION NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 854057AG www.icst.com/products/hiperclocks.html 4 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION PARAMETER MEASUREMENT INFORMATION 2.5V 5% VDD Qx 2.5V5% POWER SUPPLY + Float GND - SCOPE nPCLK0: nPCLK3 LVDS nQx nPCLK0: nPCLK3 V PP Cross Points V CMR GND 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Q0x nQy PART 2 Qy nQ0 Q0 Pulse Width t PERIOD tsk(pp) odc = t PW t PERIOD PART-TO-PART SKEW odc & tPERIOD nPCLK0: nPCLK3 PCLK0: PCLK3 nQ0 Q0 tPD 80% Clock Outputs 80% VOD 20% tR tF 20% PROPAGATION DELAY VDD out DC Input OUTPUT RISE/FALL TIME VDD out out VOS/ VOS out VOS SETUP 854057AG VOD SETUP www.icst.com/products/hiperclocks.html 5 REV. A JUNE 30, 2003 LVDS DC Input LVDS 100 VOD/ VOD PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION APPLICATION INFORMATION 2.5V LVDS DRIVER TERMINATION Figure 1 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 1. TYPICAL LVDS DRIVER TERMINATION 2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50W TERMINATION UNUSED INPUT HANDLING To prevent oscillation and to reduce noise, it is recommended to have pull up and pull down connect to true and compliment of the unused input as shown in Figure 2. 2.5V 2.5V R1 680 PCLK VT nPCLK R2 680 Receiver with Built-In 50 Ohm FIGURE 2. UNUSED INPUT HANDLING 854057AG www.icst.com/products/hiperclocks.html 6 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. PCLK/NPCLK INPUT WITH BUILT-IN 50W TERMINATION INTERFACE The PCLK /nPCLK with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS PCLK/nPCLK input with built-in 50 terminations 2.5V 2.5V 3.3V or 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm PCLK Zo = 50 Ohm PCLK VT nPCLK Zo = 50 Ohm LVDS VT nPCLK Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 Receiver With Built-In 50 Ohm FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT WITH BUILT-IN 50W DRIVEN BY AN LVDS DRIVER FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT WITH BUILT-IN 50W DRIVEN BY AN LVPECL DRIVER 2.5V 2.5V 2.5V 2.5V Zo = 50 Ohm PCLK Zo = 50 Ohm PCLK Zo = 50 Ohm VT nPCLK Zo = 50 Ohm VT nPCLK CML Receiver With Built-In 50 Ohm SSTL R1 50 R2 50 Receiver With Built-In 50 Ohm FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT WITH BUILT-IN 50W DRIVEN BY A CML DRIVER FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT WITH BUILT-IN 50W DRIVEN BY AN SSTL DRIVER 854057AG www.icst.com/products/hiperclocks.html 7 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. SCHEMATIC EXAMPLE Figure 4 shows a schematic example of the ICS854057. In this example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION used. The decoupling capacitors should be physically located near the power pin. VDD VDD LVDS VDD ICS854057 Zo = 50 R1 1K 1 2 3 4 5 6 7 8 9 10 U1 VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND VDD PCLK3 VT3 nPCLK3 Q0 nQ0 PCLK2 VT2 nPCLK2 GND 20 19 18 17 16 15 14 13 12 11 R2 680 R1 1K LVPECL Zo = 50 C1 0.1u C2 0.1u R6 18 (U1,1) VDD (U1,20) R4 680 VDD R1 680 R3 680 VDD Zo = 50 Zo = 50 R5 100 + VDD Zo = 50 LVDS Zo = 50 VDD=2.5V FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS854057-01 is: 346 854057AG www.icst.com/products/hiperclocks.html 8 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION PACKAGE OUTLINE - G SUFFIX TABLE 8. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum Reference Document: JEDEC Publication 95, MO-153 854057AG www.icst.com/products/hiperclocks.html 9 REV. A JUNE 30, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 74 per tube 2500 Temperature -40C to 85C -40C to 85C TABLE 9. ORDERING INFORMATION Part/Order Number ICS854057AG ICS854057AGT ICS854057AG ICS854057AG While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854057AG www.icst.com/products/hiperclocks.html 10 REV. A JUNE 30, 2003 |
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