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Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 4 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 650MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 1.4ns (maximum) * Additive phase jitter, RMS: 0.06ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free packages available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL Fanout HiPerClockSTM Buffer and a member of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS8533-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8533-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VCC Q1 nQ1 Q2 nQ2 VCC Q3 nQ3
CLK_SEL
ICS8533-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
8533AG-01
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REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Name VEE CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc VCC nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Input Input Input Unused Power Output Output Output Output Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. Pullup LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Inver ting differential LVPECL clock input. No connect. Positive supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
8533AG-01
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Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8533AG-01
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 50 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN CLK_SEL CLK_EN CLK_SEL VIN = VCC = 3.465V VIN = VCC = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VEE + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
8533AG-01
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nP CLK VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCC - 1.4 VCC - 2.0 1 VCC VCC - 1.0 VCC - 1.7 1.0 Minimum Typical Maximum 150 5 Units A A A A V V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL V PP VCMR VOH VOL Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time 650MHz 1.0 Test Conditions Minimum Typical Maximum 650 1.4 30 150 0.06 20% to 80% @ 50MHz 300 700 53 Units MHz ns ps ps ps ps %
t sk(o) t sk(pp) t jit
tR / tF
odc Output Duty Cycle 47 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Driving only one input clock.
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter
at 156.25MHz = 0.06ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
8533AG-01
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nPCLK, nCLK
LVPECL
VEE
nQx PCLK, CLK
V
PP
Cross Points
V
CMR
V EE
-1.3V 0.165
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy Qy
nPCLK, nCLK PCLK, CLK nQ0:nQ3 Q0:Q3
tsk(o)
tPD
OUTPUT SKEW
PROPAGATION DELAY
nQ0:nQ3 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q0:Q3
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
8533AG-01
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
Zo = 50 84 84
1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o
FIGURE 3A. LVPECL OUTPUT TERMINATION
8533AG-01
FIGURE 3B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
8533AG-01
BY
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REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
3.3V
3.3V 3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
R5 100
C2
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 5F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8533-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.294W * 66.6C/W = 89.6C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-01 is: 404
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MS-153
8533AG-01
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ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead "Lead Free/Annealed" TSSOP 20 lead "Lead Free/Annealed" TSSOP on Tape and Reel 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 72 per tube 2500 Temperature 0C to 70C 0C to70C 0C to 70C 0C to70C 0C to 70C 0C to70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8533AG-01 ICS8533AG-01T ICS8533AG-01LN ICS8533AG-01LNT ICS8533AG-01LF ICS8533AG-01LFT ICS8533AG-01 ICS8533AG-01 ICS8533A01LN ICS8533A01LN ICS8533A01LF ICS8533A01LF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8533AG-01
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15
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change VPP values changed from 0.1 Min. to 0.15 Min. VCMR values changed from 0.13 Min., 1.3 Max. to 1.5 Min, VCC Max. Deleted VIH and VIL rows. 5/22/01 tR values changed from 100 Min. to 300 Min, and added 700 Max. tF values changed from 100 Min., 600 Max. to 300 Min. to 700 Max. For tR and tF rows changed test conditions from 30% to 70% to 20% to 80%. tjit(cc) values changed 150 Max. to 0 Max. Deleted tS and tH rows. VPP values changed from 0.15 Min., 1.3 Max. to 0.3 Min., 1 Max. VCMR values changed from 1.5 Min., to VEE + 1.5 Min. VIH values changed from 3.765 Max. to VCC + 0.3 Max. Deleted tjit(cc) row. Revised Parameter Measurement diagrams. Updated Figure 1, CLK_EN Timing Diagram. Added Termination for LVPECL Outputs section. Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V 0.165V from VEE = -1.3V 0.135V. Added RMS Jitter to Features section. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Changed Outputs Absolute Maximum Rating. LVPECL Table - changed VSWING 0.85V max. to 1.0V max. AC Characteristics Table - added RMS jitter. Added Additive Phase Jitter Section. Updated LVPECL Output Termination diagrams. Added Differential Clock Input Interface. Added LVPECL Clock Input Interface. Updated format throughout data sheet. Added Lead Free Annealed par t number to Ordering Information table. Updated LVPECL Clock Input Interface section. Ordering Information Table - added Lead Free par t number. Date
Rev
Table 4C
Page 4
4D B 5
5 5
B B C C C C C
5 4D 4B 5
5 5 4 5 6, 7 3 8 6 1 2 4 5 5 6 8 9 10 15 10 15
6/4/01 6/28/01 10/15/01 10/18/01 11/1/01 5/28/02 10/03/02
T2 T4D T5
D
10/12/03
D D
T9 T9
2/9/04 6/17/04
8533AG-01
www.icst.com/products/hiperclocks.html
16
REV. D JUNE 17, 2004

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