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Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 9 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 50ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 2ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications.
BLOCK DIAGRAM
CLK_EN
PIN ASSIGNMENT
VCCO VCCO nQ0 nQ1 nQ2 Q0 Q1 Q2
D Q LE
32 31 30 29 28 27 26 25 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Vcco nQ8 Q8 nQ7 Q7 nQ6 Q6 Vcco
CLK nCLK PCLK nPCLK
0 1
24 23 22 21 20 19 18 17
VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 VCCO
CLK_SEL
ICS8531-01
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
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REV. C OCTOBER 15, 2004
Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description Core supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Output supply pins. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 17, 24, 25, 32 10, 11 12, 13 14, 15 18, 19 20, 21 22, 23 26, 27 28, 29 30, 31 Name VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN VCCO nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3 Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Input Input Input Input Input Power Input Power Output Output Output Output Output Output Output Output Output Pullup Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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REV. C OCTOBER 15, 2004
Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Sourced CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q8 Disabled; LOW Disabled; LOW Enabled nQ0:nQ8 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
nCLK, nPCLK CLK, PCLK
Disabled
Enabled
CLK_EN
nQ0:nQ8 Q0:Q8
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q8 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ8 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 80 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter CLK_EN, CLK_SEL CLK_EN, CLK_SEL Input High Current Input Low Current CLK_EN CLK_SEL CLK_EN CLK_SEL VCC = VIN = 3.465V VCC = VIN = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum 3.765 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode input voltage is defined as VIH.
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REV. C OCTOBER 15, 2004
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VCC = VIN = 3.465V VCC = VIN = 3.465V VIN = 0V, VCC = 3.465V VIN = 0V, VCC = 3.465V -5 -150 0.3 VEE + 1.5 VCCO - 1.4 VCCO - 2.0 1 VCC VCCO - 1.0 VCCO - 1.7 0.85 Minimum Typical Maximum 150 5 Units A A A A V V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP VCMR VOH VOL Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 250MHz 1 Test Conditions Minimum Typical Maximum 500 2 50 250 700 700 52 Units MHz ns ps ps ps ps %
t sk(o) t sk(pp)
tR tF
odc Output Duty Cycle 48 50 All parameters measured at 250MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V V CC
VCC, VCCO
Qx
SCOPE
LVPECL
nQx
nCLK, nPCLK V CLK, PCLK VEE
PP
Cross Points
V
CMR
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1 nQx Qx PART 2 nQy Qy
nQx Qx nQy Qy
tsk(o)
tsk(o)
OUTPUT SKEW
80% VSW I N G Clock Outputs 20% tR tF 20%
PART-TO-PART SKEW
nQ0:nQ8 80% Q0:Q8
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 Q0:Q4
tPD
PROPAGATION DELAY
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
LVPECL OUTPUTS
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
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FIGURE 3B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8531-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30.2mW = 271.8mW
Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 271.8mW = 549mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.549W * 42.1C/W = 93.1C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
32-PIN LQFP FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8531-01 is: 632
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FOR
PACKAGE OUTLINE
AND
DIMENSIONS - Y SUFFIX
32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Marking ICS8531AY-01 ICS8531AY-01 ICS8531AY01L ICS8531AY01L Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free" LQFP 32 Lead ""Lead-Free"" LQFP on Tape and Reel Count 250 per tray 1000 250 per tray 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8531AY-01 ICS8531AY-01T ICS8531AY-01LF ICS8531AY-01LFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8531AY-01
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ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Date
Rev
Table 4A 4C
Page 4 4
Separated LVCMOS rows into own table. Changed HSTL table to Differential table. Changed VPP value from 0.1 Min. to 0.15 Min. Changed VCMR values from 0.13 Min, 1.3 Max. to 0.5 Min, VCC - 0.85. In LVPECL table, changed VCMR values from 0.7 Min, 2.5 Max. to 0.5 Min, VCC - 0.85. Changed VOH values from 1.9 Min., 2.3 Max. to VCC - 1.4 Min., VCC - 1.0 Max. Changed VOL values from 1.2 Min, 1.6 Max. to VCC - 2.0 Min, VCC - 1.7 Max. Changed VSWING values from 0.55 Min. to 0.6 Min. Changed tpLH & tpHL rows to tPD. Values stayed same. tR and tF values changed from 100 Min, 600 Max. to 300 Min., 700 Max. Changed tDC row to odc. Values stayed same. Deleted tS and tH rows. Changed all VDDx to VCCx . Changed VCCO to equal 3.3V 5% from 1.8V 0.2V. Updated Block Diagram. Changed VCMR value from 0.5 Min. to VEE + 0.5 Min. Changed VPP values from 0.15 Min, 1.3 Max, to 03. Min, 1 Max. Changed VCMR values from 0.5 Min., VCC - 0.85 Max. to VEE + 1.5 Min., VCC Max. Udated Figure 1, CLK_EN Timing Diagram. Updated Figure 2, Output Load Test Circuit. Revised labels on figures. Added Termination for LVPECL Outputs section. Pin Description table - VCC description changed to "Core supply pin" from "Positive supply pin". Power Supply Characteristics table - VCC description changed to "Core Supply Voltage" from "Positive Supply Voltage". Output Load Test Circuit diagram - corrected VEE equation to read, VEE = -1.3V 0.165V from VEE = -1.3V 0.135V. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Updated Absolute Maximum Ratings. Power Supply DC Characteristics table - changed IEE 70mA max. to 80mA max and deleted 50mA typical. Updated LVPECL Output Termination drawings. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Power Considerations - corrected Power Dissipation from 70mA to 80mA to correspond with IEE. Updated format throughout the data sheet. Ordering Information Table - added Lead-Free par t number. 6/15/01
4D B
5
5
5
B 4C 4D
1 4 5 3 6 6, 7 8 2 4 5 T2 T4A 2 4 4 7 8 9 10
6/18/01
B
8/9/01
B B
11/1/01 5/28/02
B
10/02/02
C
2/2/04
C
T9
14
10/15/04
8531AY-01
www.icst.com/products/hiperclocks.html
15
REV. C OCTOBER 15, 2004

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