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Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FEATURES
* 4 differential HSTL compatible outputs * Selectable diffferential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 650MHz * Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 200ps (maximum) * Propagation delay: 1.6ns (maximum) * 3.3V core, 1.8V output operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8523 is a low skew, high performance 1-to-4 Differential-to-HSTL fanout buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8523 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3
PIN ASSIGNMENT
GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3
CLK_SEL
ICS8523
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View
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Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Type Power Input Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 Name GND CLK_EN
3 4 5 6 7 8, 9 10 11, 12 13, 18 14, 15 16, 17 19, 20
CLK_SEL CLK nCLK PCLK nPCLK nc VDD nQ3, Q3 VDDO nQ2, Q2 nQ1, Q1 nQ0, Q0
Input Input Input Input Input Unused Power Output Power Output Output Output
Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced Pullup high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK Pulldown inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Inver ting differential LVPECL clock input. No connect. Core supply pin. Differential output pair. HSTL interface levels. Output supply pins. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Pulldown Non-inver ting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q3 Disabled; LOW Disabled; LOW Enabled nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQ0:nQ3 Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Core Power Supply Voltage Output Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 50 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN CLK_SEL CLK_EN CLK_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol IIH IIL V PP Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX VSWING Output Crossover Voltage Test Conditions Minimum 0.9 0 40% x (VOH - VOL) + VOL 0.75 Typical Maximum 1.4 0.4 60% x (VOH - VOL) + VOL 1.25 Units V V V V
Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 650MHz 1.0 Test Conditions Minimum Typical Maximum 650 1.6 30 200 700 700 55 Units MHz ns ps ps ps ps %
t sk(o) t sk(pp)
tR tF
odc Output Duty Cycle 45 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.8V0.2V 3.3V5%
V DD
V DD VDDO
Qx
SCOPE
nCLK, nPCLK
V
PP
HSTL
CLK, PCLK
nQx
Cross Points
V
CMR
GND
GND = 0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
DIFFERENTIAL INPUT LEVEL
Qx PART 1 nQx Qy PART 2 nQy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
80% Clock Outputs
80% VSW I N G
nCLK, nPCLK CLK, PCLK nQ0:nQ3 Q0:Q3
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nQ0:nQ3 Q0:Q3
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
odc & tPERIOD
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REV. D SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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BY
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R3 125
R4 125
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 125 R2 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
R5 100
C2
3.3V 3.3V
3.3V
Zo = 50 Ohm
LVDS
C1
R4 120
R3 1K
R4 1K
PCLK
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
power pin. For ICS8523, the unused clock outputs can be left floating.
Zo = 50 +
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example of the ICS8523. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near the
Zo = 50 3.3V R12 1K U3 1.8V Zo = 50 Ohm 1 2 3 4 5 6 7 8 9 10 GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK NC NC VDD Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 20 19 18 17 16 15 14 13 12 11 1.8V Zo = 50 1.8V R4 50 R3 50 Zo = 50 R2 50 R1 50
-
+
-
Zo = 50 Ohm R11 1K LVHSTL Driver R9 50 R10 50 3.3V
C1 0.1u 8523 Zo = 50 + 1.8V Zo = 50 C2 0.1u C3 0.1u R6 50 R5 50 -
Zo = 50 +
Zo = 50 R8 50 R7 50
-
FIGURE 5. ICS8523 HSTL BUFFER SCHEMATIC EXAMPLE
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.6mW = 130.4mW
Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 130.4mW = 303.7mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.304W * 66.6C/W = 90.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 6.
VDDO
Q1
VOUT RL 50
FIGURE 6. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DDO_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (0.9V/50) * (2V - 0.9V) = 19.8mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
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REV. D SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8523 is: 472
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ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MS-153
8523BG
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Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Marking ICS8523BG ICS8523BG ICS8523BGLF ICS8523BGLF Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 Temperature 0C to 70C 0C to70C 0C to 70C 0C to70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8523BG ICS8523BGT ICS8523BGLF ICS8523BGLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8523BG
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REV. D SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8523
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change LVHSTL table. Added VSWING row to LVHSTL DC Characteristics Table. AC Characteristics table. tPD row, added value of 1.3 to Min.; changed Max. from 2.0 to 1.6. Updated Figure 1, CLK_EN Timing Diagram. Updated Figure 1, CLK_EN Timing Diagram. AC Characteristics table. tPD row, changed Min. from 1.3ns to 1.0ns. tsk(pp) row, changed Max. from 150ps to 200ps. Revised Features section, Bullet 1,6 - took out 1.8V In the Application Information section, added Schematic Examples. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. HSTL DC Characteristics Table - changed VOH 1V min. to 0.9V min. Power Considerations - changed Total Power Dissipation to reflect VOH change. Calculations changed due to new Total Power Dissipation. Changed LVHSTL to HSTL throughout data sheet. Features section - added Lead-Free bullet. Updated LVPECL Clock Input Interface section. Added Lead-Free marking to Ordering Information table. Date 7/31/01 10/17/01 11/2/01 1/11/02 5/6/02 10/25/02
Rev B B B C C C
Table T4D T5
Page 5 5 3
T5
3 5 1
T2 D T4D
8 - 10 2 4 5 11 - 12
6/20/03
D T9
1 9 15
9/13/04
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