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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
FEATURES
* 6 LVDS outputs * Crystal oscillator interface * Output frequency range: 75MHz to 150MHz * Crystal input frequency: 25MHz * Cycle-to-cycle jitter: 20ps (typical) * RMS phase jitter at 150MHz, using a 25MHz crystal (899.9KHz to 20MHz): TBD * Phase noise: TBD Offset Noise Power 100Hz ............... TBD 1KHz ............... TBD 10KHz ............... TBD 100KHz ............... TBD * 3.3V supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS84426 is a Crystal-to-LVDS Clock Synthesizer/Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO and output frequency can be programmed using the frequency select pins. The low jitter characteristics of the ICS84426 make it an ideal clock source for Serial Attached SCSI applications.
,&6
FUNCTION TABLE
Inputs MR 1 0 0 F_SEL X 0 1 Output Frequency F_OUT LOW 75MHz 150MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD F_SEL nc MR XTAL1 XTAL2 nc VDDA VDD PLL_SEL GND VDD
XTAL1
OSC
XTAL2
0 1
6 Output Divider
PLL
/ 6 /
Q0:Q5 nQ0:nQ5
Feedback Divider
ICS84426
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View
MR PLL_SEL F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84426BM
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Type Output Output Output Output Output Output Power Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Core supply pins. Power supply ground. Selects between the PLL and crystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Analog supply pin. No connect. Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active High Master Reset. When logic LOW, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 13, 16, 24 14 15 17 18, 22 19, 20 21 23 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 Q5, nQ5 VDD GND PLL_SEL VDDA nc XTAL2, XTAL1 MR F_SEL Input Power Unused Input Input Input Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
84426BM
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 50C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 242 19 Maximum 3.465 3.465 Units V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current PLL_SEL, MR, F_SEL PLL_SEL, MR, F_SEL MR PLL_SEL, F_SEL MR PLL_SEL, F_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.4 50 Test Conditions Minimum 250 Typical 400 Maximum 600 50 Units mV mV V mV
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Test Conditions Minimum Typical Fundamental 25 70 7 MHz pF Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT Output Frequency Cycle-to-Cycle Jitter ; NOTE 2 Period Jitter, RMS Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% Test Conditions Minimum 75 20 TBD 40 400 50 1 Typical Maximum 150 Units MHz ps ps ps ps % ms
tjit(cc) tjit(per) tsk(o)
tR / tF odc
tLOCK PLL Lock Time See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84426BM
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD out DC Input
Qx
3.3V5% POWER SUPPLY
SCOPE
LVDS
+ Float GND -
LVDS
nQx
out
VOS/ VOS
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD out
VOS / DVOS SETUP
nQx Qx
DC Input
LVDS
100
VOD/ VOD out
nQy Qy
tsk(o)
VOD / DVOD SETUP
OUTPUT SKEW
VOH
nQ0:nQ5 VREF Q0:Q5 VOL
tcycle
n
tcycle n+1
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
CYCLE-TO-CYCLE JITTER
nQ0:nQ5
PERIOD JITTER
80% 80% VO D
Q0:Q5
Pulse Width t
PERIOD
20% Clock Outputs t
R
t
F
odc =
t PW t PERIOD
odc & tPERIOD
84426BM
OUTPUT RISE/FALL TIME
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20%
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER APPLICATIONS INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84426 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10 F 24
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS84426 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL2 C1 18p X1 18pF Parallel Cry stal XTAL1 C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
put. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver in-
3.3V 3.3V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS84426. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL=1, therefore, the output frequency is 75MHz. It is recVDD
ommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible. For LVDS driver, the unused output pairs should be terminated with a 100 resistor across.
VDD R7 24 VDDA 22p C11 0.1u C16 10u C1 X1 25MHz,18pF C2 18p
R4 1K
VDD 13 14 15 16 17 18 19 20 21 22 23 24 R6 1K
U1 Zo = 50 VDD GND PLL_SEL VDD VDDA nc XTAL2 XTAL1 MR nc F_SEL VDD nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 + R1 100 Zo = 50 LVDS_input
-
R5 1K
ICS84426
(U1,13)
VDD
(U1,16) C5 0.1u
(U1,24) C3 0.1u
VDD=3.3V
C6 0.1u
FIGURE 4A. ICS84426 SCHEMATIC EXAMPLE
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
* The differential 50 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
POWER
AND
GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
C6
GND VCC
C1 R7
C5
Signals VIA
VDDA
C16 C11
X1
C2
C3
U1
ICS84426
Pin1
50 Ohm Traces
FIGURE 4B. PCB BOARD LAYOUT FOR ICS84426
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84426 is: 2804
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
84426BM
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REV. A ARPIL 2, 2003
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS84426
CRYSTAL-TO-LVDS SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER
Marking ICS84426BM ICS84426BM Package 24 Lead SOIC 24 Lead SOIC on Tape and Reel Count 30 per tube 1000 Temperature 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS84426BM ICS84426BMT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84426BM
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REV. A ARPIL 2, 2003

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