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ICS673-01
PLL BUILDING BLOCK
Description
The ICS673-01 is a low cost, high-performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (the ICS674-01), the user can customize the clock to lock to a wide variety of input frequencies. The ICS673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power-down feature which turns off the entire device. For applications that require low jitter or jitter attenuation, see the MK2069.
Features
* * * * * * * * * * * *
Packaged in 16-pin SOIC Available in Pb-free package Access to VCO input and feedback paths of PLL VCO operating range up to 120 MHz (5 V) Able to lock MHz range outputs to kHz range inputs through the use of external dividers Output Enable tri-states outputs Low skew output clocks Power-down turns off chip VCO predivide to feedback divider of 1 or 4 25 mA output drive capability at TTL levels Advanced, low power, sub-micron CMOS process Single supply +3.3 V (5%) or +5 V (10%) operating voltage
* Industrial temperature range available * Forms a complete PLL, using the ICS674-01 * For better jitter performance, use the MK1575
Block Diagram
VDD
2
CHCP VCOIN
VDD
Icp
Clock Input REFIN FBIN
UP
Phase/ Frequency Detector
CLK1 VCO 2 4
1 0
DOWN
MUX
2
CLK2
Icp
PD
(entire chip)
CAP
3
GND
SEL
OE (both
outputs)
External Feedback Divider (such as the ICS674-01)
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ICS673-01 PLL BUILDING BLOCK
Pin Assignment
F B IN VDD VDD GND GND GND CHGP V C O IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R E F IN NC C LK1 C LK2 PD SEL OE CAP
VCO Predivide Select Table SEL
0 1
VCO Predivide
4 1
0 = connect pin directly to ground 1 = connect pin directly to VDD
1 6 p in n a rro w (1 5 0 m il) S O IC
Pin Descriptions
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
FBIN VDD VDD GND GND GND CHGP VCOIN CAP OE SEL PD CLK2 CLK1 NC REFIN
Pin Type
Input Power Power Power Power Power Output Input Input Input Input Input Output Output Input
Pin Description
Feedback clock input. Connect the feedback clock to this pin. Triggered on falling edge. Connect to +3.3 V or +5 V and to VDD on pin 3. Connect to VDD on pin 2. Connect to ground. Connect to ground. Connect to ground. Charge pump output. Connect to VCOIN under normal operation. Input to internal VCO. Loop filter return. Output enable. Active when high. Tri-states both outputs when low. Internal weak pull-up resistor. Select pin for VCO predivide to feedback divider per table above. Internal weak pull-up resistor. Power down. Turns off entire chip when pin is low. Outputs stop low. Internal weak pull-up resistor. Clock output 2. Low skew divide by two version of CLK1. Clock output 1. No connect. Nothing is connected internally to this pin. Reference input. Connect reference clock to this pin. Triggered on falling edge.
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ICS673-01 PLL BUILDING BLOCK
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS673-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Industrial Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
0 +3.13
Typ.
Max.
+70 +5.50
Units
C V
DC Electrical Characteristics
VDD=3.3 V 5% or 5.0 V 10%, Ambient temperature -40 to +85C, unless stated otherwise.
Parameter
Operating Voltage Logic Input High Voltage Logic Input Low Voltage LF Input Voltage Range Output High Voltage Output Low Voltage Output High Voltage, CMOS level Operating Supply Current Short Circuit Current Input Capacitance
Symbol
VDD VIH VIL VI VOH VOL VOH IDD IOS CIN
Conditions
REFIN, FBIN, SEL REFIN, FBIN, SEL
Min.
3.13 2
Typ.
Max.
5.50
Units
V V
0.8 0 VDD 0.4 VDD-0.4 15 100 5
V V V V
IOH = -25 mA IOL = 25 mA IOH = -8 mA VDD = 5.0 V, No load, 40 MHz CLK SEL
2.4
mA mA pF
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AC Electrical Characteristics
VDD = 3.3 V 5%, Ambient Temperature -40 to +85C, CLOAD at CLK = 15 pF, unless stated otherwise.
Parameter
Output Clock Frequency (from pin CLK) Input Clock Frequency (into pins REFIN or FBIN) Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute peak-to-peak VCO Gain Charge Pump Current
Symbol
fCLK fREF tOR tOF tDC tJ KO Icp
Conditions
SEL = 1 SEL = 0
Min.
1 0.25 Note 1
Typ.
Max. Units
100 25 8 MHz MHz MHz ns ns % ps MHz/V A
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 40
1.2 0.75 50 250 190 2.5
2 1.5 60
VDD = 5.0 V 10%, Ambient Temperature -40 to +85C, CLOAD at CLK = 15 pF, unless stated otherwise.
Parameter
Output Clock Frequency (from pin CLK) Input Clock Frequency (into pins REFIN or FBIN) Output Rise Time Output Fall Time Output Clock Duty Cycle Jitter, Absolute peak-to-peak VCO Gain Charge Pump Current
Symbol
fCLK fREF tOR tOF tDC tJ KO Icp
Conditions
SEL = 1 SEL = 0
Min.
1 0.25 Note 1
Typ.
Max. Units
120 30 8 MHz MHz MHz ns ns % ps MHz/V A
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2 45
0.5 0.5 50 150 190 2.4
1 1 55
Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.
External Components
The ICS673-01 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01F should be connected between VDD and GND as close to the ICS673-01 as possible. A series termination resistor of 33 may be used at the clock output. Special considerations must be made in choosing loop components CS and CP. These can be found online at http://www.icst.com/products/telecom/loopfiltercap.htm
Avoiding PLL Lockup
In some applications, the ICS673-01 can "lock up" at the maximum VCO frequency. This is usually caused by power supply glitches or a very slow power supply ramp. This situation also occurs if the external divider starts to fail at high input frequencies. The usual failure mode of a divider circuit is that the output of the divider begins to miss clock edges. The phase detector interprets this as a too low output frequency and
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increases the VCO frequency. The feedback divider begins to miss even more clock edges and the VCO frequency is continually increased until it is running at its maximum frequency. Whether caused by power supply issues or by the external divider, the loop can only recover by powering down the circuit or asserting PD. The simplest way to avoid this problem is to use an external divider that always operates correctly regardless of the VCO speed. Figures 2 and 3 show that the VCO is capable of high speeds. By using the internal divide-by-four and/or the CLK2 output, the maximum VCO frequency can be divided by 2, 4, or 8 and a slower counter can be used. Using the ICS673 internal dividers in this manner does reduce the number of frequencies that can be exactly synthesized by forcing the total VCO divide to change in increments of 2, 4, or 8. If this lockup problem occurs, there are several solutions; three of which are described below. 1. If the system has a reset or power good signal, this should be applied to the PD pin, forcing the chip to stay powered down until the power supply voltage has stabilized. If the dividers are implemented in an FPGA or other circuit configured on power-up, it is critical keep the ICS673 powered down until the dividers are working properly. 2. If no power good signal is available, a simple power-on reset circuit can be attached to the PD pin, as shown in Figure 1. When the power supply ramps up, this circuit holds PD asserted (device powered down) until the capacitor charges.
VDD R1
I CS673- 01 PD
C3
A. Basi c Ci r cui t
VDD R1 D1
I CS673-01 PD
C3
B. Fast er Di scharge
Fi g 1 . Po we r o n Re s e t Ci r c u i t s
The circuit of Figure 1A is adequate in most cases, but the discharge rate of capacitor C3 when VDD goes low is limited by R1. As this discharge rate determines the minimum reset time, the circuit of Figure 1B may be used when a faster reset time is desired. The values of R1 and C3 should be selected to ensure that PD stays below 1.0 V until the power supply is stable. 3. A comparator circuit may be used to monitor the loop filter voltage as shown in Figure 2. This circuit will dump the charge off the loop filter by asserting PD if the VCO begins to run too fast and the PLL can recover. A good choice for the comparator is the National Semiconductor LMC7211BIM5X. It is low power, version of the small (SOT-23), low cost, and has high input impedance. The trigger voltage of the comparator is set by the voltage divider formed by R2 and R3. The voltage should be set to a value higher than the VCO input is expected to run during normal operation. Typically, this might be 0.5 V below VDD. Hysteresis should be added to the circuit by connecting R4.
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ICS673-01 PLL BUILDING BLOCK
Explanation of Operation
CHGP VCOIN CP R2 R3 R4 Figure 2. Using an External Comparator to Reset the VCO RS CS CAP PD
+
The ICS673-01 is a PLL building block circuit that includes an integrated VCO with a wide operating range. The device uses external PLL loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 kHz Hsync input. The phase/frequency detector compares the falling edges of the clocks inputted to FBIN and REFIN. It then generates an error signal to the charge pump, which produces a charge proportional to this error. The external loop filter integrates this charge, producing a voltage that then controls the frequency of the VCO. This process continues until the edges of FBIN are aligned with the edges of the REFIN clock, at which point the output frequency will be locked to the input frequency.
The CLK output frequency may be up to 2x the maximum Output Clock Frequency listed in the AC Electrical Characteristics above when the device is in an unlocked condition. Make sure that the external divider can operate up to this frequency.
Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.
+3.3 or 5 V CP
0.01 F
RS SEL OE PD
200 kHz
CS CAP CLK1 40 MHz 20 MHz
VDD
CHGP VCOIN
REFIN FBIN
ICS673-01
GND
CLK2
200 kHz
100
Digital Divider such as ICS674-01
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Determining the Loop Filter Values
The loop filter components consist of CS, CP, and RS. Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 20 MHz from a 200 kHz input. The phase locked loop may be approximately described by the following equations: R K I 2N 0.7
=
25, 000 190 10 2.5 10 C S --------------- ---------------------------------------------------------2 200
6
-6
and CS = 1.32 nF (1.2 nF is the nearest standard value). The capacitor CP is used to damp transients from the charge pump and should be approximately 1/20th the size of CS, i.e., C P C S 20 Therefore, CP = 60 pF (56 pF nearest standard value). To summarize, the loop filter components are: CS = 1.2 nf CP = 56 pf RS = 26 k
Bandwidth NBW
S O CP = ---------------------------
Damping factor,
R S K O I CP C S = ----- ---------------------------2 N
where: KO = VCO gain (Hz/V) Icp = Charge pump current (A) N = Total feedback divide from VCO, including the internal VCO post divider CS = Loop filter capacitor (Farads) RS = Loop filter resistor (Ohms) As a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e., BW ( REFIN ) 20 In this example, using the above equation, bandwidth should be less than or equal to 10 kHz. By setting the bandwith to 10kHz and using the first equation, RS can be determined since all other variables are known. In the example of Figure 1, N = 200, comprising the divide by 2 on the chip (VCO post divider) and the external divide by 100. Therefore, the bandwidth equation becomes: 10,000 R S 190 10 2.5 10 = ---------------------------------------------------------2 200
6 -6
Output Clock Alignment to REFIN
When choosing either CLK1 or CLK2 to drive the feedback divider, ICS recommends that CLK2 be used so that the falling edges of CLK2 and REFIN, and the rising edge of CLK1, are all synchronized. If CLK1 is used for feedback, CLK2 may be either a rising or falling edge when compared to REFIN. See diagrams below.
CLK1 CLK2 REFIN CLK2 Feedback
and RS = 26 k
CLK1
CLK2 REFIN
Choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes:
CLK1 Feedback
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ICS673-01 PLL BUILDING BLOCK
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
16
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
ICS673M-01I ICS673M-01IT ICS673M-01ILF ICS673M-01ILFT
Marking
ICS673M-01I ICS673M-01I 673M-01ILF 673M-01ILF
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC
Temperature
-40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Note: "LF" denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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