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CMM5114A
November 1995
Radiation Hardened, High Reliability, CMOS/SOS 1024 Word by 4-Bit LSI Static RAM
Pinouts
18 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T18 TOP VIEW
Features
* Radiation Hardened to 10K RAD (Si) * SEP Effective LET No Upsets: >100 MEV-cm2/mg * Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/ Bit-Day (Typ) * Dose Rate Survivability: >1 x 1012 RAD (Si)/s * Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse * Latch-Up Free Under Any Conditions * Fully Static Operation * Single Power Supply 4.5V to 6.5V * All Inputs and Outputs TTL Compatible * Three-State Outputs * Industry Standard 18 Pin Configuration * Low Standby and Operating Power * Common Data Inputs and Outputs * Gated Address Inputs by CE
A6 1 A5 2 A4 3 A3 4 A0 5 A1 6 A2 7 CE 8 VSS 9
18 VDD 17 A7 16 A8 15 A9 14 I/O1 13 I/O2 12 I/O3 11 I/O4 10 WE
Description
The CMM5114A is a high reliability 1024 word by 4-bit static random access memory using CMOS/SOS technology. It is designed for use in memory systems where low power and simplicity in use are desirable. TTL compatibility on all I/O terminals permits easy system integration. CMOS/SOS technology permits operation in radiation environments. It is insensitive to neutrons, cannot latch up at any dose rate and is resistance to single event upset caused by cosmic rays or heavy ions.
NC A6 A5 A4 A3 NC A0 A1 A2 NC
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F2 TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12
Ordering Information
PART NUMBER CMM5114AK3 TEMP RANGE PACKAGE -55oC to +125oC Class B, 24 Lead Ceramic Flatpack (Not Rad Verified) -55oC to +125oC Class B, 18 Lead SBDIP (Not Rad Verified)
CE VSS
24 23 22 21 20 19 18 17 16 15 14 13
VDD A7 A8 A9 NC NC I/O1 I/O2 I/O3 I/O4 NC WE
CMM5114AD3
CMM5114AK1DZ -55oC to +125oC Class S, 24 Lead Ceramic Flatpack (Rad Verified) CMM5114AD1DZ -55oC to +125oC Class S, 18 Lead SBDIP (Rad Verified)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518734 2081.2
CMM5114A Functional Diagram
A4 A5 A6 A7 A8 A9 I/O1 TRANSITION DETECTORS, BUFFERS, AND ROW DECODER E MEMORY ARRAY 64 x 64 SENSE AMPLIFIERS AND OUTPUT BUFFER OE I/O2 I/O3 I/O4
POWER CONVERTER
E
TRANSITION DETECTORS, BUFFERS, AND COLUMN DECODER
WE AND CE DECODER (SEE TRUTH TABLE)
A0
A1
A2
A3
WE
CE
TRUTH TABLE CE L L H WE H L X Read Write Not Selected MODE OUTPUT Dependent on Data Input High Impedance
Spec Number 2
518734
Specifications CMM5114A
Absolute Maximum Ratings
Supply Voltage (VDD), All voltage values referenced to VSS Terminal . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC Typical Derating Factor. . . . . . . . . . .3.0mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package. . . . . . . . . . . . . . . . . . . . 78oC/W 18oC/W Ceramic Flatpack Package . . . . . . . . . . . 80oC/W 20oC/W Maximum Package Power Dissipation at +125oC SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.64W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.63W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 12.5mW/oC Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5400 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +6.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .VDD/2 to VDD Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS (NOTE 1) CONDITIONS VIN = 0V or VDD, VCS = VDD, VDD = 5.25V Output Open Circuited Cycle Time = 1s, VDD = 5.25V VOUT = 0.4V, VDD = 4.75V VOUT = VDD - 0.4V, VDD = 4.75V VDD = 4.75V VDD = 4.75V VIN = 0V or VDD, VDD = 5.25V VDD = 5.25V Applied Voltage = 0V or VDD -55oC, +25oC MIN 2.6 1.8 VDD/2 VDD = VDR MAX 0.1 5.0 0.8 2 5 2 50 +125oC MIN 1.7 1.1 VDD/2 MAX 1.0 6.0 0.8 10 50 2.5 500 UNITS mA mA mA mA V V A A V A
PARAMETER Quiescent Device Current Operating Device Current (Note 2) Output (Sink) Current Output (Source) Current Input Low Voltage (Note 3) Input High Voltage (Note 3) Input Leakage Current Three-State Output Leakage Current Minimum Data Retention Voltage Data Retention Quiescent Current NOTES:
SYMBOL IDD IDD1 IOL IOH VIL VIH IIN IOZ VDR IDDDR
1. VDD = 5V 5%, VIN = 0V or VDD, Unless Otherwise Specified. 2. Operating current measured using 1MHz cycle and CL = 50pF. 3. Measured using 1MHz cycle. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) LIMITS -55oC, +25oC PARAMETER READ CYCLE TIMES Read Cycle Access Chip Enable to Output Valid WRITE CYCLE TIMES Write Cycle tAVAV 250 300 ns tAVAV tAVQV tELQV 200 200 220 250 250 280 ns ns ns SYMBOL MIN MAX MIN +125oC MAX UNITS
Spec Number 3
518734
Specifications CMM5114A
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) (Continued) LIMITS -55 C, +25 C PARAMETER Write Pulse Width (Note 2) Address Hold Time From Write Enable Address to Write Set Up Time Address Set Up to End of Write CE to Write Set Up Time CE Pulse Width (Note 2) Data to Write Set Up Time Data Hold From Write NOTES: 1. VDD = 5V 5%, CL = 50pF. 2. CE and WE must overlap for at least tWLWH minimum value, tDVWH minimum value must occur during this overlap and CE must be held low for 10ns after WE goes high. 3. Table 2 AC parameters are verified with VDD = 4.75V. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS -55oC, +25oC PARAMETER Output Voltage Low Level Output Voltage High Level Input Capacitance Output Capacitance Chip Enable to Output Active Output Three-State from Disable Output Hold from Address Change NOTE: 1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterize upon initial design release and upon design changes which would affect these characteristics. SYMBOL VOL VOH CIN COUT tELQA tEHQZ tAVQZ MIN VDD - 0.1 20 30 MAX 0.1 5 7 100 110 MIN VDD - 0.2 20 55 +125oC MAX 0.2 5 7 140 150 UNITS V V pF pF ns ns ns SYMBOL tWLWH tWHAV tAVWL tAVWH tELWH tELEH tDVWH tWHDX MIN 200 40 0 200 200 200 90 5 MAX MIN 200 50 0 250 250 250 105 5
o o
+125oC MAX UNITS ns ns ns ns ns ns ns ns
TABLE 4. POST 10K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS POST RADIATION +25oC PARAMETER Quiescent Device Current Operating Device Current (Note 1) Output Current (Sink) Output Current (Source) Input Low Voltage (Note 2) Input High Voltage (Note 2) Input Leakage Current Three-State Output Leakage Current SYMBOL IDD IDD1 IOL IOH VIL VIH IIN IOZ VIN = 0V or VDD Applied Voltages = 0V or VDD CONDITIONS VIN = 0V or VDD, VCS = VDD Output Open Circuited Cycle Time = 1s VOUT = 0.4V VOUT = VDD - 0.4V MIN 1.7 -1.1 VDD/2 MAX 1.0 6.0 0.8 10 50 UNITS mA mA mA mA V V A A
Spec Number 4
518734
Specifications CMM5114A
TABLE 4. POST 10K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS POST RADIATION +25oC PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current Read Cycle Access CE to Output Valid Write Cycle Write Pulse Width (Note 3) Address Hold Time from Write Enable Address to Write Set Up Time Address Set Up to End of Write CE to Write Set Up Time CE Pulse Width (Note 3) Data to Write Set Up Time Data Hold From Write NOTES: 1. CE and WE must overlap for at least tWLWH minimum value, tDVWH minimum value must occur during this overlap. 2. Measured using 1MHz cycle. 3. Operating current measured using 1MHz cycle and CL = 50pF. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Quiescent Device Current Output Low Drive Current (Sink) Output High Drive Current (Source) Three-State Output Leakage Current SYMBOL IDD IOL IOH IOZ DELTA LIMITS +30A -10% of 0 hour value -10% of 0 hour value +500nA SYMBOL VDR IDDDR tAVAV tAVQV tELQV tAVAV tWLWH tWHAV tAVWL tAVWH tELWH tELEH tDVWH tWHDX CONDITIONS MIN 250 300 200 50 0 250 250 250 105 5 MAX 2.5 500 250 280 UNITS V A ns ns ns ns ns ns ns ns ns ns ns ns
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A Group B (Optional) Group C (Optional) Group D (Optional) Group E, Subgroup 2 B5 Others METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 Samples/5005 -IRZ SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7 N/A 1, 7, 9 1, 7, 9 3 SUBGROUPS 1, 7, 9 N/A 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 N/A
Spec Number 5
518734
CMM5114A Intersil Space Level Product Flow -1DZ
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer), 2 Samples/Wafer, 0 Rejects Sample - Die Shear Monitor, Method 2019 or 2027 Sample - Wire Bond Monitor, Method 2011 100% Nondestructive Bond Pull, Method 2023 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% Serialization 100% Initial Test Optional High Temperature Stress Test, 48 Hours at +125oC (This is a Intersil Option) Optional Interim Electrical Test (T0) (Only if the High Temperature Stress Test was performed) 10% PDA (Note 1)
NOTES: 1. If the optional 48-hour Stress Test is not utilized, then the Initial Test is used for T0 reference when calculating deltas. 2. Failures from Interim Electrical Tests T1 and T2 are combined for determining PDA. 3. Failures from subgroups 1, 7, and deltas are used for calculating PDA. The maximum allowable PDA is 5% with no more than 3% from subgroup 7. 4. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. Per Method 5004. 5. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 6. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, RAD Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Static Burn-In 1, Condition A or B, 24 Hours Minimum, +125oC Minimum (or Equivalent Time/Temperature), Method 1015 100% Interim Electrical Test (T1) and Deltas (T0-T1) 100% Static Burn-In 2, Condition A or B, 24 Hours Minimum, +125oC Minimum, (or equivalent Time/Temperature), Method 1015 100% Interim Electrical Test (T2) and Delta (T0-T2) (Notes 2, 3) 100% Dynamic Burn-In, Condition D, 240 Hours at 125oC (or Equivalent Time/Temperature), Method 1015 100% Interim Electrical Test (T3). 5% PDA All Failures, Deltas (T0-T3) (Note 3) 100% Final Test, Method 5004 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 4) 100% External Inspection, Method 2009 Sample - Group A, Method 5005 (Note 5) 100% Data Package Generation (Note 6)
Spec Number 6
518734
CMM5114A Intersil Space Level Product Flow -3
100% Internal Visual Inspection, Method 2010, Condition B or Alternate Condition B 100% Temperature Cycle, Method 1010, Condition C 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Fine/Gross Leak, Method 1014 100% Initial Electrical Test, +25oC Optional High Temperature Stress Test, 48 Hours at +125oC (This is a Intersil Option) Optional Interim Electrical Test (Only if the High Temperature Stress Test was performed at Intersil option) 10% PDA 100% Static Burn-In, Condition A or B, 24 Hours minimum, +125oC minimum (or Equivalent Time/Temperature), per Method 1015 100% Interim Electrical Test, 5% PDA, 3% PDA functional (Note 1)
NOTES: 1. Failures from subgroups 1 and 7 are used for calculating PDA. The maximum allowable PDA is 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 3. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Final Electrical Tests 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 2) Data Package Generation (Note 3)
Spec Number 7
518734
CMM5114A Timing Waveforms
READ CYCLE
tAVAV tAVQV ADDR CE CE tELQV tELQA DOUT ACTIVE tEHQZ tAVQZ VALID DIN DON'T CARE WE tWHDX tDVWH VALID DON'T CARE tAVWL tWLWH ADDRESS tELWH tELEH
WRITE CYCLE
tAVAV
tAVWH tWHAV
NOTE: WE is high during the READ cycle timing measurement reference level is VDD/2.
NOTE: 1. Timing measurement is referenced to VDD/2.
Typical Performance Curves
210 CHIP ENABLE ACCESS TIME (ns) CHIP ENABLE ACCESS TIME (ns) 190 170 150 130 110 90 70 3.5 TA = +125oC TA = +25oC TA = -55oC 210 190 TA = +125oC 170 150 130 110 90 70 3.5 TA = +25oC TA = -55oC
4.0
4.5
5.0
5.5
6.0
6.5
7.0
4.0
4.5
5.0
5.5
6.0
6.5
7.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 1. ADDRESS ACCESS TIME CHARACTERISTICS
FIGURE 2. CHIP ENABLE ACCESS TIME CHARACTERISTICS
1.8 1.7 INPUT LOW VOLTAGE (V) 1.6 1.5 1.4 1.3 1.2 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TA = +125oC TA = +25oC TA = -55oC
3.6 3.4 INPUT HIGH VOLTAGE (V) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) TA = +125oC TA = +25oC TA = -55oC
FIGURE 3. INPUT LOW VOLTAGE CHARACTERISTICS
FIGURE 4. INPUT HIGH VOLTAGE CHARACTERISTICS
Spec Number 8
518734
CMM5114A Typical Performance Curves
OUTPUT LOW (SINK) DRIVE CURRENT (mA) 12 11 10 9 8 7 6 5 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 SUPPLY VOLTAGE (V) TA = -55oC TA = +25oC
(Continued)
OUTPUT HIGH (SOURCE) DRIVE CURRENT (mA)
6.4 6.0 5.6 5.2 4.8 4.4 4.0 3.6 3.5 TA = +125oC TA = +25oC TA = -55oC
TA = +125oC
4.0
4.5
5.0
5.5
6.0
6.5
7.0
SUPPLY VOLTAGE (V)
FIGURE 5. OUTPUT LOW (SINK) DRIVE CURRENT CHARACTERISTICS
FIGURE 6. OUTPUT HIGH (SOURCE) DRIVE CURRENT CHARACTERISTICS
160 QUIESCENT DEVICE CURRENT (A) 140 120 100 80 60 40 20 0 3.5 TA = -55oC 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TA = +25oC TA = +125oC
SUPPLY VOLTAGE (V)
FIGURE 7. QUIESCENT DEVICE CURRENT CHARACTERISTICS
Spec Number 9
518734
CMM5114A Burn-In Circuits
VDD R1 STATIC 1 STATIC 2 VDD R1 R1 3 4 R1 5 R1 6 R1 7 R1 8 9 11 R1 10 12 13 R1 R1 14 R1 16 R1 15 R1
A0 A4 A9 A8 A7 A6
A5
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10 A3 A2 A1 A10 A11 A12 A13 01
1 R1 2 R1 R1
18 17
A14
DYNAMIC CONFIGURATION NOTES: R1 = 1k to 6k, Unless Otherwise Specified VDD = 5.5V (Min) Frequencies: A0 = 100KHz 5% A1 = A0/2 . . . . A13 = A12/2 01 = 200KHz 5%, 0.6s Low, 4.4s High Ceramic DIP biasing shown. NOTES:
STATIC CONFIGURATION
R1 = 1k to 6k VDD = 5.5V (Min) Stress Test; Switch is at VSS Static 1: Switch is at VDD Static 2: Switch is at VSS Ceramic DIP biasing shown.
Irradiation Circuit
1 2 3 4 5 6 7 8 GND 9
18 17 16 15 14 13 12 11 10
VDD
NOTES: VDD = +5V, 5% GND = Ground All Resistors are 47k 5%
Spec Number 10
518734
CMM5114A
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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