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MITSUBISHI LSIs
P
tion. al specifica is is not a fin to change. Notice : Th are subject metric limits Some para
RY RELIMINA
M6MF16S2AVP
16777216-BIT (2097152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM Stacked-MCP (Multi Chip Package) FEATURES * Access time (Flash Memory, SRAM) 110ns (Max.) * Supply voltage Vcc=2.7 ~ 3.6V * Ambient temperature Ta=-20 ~ 85C * Package : 48-pin TSOP (Type-I) , 0.4mm lead pitch
DESCRIPTION The MITSUBISHI M6MF16S2AVP is a Stacked Muti Chip Package (S-MCP) that contents 16M-bit flash memory and 2M-bit Static RAM in a 48-pin TSOP (TYPE-I). 16M-bit Flash memory is a 2097152 bytes, 3.3V-only, and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR(DIvided bit-line NOR) architecture for the memory cell. 2M-bit SRAM is a 262144 bytes unsynchronous SRAM fabricated by silicon-gate CMOS technology. M6MF16S2AVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight .
APPLICATION Mobile communication products
PIN CONFIGURATION (TOP VIEW)
A20 A19 A18 A16 A15 A14 A13 S-WE# S-CE2 A12 F-CE# F-Vcc S-Vcc F-WP2# F-RP# A11 A10 A9 A8 A7 A6 A5 A4 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 F-WP1# S-OE# A17 F-WE# F-OE# S-CE1# F-RY/BY# DQ7 DQ6 DQ5 DQ4 F-Vcc F-GND F-GND DQ3 S-GND DQ2 DQ1 DQ0 A0 A1 A2 A3 NC
10.0 mm
14.0 mm
F-Vcc F-GND S-Vcc S-GND A0-A17 A18-A20 DQ0-DQ7 F-CE# F-OE# F-WE# F-WP1#,WP2# F-RP# F-RY/BY# S-CE1#,CE2 S-OE# S-WE#
1
:Vcc for Flash :GND for Flash :Vcc for SRAM :GND for SRAM :Flash/SRAM common Address :Address for Flash :Data I/O :Flash Chip Enable :Flash Output Enable :Flash Write Enable :Flash Write Protect :Flash Reset Power Down :Flash Ready /Busy :SRAM Chip Enable :SRAM Output Enable :SRAM Write Enable
NC:Non Connection
May.1998 , Rev.1.2
MITSUBISHI LSIs
P
tion. al specifica is is not a fin to change. Notice : Th are subject metric limits Some para
RY RELIMINA
M6MF16S2AVP
16777216-BIT (2097152-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM Stacked-MCP (Multi Chip Package)
BLOCK DIAGRAM
16M Flash Memory
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256 BYTE PAGE BUFFER 64K BYTE BLOCK0 64K BYTE BLOCK1 64K BYTE BLOCK2 X-DECODER F-VCC F-GND (0V)
ADDRESS INPUTS (A0-A17 is in common to SRAM)
64K BYTE BLOCK31 Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER MULTIPLEXER
Command User Interface
CHIP ENABLE INPUT F-CE# OUTPUT ENABLE INPUT F-OE# WRITE ENABLE INPUT F-WE#
WRITE PROTECT INPUT F-WP1#,WP2#
Write State Machine INPUT/OUTPUT BUFFERS
RESET/POWER DOWN INPUT F-RP# READY/BUSY OUTPUT F-RY/BY# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DATA INPUTS/OUTPUTS (In common to SRAM)
2M SRAM
A4 A5
ADDRESS INPUTS (In common to Flash memory)
ADDRESS INPUT BUFFER
DQ0
ROW DECODER 262144 WORDS x 8 BITS OUTPUT BUFFER (512 ROWS x 128COLUMNS x 32 BLOCKS) SENSE AMP.
A6 A7 A8 A9 A10 A11 A12
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
A1 A2 A3 A13 A14 A15 A16 A17
CLOCK GENERATOR
DATA INPUT BUFFER
COLUMN DECODER
A0
ADDRESS INPUT BUFFER
S-WE#
ADDRESS INPUT BUFFER BLOCK DECODER
S-CE1# S-CE2
S-OE# S-VCC S-GND
(0V)
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May.1998 , Rev.1.2
DATA INPUTS/OUTPUTS (In common to Flash memory)
PRELIMIN
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
1. Flash Memory
FUNCTION
The Flash Memory of M6MF16S2AVP includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase, page (256byte) program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption. Read The Flash Memory of M6MF16S2AVP has three read modes, which accesses to the memory array, the Device Identifier and the Status Register. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the Flash Memory automatically resets to read array mode. In the read array mode, low level input to CE# and OE#, high level input to WE# and RP#, and address signals to the address inputs (A0-A20) output the data of the addressed location to the data input/output(D0-D7). Write Writes to the CUI enable reading of memory array data, device identifiers and reading and clearing of the Status Register. they also enable block erase and program. The CUI is written by bringing WE# to low level, while CE# is at low level and OE# is at high level. Addresses and data are latched on the earlier rising edge of WE# and CE#. Standard micro-processor write timings are used. Output Disable When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. Standby When CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance(High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. Deep Power-Down When RP# is at VIL, the device is in the deep powerdown mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance(High-Z) state. After return from powerdown, the CUI is reset to Read Array , and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid. SOFTWARE COMMAND DEFINITIONS The device operations are selected by writing specific software command into the CUI. Read Array Command (FFH) The device is in Read Array mode on initial device powerup and after exit from deep powerdown, or by writing FFH to the CUI. The device remains in Read Array mode until the other commands are written. Read Device Identifier Command (90H) The Device Identifier is read after writing the Read Device Identifier command of 90H to the Command User Interface. Following the command write, the manufacturer code and the device code can be read from address 000000H and 000001H, respectively. Read Status Register Command (70H) The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. The contents of Status Register are latched on the later falling edge of OE# or CE#. So CE# or OE# must be toggled every status read. Clear Status Register Command (50H) The Erase Status and Program Status bits are set to "1"s by the Write State Machine and can be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. Block Erase / Confirm Command (20H/D0H) Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation. Suspend/Resume Command (B0H/D0H) Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes.
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May.1998 , Rev.1.2
PRELIMIN
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
Program Command Program consists of data load sequence to page buffer and data program sequence to flash memory array. A) Start Load Page Buffer (DBH/XXH/XXH) Writing Start Load Page Buffer command allows data load to page buffer. DBH is written to the CUI, follwed by two write cyclle of a certain command except for Block Erase Command(20H/D0H) and Lock Bit Program Command(77H/D0H). B) Sequential Load to Page Buffer (DBH/FFH/00H) Writing Sequential Load to Page Buffer command allows 256 bytes data load to page buffer sequentially. Follwing a three command sequence(DBH/FFH/00H) , 256 writes cycle specifying the address and data executes loading to page buffer. In this mode, only A0-7 is used and A8-A20 is a don't care. C) End Load Page Buffer (5FH/XXH/XXH) Writing End Load Page Buffer command ends data load to page buffer. 5FH is written to the CUI, follwed by two write cyclle of a certain command except for Block Erase Command(20H/D0H) and Lock Bit Program command(77H/D0H). The data of page command is stored while Vcc power is on or until writing Page Buffer Write to Flash command or Page Buffer Clear command.The stored data in page buffer can be changed by data load sequence follwed by re-start load page buffer. D) Page Buffer Write to Flash (0EH/D0H) Programming to flash memory array from page buffer is executed by Page Buffer Write to Flash command. The Page Buffer Write to Flash setup command (0EH) is witten to the CUI, followed by the confirm commasnd (D0H). In this mode, A8-A20 is used. The WSM controls the program pulse application and verify operation. After programming, each page buffer is cleared to "FFH". And the page buffer data is invaid in the suspend mode. Basically re-program must not be done on a page which has already programmed.
DATA PROTECTION The Flash Memory of M6MF16S2AVP provides hardware-locking of memory blocks. Each block has an associated nonvolatile lock-bit which determines the lock status of the block.In addition, this flash memory has a master Write Protect pin (WP) which prevents any modifications to memory blocks. When WP2# is at low, all memory blocks are locked. And when both WP1# and WP2# are at low, this part is in read array only mode.(not be accepted any write command) When WP1# is at low and WP2# is at high, the memory blocks whose lock-bits are set to "0" are locked. When both WP1# and WP2# are at high, lock-bits can be programmed (to "0"), all blocks can be programmed or erased regardless of the state of the lock-bits, and lock-bits are cleared to "1" by this erase. See the BLOCK LOCKING table on P.6 for details. Power Supply Voltage When the power supply voltage (Vcc) is less than 2.2V, the device is set to the Read-only mode. A delay time of 2 us is required before any device operation is initiated. The delay time is measured from the time Vcc reaches Vccmin. During power up, F-RP#=GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device.
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May.1998 , Rev.1.2
PRELIMIN
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
MEMORY MAP
1F0000H-1FFFFFH 1E0000H-1EFFFFH 1D0000H-1DFFFFH 1C0000H-1CFFFFH 1B0000H-1BFFFFH 1A0000H-1AFFFFH 190000H-19FFFFH
32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK
060000H-06FFFFH 050000H-05FFFFH 040000H-04FFFFH 030000H-03FFFFH 020000H-02FFFFH 010000H-01FFFFH 000000H-00FFFFH A0 - A20
32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK 32Kword BLOCK
Flash Memory Memory Map
BUS OPERATIONS
Mode Read Pins F-CE# VIL VIL VIL VIL VIL VIH VIL VIL VIL X F-OE# VIL VIL VIL VIL VIH X 2) VIH VIH VIH X F-WE# VIH VIH VIH VIH VIH X VIL VIL VIL X F-RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL DQ0-7 Data out Status Register Data Lock Bit Data (DQ6) Identifier Code Hi-Z Hi-Z Command/Data in Command Command Hi-Z F-RY/BY# VOH(Hi - Z) X 1) X VOH(Hi - Z) X X X X X VOH(Hi - Z)
Array Status Register Lock Bit Status Identifier Code Output Disable Stand by Program Write Erase Others Deep Power Down
1) X at RY/BY# is VOL or VOH(Hi-Z). *The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low,it indicates that the WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition. 2) X can be VIH or VIL for control pins.
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May.1998 , Rev.1.2
PRELIMIN
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command
Read Array Device Identifier Read Status Register Clear Status Register Block Erase / Confirm Suspend Resume
Start Load Page Buffer Sequential Load Page Buffer End Load Page Buffer Page Buffer Write to Flash Read Lock Bit Status 4)
Lock Bit Program / Confirm Erase All Unlocked Blocks / Confirm 8) Sleep
1) 2) 3) 4)
Mode Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
1st bus cycle Address X X X X X X X X X X X X X X X
Data FFH 90H 70H 50H 20H B0H D0H DBH E0H 5FH 0EH 71H 77H A7H F0H
Mode Read Read Write
2nd bus cycle Address
Ist bus cycle
Data ID 1) SRD 2) D0H
Mode
3rd bus cycle Address
Data
IA 1) X BA 3)
Write Write Write Write Read Write Write
X X X WA 6) BA BA X
X FFH X D0H D6 7) D0H D0H
Write Write Write
X X X
X 00H 5) X
IA=ID Code Address : A0=VIL (Manufacture's Code) : A0=VIH (Device Code), ID=ID Code, A1-A20=VIL SRD=Status Register Data BA=Block Address (A16-A20) Two dummy write cycle is necessary,except for Block Erase/Confirm command(20H/D0H) and Lock Bit Program/Confirm command(77H/D0H), after Start Page Buffer Load command and End Load Page Buffer command. 6) WA=Write Address : Page Buffer Data is programmed to the same page address in the memory arrary, and address A0-7 is ignored. 7) DQ6 provides Block Lock Bit Status, DQ6=1 : Block Unlock , DQ6=0 : Block Locked. 8) Sleep command (F0H) put the device into the sleep mode after completing the current operation. The active current is reduced to deep power -down levels. The Read Array command (FFH) must be written to get the device out of sleep mode.
BLOCK LOCKING
RP# VHH WP1# X VIH VIH VIL VIL X WP2# X VIH VIL VIH VIL X Erase/Program Operation
Memory Block Lock Bit
Write Protection Provided All Blocks/Lock Bits Unlocked (Erase/Program enable) All Blocks/Lock Bits Unlocked (Erase/Program enable) All Blocks/Lock Bits Locked Locked by Lock Bit Alll Blocks/Lock Bits Locked (Read Array Only Mode) All Blocks/Lock Bits Locked (Deep Power Down Mode)
Unlock Unlock Lock
Depend on Lock Bit Data 1)
Lock Lock
Unlock Unlock Lock Lock Lock Lock
4)
1) When the Lock bit is "0" ,its block cannot be programed and erased. Lock bit is set to "0" by LOCK BIT PROGRAM. Locked bit("0") is cleared to "1" with block memory by BLOCK ERASE on setting unlock mode. 2) DQ6 provides Lock Bit Status of each block after writing the Read Lock Status command (71H). 3) WP# pin must not be switched during performing Read / Write operations or WSM Busy (WSMS = 0). 4) The device prpvides a complete read array only mode. (not be accepted any write command, including read mode command, ex:device identifier, read status register.) 5) X can be VIH or VIL for control pins.
STATUS REGISTER DATA (SRD)
Symbol SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 (D7) (D6) (D5) (D4) (D3) (D2) (D1) (D0) Status Write State Machine Status Suspend Status Erase Status Program Status Block Status after Program Reserved Reserved Device Sleep Status Definition "1" Ready Suspended Error Error Error Device in Sleep "0" Busy Operation in Progress / Completed Successful Successful Successful Device Not in Sleep
*DQ3 indicates the block status after the page programming. When DQ3 is "1", the page has the over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
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May.1998 , Rev.1.2
PRELIMIN
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
DEVICE IDENTIFIER CODE
Code Manufacturer Code Device Code
Pins
A0 VIL VIH
D7 0 0
D6 0 1
D5 0 1
D4 1 0
D3 1 1
D2 1 0
D1 0 0
D0 0 1
Hex. Data 1CH 69H
ABSOLUTE MAXIMUM RATINGS
Symbol F-Vcc VI1 VI2 Ta Tbs Tstg I OUT Parameter Vcc voltage (Flash Memory) All input or output voltage except1) Vcc,RP# for RP# supply voltage Ambient temperature Temperature under bias Storage temperature Output short circuit current Conditions
with respect to Ground
Min. -0.2 -0.2 -0.6 -20 -30 -65
Max. 4.6 4.6 14.0 85 85 125 100
Unit V V V C C C mA
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Symbol CIN COUT Parameter Input capacitance (address, Control Pins) Output capacitance Test conditions Ta = 25C, f=1MHz, VIN=VOUT=0V Min. Limits Typ. Max. 8 12 Unit pF pF
Note: The value of common pins to SRAM is the sum of Flash Memory and SRAM.
DC ELECTRICAL CHARACTERISTICS
Symbol ILI ILO ISB1 ISB2 ISB3 ISB4 ICC1 ICC2 ICC3 ICC4 ICC5 I RP VIHH VIL VIH VOL VOH1 VOH2 VLKO Parameter Input leakage current Output leakage current Vcc standby current Vcc deep powerdown current Vcc read currenr Vcc write current Vcc program currenrt Vcc erase current Vcc suspend current RP# block unlock current RP# block unlock voltage Input low voltage Input high voltage Output low voltage Output high voltage Low Vcc Lock-Out voltage 2)
( Ta = -20 ~ 85C, Vcc = 2.7V ~ 3.6V, unless otherwise noted ) Test conditions Min Limits Typ Max 1.0 10 200 5 15 5 25 30 30 40 200 500 12.6 0.8
Vcc+0.5
Unit A A A A A A mA mA mA mA A A V V V V V V V
0V VIN F-VCC 0V VOUT F-VCC
F-Vcc = 3.6V, VIN=VIL/VIH, F-CE#=F-RP#=F-WP1#,WP2#=VIH
F-Vcc=3.6V,VIN=F-GND or F-Vcc, F-CE#=F-RP#=F-WP1#,WP2#=Vcc0.3V
F-VCC = 3.6V, VIN=VIL/VIH, F-RP#= VIL
F-Vcc = 3.6V, VIN=F-GND or F-Vcc, F-RP#=F-GND0.3V
50 0.1 5 0.1 7
F-VCC = 3.6V, VIN=VIL/VIH, F-CE# = VIL, F-RP#=F-OE#=VIH, f = 5MHz, IOUT = 0mA
F-Vcc=3.6V,VIN=VIL/VIH,F-CE#=F-WE#=VIL,F-RP#=F-OE#=VIH F-Vcc = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP1#,WP2# = VIH F-Vcc = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP1#,WP2# = VIH F-Vcc = 3.6V, VIN=VIL/VIH, F-CE# = F-RP# =F-WP1#,WP2# = VIH
F-RP# = VHH max 11.4 - 0.5 2.0 IOL = 4.0mA IOH = -2.5mA IOH = -100A 0.85Vcc
Vcc-0.4
12.0
0.45
1.5
2.5
All currents are in RMS unless otherwise noted. 1) Typical values at Vcc=3.3V, Ta=25C 2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO. If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
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May.1998 , Rev.1.2
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MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS ( Ta = -20 ~ 85C, Vcc = 2.7V ~ 3.6V, unless othe
Read-Only Mode
Limits Symbol tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tOH tOEH tPS tAVAV tAVQV tELQV tGLQV tELQX tEHQZ tGLQX tGHQZ tPLQZ tOH tWHGL tPHEL Parameter Min Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low-Z Chip enable high to output in high Z Output enable to output in low-Z Output enable high to output in high Z RP# low to output high-Z Output hold from CE#, OE#, addresses OE# hold from WE# high RP# high recovery to CE# low 110 110 110 55 0 30 0 30 300 0 110 500 Typ Max ns ns ns ns ns ns ns ns ns ns ns ns Unit
Timing measurements are made under AC waveforms for read operations.
Read/Write Mode (WE# control)
Limits Symbol tWC tAS tAH tDS tDH tCS tCH tWP tWPH tBLS tWPS tBLH tWPH tDAP tDAE tWHRL tPS tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL Write cycle time Address set-up time Address hold time Data set-up time Data hold time
Chip enable set-up time
Parameter Min 110 50 10 50 10 0 0 60 20 110 0 5 50 500 80 600 110 Typ Max
Unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
Chip enable hold time Write pulse width Write pulse width high
tPHHWH Block Lock set-up to write enable high tPHHWH Block Lock hold from valid SRD tWHRH1 tWHRH2 tWHRL tPHWL Duration of auto-program operation Duraruin of auto-erase operation
Write enable high to RY/BY# low
F-RP# high recovery to F-WE# low
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25C
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May.1998 , Rev.1.2
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MITSUBISHI LSIs
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M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
Read/Write Mode (CE# control)
Limits Symbol tWC tAS tAH tDS tDH tWS tWH tCEP tCEPH tBLS tWPS tBLH tWPH tDAP tDAE tEHRL tPS tAVAV tAVWL tWLAX tDVWH tWHDX tELWL tWHEH tWLWH tWHWL Parameter Min Write cycle time Address set-up time Address hold time Data set-up time Data hole time
Write enable set-up time
Unit Typ Max ns ns ns ns ns ns ns ns ns ns ns 5 50 500 80 600 110 ms ms ns ns 110 50 10 50 10 0 0 60 20 110 0
Write enable hold time CE# pulse width CE# pulse width high
tPHHWH Block Lock set-up to write enable high tPHHWH Block lock hold from valid SRD tWHRH1 tWHRH2 tEHRL tPHWL Duration of auto-program operation Duration of auto-erase operation
Chip enable high to RY/BY# low
RP# high recovery to write enable low
Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25C
Erase and Program Performance
Parameter Block Erase Time Block Program Time (Page Mode) Page Program Time Min Limits Typ 40 1.3 4 Max 600 5 80 Unit ms sec ms
Vcc Power UP/Down Timing
Symbol tVCS Parameter RP# =VIH set-up time from Vcc at 2.7V Min 2 Limits Typ Max Unit s
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. The device must be protected against initiation of write cycle for memory contents during power up/down. The delay time of min.2usec is always required before read operation or write operation is initiated from the time Vcc reaches 2.7V during power up. By holding RP# VIL, the contents of memory is protected during Vcc power up/down. During power up, RP# must be held VIL for min.2us from the time Vcc reaches 2.7V. During power down, RP# must be held VIL until Vcc reaches GND. RP# doesn't have latch mode ,so RP# must be held VIH during read operation or erase/program operation.
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May.1998 , Rev.1.2
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MITSUBISHI LSIs
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M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
VIH
ADDRESSES ADDRESS VALID
VIL F-CE# VIH VIL F-OE# VIH VIL F-WE# VIH VIL DATA VOH VOL tPS F-RP# VIH VIL HIGH-Z tCLZ tOEH
tRC ta (AD) ta (CE) tDF(CE)
tDF(OE) ta (OE) tOLZ
OUTPUT VALID
tOH HIGH-Z
tPHZ
TEST CONDITIONS FOR AC CHARACTERISTICS Test Configuration Input voltage Input rise and fall times (10%-90%) Reference voltage at timing measurement Capacitance load value Output load : 1TTL gate + CL or
1.3V 1N914 3.3k
Vcc=2.7V ~ 3.6V VIL VIH 0V 3.0V 10ns 1.5V CL 100pF
DUT
CL
Vcc POWER UP / DOWN TIMING
Read/Write Inhibit Read/Write Inhibit Read/Write Inhibit
F-VCC
3.3V GND tVCS VIH VIL VIH VIL
F-RP#
F-CE#
tPS
tPS
F-WE#
VIH VIL
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May.1998 , Rev.1.2
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M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
AC WAVEFORMS FOR READ/WRITE (WE# control)
Address VIH
ADDRESS VALID
PRPGRAM or ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL F-CE# VIH VIL tCS F-OE# VIH VIL F-WE# VIH VIL Data VIH VIL
tWC
tAS
tAH ta(CE)
tCH tWPH tOEH tDAP,tDAE
ta(OE)
tWP
DIN1
tDS
DIN2
tDH
SRD FFH
tWHRL F-RY/BY# VOH VOL VHH F-RP# VIH VIL VIH F-WP1#, WP2# VIL
Note, (1) Block Rrase: DIN1=20H, DIN2=D0H (tDAE : Duration of Block Erase) (2) Page Buffer Write to Flash : DIN1=0EH, DIN2=D0H (tDAP : Duration of program) (3) Lock Bit Program / Confirm: DIN1=77H, DIN2=D0H (tDAP : Duration of program) (4) Erase All Unlocked Blocks / Confirm : DIN1=A7H, DIN2=D0H (tFERS : Duration of Chip Erase)
tBLS tPS
tBLH
tWPS
tWPH
AC WAVEFORMS FOR READ/WRITE (CE# control)
Address VIH
ADDRESS VALID
PRPGRAM or ERASE READ STATUS REGISTER WRITE READ ARRAY COMMAND
VIL F-CE# VIH VIL F-OE# VIH VIL F-WE# VIH VIL Data VIH VIL tWS
tWC
tAS
tAH ta(CE)
tCEP
tCEPH tOEH tDAP,tDAE tWH tDS
ta(OE)
tDH
DIN2 SRD FFH
DIN1
tEHRL F-RY/BY# VOH VOL VHH F-RP# VIH VIL F-WP1#, WP2# VIH VIL
Note, (1) Block Rrase: DIN1=20H, DIN2=D0H (tDAE : Duration of Block Erase) (2) Page Buffer Write to Flash : DIN1=0EH, DIN2=D0H (tDAP : Duration of program) (3) Lock Bit Program / Confirm: DIN1=77H, DIN2=D0H (tDAP : Duration of program) (4) Erase All Unlocked Blocks / Confirm : DIN1=A7H, DIN2=D0H (tFERS : Duration of Chip Erase)
tBLS tPS
tBLH
tWPS
tWPH
11
May.1998 , Rev.1.2
PRELIMIN
ARY
MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
AC WAVEFORMS FOR PAGE BUFFER WRITE OPERATION (WE# control)
VIH VIL F-CE# VIH VIL VIH VIL Data VIH VIL
DIN
Address
Address Valid
tAS tCS tWP
tAH tCH tWPH
F-WE#
tDS
tDH
AC WAVEFORMS FOR PAGE BUFFER WRITE (CE# control)
VIH VIL F-CE# VIH VIL VIH VIL Data VIH VIL
DIN
Address
Address Valid
tAS
tAH
tCEP tWS tDS tWH tDH
tCEPH
F-WE#
FULL STATUS CHECK PROCEDURE
STATUS REGISTER READ
SR.4 =1 and SR.5 =1 ? NO
YES
COMMAND SEQUENCE ERROR
SR.5 = 0 ? NO YES
BLOCK ERASE ERROR
SR.4 = 0 ? NO
PROGRAM ERROR ( PAGE, LOCK BIT)
SR.3 = 0 ? NO YES SUCESSFUL (BLOCK ERASE, PROGRAM)
PROGRAM ERROR (BLOCK)
12
May.1998 , Rev.1.2
PRELIMIN
ARY
MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
LOCK BIT PROGRAM FLOW CHART
START
RP#=WP#(1,2)=VIH,or RP#=VIHH
WRITE 77H
WRITE D0H BLOCK ADDRESS
SR.7 = 1 ? NO YES
SR.4 = 0 ? NO YES RP#=VIH, WP#(1,2)=VIL
LOCK BIT PROGRAM ERROR
LOCK BIT PROGRAM SUCCESSFUL
BLOCK ERASE FLOW CHART
START
WRITE 20H
WRITE D0H BLOCK ADDRESS
STATUS REGISTER READ
NO SR.7 = 1 ?
WRITE B0H ?
NO
YES FULL STATUS CHECK IF DESIRED
YES
SUSPEND LOOP WRITE D0H
YES
BLOCK ERASE COMPLETED
13
May.1998 , Rev.1.2
PRELIMIN
ARY
MITSUBISHI LSIs
tion. al specifica ge. is is not a fin bject to chan Notice : Th limits are su e parametric Som
M6MF16S2AVP
16777216-BIT (2 M x 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY
PROGRAM FLOW CHART (PAGE BUFFER WRITE TO FLASH FLOW)
START
SUSPEND / RESUME FLOW CHART
START
WRITE B0H WRITE DBH, X, X
SUSPEND
START LOAD PAGE BUFFER
STATUS REGISTER READ
n=0
WRITE E0H, FFH, 00H
SEQUENTIAL LOAD PAGE BUFFER
SR.7 = 1? NO YES
WRITE ADDRESS n, DATA n
n = n+1
SR.6 =1? YES
NO
PROGRAM / ERASE COMPLETED
n = FFH ? YES WRITE 5FH, X, X
NO
WRITE FFH
READ ARRY DATA
WRITE 0EH
PAGE BUFFER WRITE TO FLASH
DONE READING ? YES WRITE D0H NO
WRITE ADDRESS, D0H
RESUME
WRITE B0H ? NO
YES SR.7 = 1 and SR.6 = 1 ? YES OPERARTION RESUMED NO
SR.7 = 1 ? NO YES FULL STATUS CHECK IF DESIRED
SUSPEND LOOP
WRITE D0H
PROGRAM COMPLETED
YES
Note; Block Erase /Confirm command(20H/DOH) and Lock Bit Program /Confirm command is not allowed as two-dummy cycles after Start Page Buffer load command and End Page Buffer Load command is written.
14
May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
2. SRAM
FUNCTION
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
The SRAM of the M6MFT/B16S2TP is the same chip with M5M5V208 and its operation mode is determined by a combination of the device control inputs S-CE1#, S-CE2, S-WE# and S-OE#. Each mode is summarized in the function table. A write cycle is executed whenever the low level S-WE# overlaps with the low level S-CE1# and the high level S-CE2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of S-WE#,S-CE1# or S-CE2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input S-OE# directly controls the output stage. Setting the S-OE# at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting S-WE# at a high level and S-OE# at a low level while S-CE1# and S-CE2 are in an active state(S-CE1#=L,S-CE2=H).
When setting S-CE1# at a high level or S-CE2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a highimpedance state, allowing OR-tie with other chips and memory expansion by S-CE1# and S-CE2. The power supply current is reduced as low as the stand-by current which is specified as ICC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE S-CE1# S-CE2 S-WE# S-OE#
X H L L L L X H H H X X L H H X X X L H Mode Non selection Non selection Write Read DQ High impedance High impedance D IN D OUT High impedance Icc Standby Standby Active Active Active
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May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
ABSOLUTE MAXIMUM RATINGS
Symbol S-Vcc VI VO Pd Topr Tstg Parameter Supply voltage (SRAM) Inout voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings Unit
- 0.3*~4.6 - 0.3* ~ Vcc + 0.5
(Max 4.6)
V V V mW C C
0 ~ Vcc 700 -20 ~ 85 - 65 ~150
* -3.0V in case of AC (Pulse Width 30ns)
DC ELECTRICAL CHARACTERISRICS (Ta=-20~85C, Vcc=2.7V~3.6V, Unless otherwise noted) Symbol VIH VIL VOH1 VOH2 VOL II IO Icc1
Parameter
High-level input voltage Low-level input voltage High-level output voltage1 High-level output voltage2 Low-level output voltage Input current Output current in off-state Active supply current (MOS level input)
Test conditions
Limits
Min 2.0 Typ Max Vcc +0.3V 0.6
Unit
V V V V
IOH= -0.5mA IOH= -0.05mA IOL=2mA VI=0 ~ Vcc
S-CE1#=VIH or S-CE2=VIL or S-OE#=VIH VI/O=0 ~ Vcc S-CE1# 0.2V, S-CE2 S-Vcc-0.2V other inputs 0.2V or S-Vcc-0.2V Output-open(duty 100%) S-CE1#=VIL, S-CE2=VIH other inputs = VIH or VIL Output-open(duty 100%) 1) S-CE2 0.2V , other inputs = 0 ~ Vcc 2) S-CE1# Vcc-0.2V, S-CE2 Vcc-0.2V other inputs = 0 ~ Vcc S-CE1# = VIH or S-CE2 = VIL, other inputs = 0 ~ Vcc
-0.3 2.4 Vcc -0.5V
0.4 1 1 20 10 3 22 12 3 0.3 25 13 5 27 15 5 40 5 2 0.33
V A A mA
Icc2
Active supply current (TTL level input)
10MHz 5MHz 1MHz 10MHz 5MHz 1MHz -20~+85C -20~+40C +25C
mA
Icc3
Stand-by current
A
Icc4
Stand-by current
mA
* -3.0V in case of AC (Pulse Width 30ns)
CAPACITANCE ( Ta = -20 ~ 85C, Vcc = 2.7V ~ 3.6V, unless otherwise noted ) Symbol CI CO Parameter
Input capacitance Output capacitance
Test conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
Min
Limits Typ
Max 7 9
Unit pF pF
Note 1: Direction for current flowing into an IC is positive (no mark). 2: Typical value is Vcc = 3V, Ta = 25C 3: The value of common pins to Flash Memory is the sum of Flash Memory and SRAM.
16
May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
AC ELECTRICAL CHARACTERISTICS
(1) MEASUREMENT CONDITIONS
(Ta=-20 ~ 85C, Vcc=2.7V ~ 3.6V, unless otherwise noted)
1TTL DQ CL including scope and JIG
VCC ................................. 2.7V ~ 3.6V Input pulse level VIH=2.2V, VIL=0.4V Input rise and fall time ..... 5ns Reference level ............... VOH=VOL=1.5V Output loads ................... Fig.1,CL = 30pF CL = 5pF (for ten,tdis) Transition is measured 500mV from steady state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol tCR ta(A) ta(CE1) ta(CE2) ta(OE) tdis(CE1) tdis(CE2) tdis(OE) ten(CE1) ten(CE2) ten(OE) tV(A)
Parameter Read cycle time Address access time Chip select1 access time Chip select2 access time Output enable access time Output disable time after S-CE1# high Output disable time after S-CE2 low Output disable time after S-OE# high Output enable time after S-CE1# low Output enable time after S-CE2 high Output enable time after S-OE# low Data valid time after address
Limits Min 110 Max 110 110 110 55 40 40 40 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Symbol tCW tw(WE) tsu(A) tsu(A-WH) tsu(CE1) tsu(CE2) tsu(D) th(D) trec(WE) tdis(WE) tdis(OE) ten(WE) ten(OE)
Parameter Write cycle time Write pulse width Address setup time Address setup time with respect to S-WE# Chip select1 setup time Chip select2 setup time Data setup time Data hold time Write recovery time Output disable time from S-WE# low Output disable time from S-OEh# hig Output enable time from S-WE# high Output enable time from S-OE# low Min 110 85 0 100 100 100 45 0 0 5 5
Limits Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
40 40
17
May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
(4) TIMING DIAGRAMS Read Cycle
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
tCR
A0~17 ta(A) ta (CE1) S-CE1#
(Note 3)
tv (A)
tdis (CE1)
(Note 3)
S-CE2
(Note 3)
ta (CE2) ta (OE) ten (OE) tdis (CE2)
(Note 3)
S-OE#
(Note 3)
tdis (OE) ten (CE1) ten (CE2)
(Note 3)
DQ0-7
S-WE# = "H" level Write cycle (WE# control mode))
DATA VALID
tCW
A0~17 tsu (CE1) S-CE1#
(Note 3) (Note 3)
S-CE2
(Note 3)
tsu (CE2)
(Note 3)
tsu (A-WH) S-OE# tsu (A) S-WE# tdis (WE) tdis (OE) DQ0-7 ten (WE)
DATA IN STABLE
tw (WE)
trec (WE)
ten(OE)
tsu (D)
th (D)
18
May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
Write cycle (CE1# control mode)
tCW A0~17 tsu (A) S-CE1# tsu (CE1) trec (WE)
S-CE2
(Note 3) (Note 5) (Note 3)
S-WE#
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ0-7
Write cycle (CE2 control mode)
DATA IN STABLE
tCW A0~17
S-CE1#
(ic 3) tsu (A) (Note 3)
tsu (CE2)
trec (WE)
S-CE2
(Note 5)
S-WE#
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DQ0-7
DATA IN STABLE
Note 3: Hatching indicates the state is "don't care". 4: Writing is executed while S-CE2 high overlaps S-CE1# and S-WE# low. 5: When the falling edge of S-WE# is simultaneously or prior to the falling edge of S-CE1# or rising edge of S-CE2, the outputs are maintained in the high impedance state. 6: Don't apply inverted phase signal externally when DQ pin is output mode.
19
May.1998 , Rev.1.2
MITSUBISHI LSIs
PRELIMIN
ARY
M6MF16S2AVP
2097152-BIT (256k x 8-BIT) CMOS STATIC RAM
tion. al specifica ge. is is not a fin ect to chan Notice : Th its are subj lim parametric Some
POWER DOWN CHARACTERISTICS
(1) ELECTRIAL CHARACTERISTICS (Ta=-20 ~ 85C, unless otherwise noted) Limits Typ
Symbol
Vcc (PD) VI (CE1#) VI (CE2) Icc (PD)
Parameter
Power down supply voltage Chip select input S-CE1# Chip select input S-CE2 Power down supply current
Test conditions
Min
Max
Unit V V V
2 2.0 0.2
S-Vcc = 3V 1) S-CE2 0.2V, other input = 0 ~ Vcc 2) S-CE1# Vcc-0.2V,S-CE2 Vcc-0.2V other inputs = 0 ~ Vcc
-20~+85C -20~+40C +25C 0.3
30 3 1
A
(2) TIMING REQUIREMENTS Symbol tsu (PD) trec (PD)
(Ta=-20 ~ 85C, unless otherwise noted)
Paramwter
Power down set up time Power down recovery time
Test conditions
Min 0 5
Limits Typ
Max
Unit ns ms
(3) POWER DOWN CHARACTERISTICS
CE1# control mode
S-Vcc t su (PD)
2.2V 2.7V 2.7V
t rec (PD)
2.2V
S-CE1#
S-CE1# Vcc - 0.2V
CE2 control mode
S-Vcc S-CE2
0.2V S-CE2 0.2V
t su (PD)
2.7V
2.7V
t rec (PD)
0.2V
20
May.1998 , Rev.1.2

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