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| Under development CMOS 8-Bit Microcontroller TMP86FM48 TMP86FM48U/F The TMP86FM48 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including FLASH, RAM, multi-function timer/counter, serial interface (UART, HSIO, I2C), a 10-bit AD converter and two clock generators on chip. Product No. TMP86FM48U TMP86FM48F FLASH (Program Area) 32256 8 bits FLASH (Data Area) 512 8 bits RAM 2.0 K 8 bits Package P-LQFP64-1010-0.50 P-QFP64-1414-0.80A Emulation Chip *TMP86C948XB *: Under development Feautures 8-bit single chip microcomputer TLCS-870/C series Instruction execution time: 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) 132 types and 731 basic instructions 20 interrupt sources (External: 5, Internal: 15) Input/Output ports (54 pins) 16-bit timer counter: 2 ch Timer, Event counter, Pulse width measurement, External trigger timer, Window, PPG output modes 8-bit timer counter: 2 ch Timer, Event counter, PWM output, Programmable divider output, Capture modes Time Base Timer Divider output function TMP86FM48F P-QFP64-1414-0.80A TMP86FM48U P-LQFP64-1010-0.50 000707EBP1 For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 86FM48-1 2003-04-08 Under development Watchdog Timer Interrupt source/internal reset generate (programmable) Serial interface UART: 1ch (The function port for UART is also used as SIO function.) SIO: 2ch I2C bus: 1ch 10-bit successive approximation type AD converter Analog input: 16 ch Four Key-On Wake-Up pins Dual clock operation Single/Dual-clock mode Nine power saving operating modes STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/High-impedance. TMP86FM48 SLOW 1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz) IDLE 0 mode: IDLE 1 mode: IDLE 2 mode: SLEEP 0 mode: SLEEP 1 mode: SLEEP 2 mode: CPU stops, and peripherals operate using high-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting. CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. CPU stops, and peripherals operate using high and low frequency clock. Release by interruputs. CPU stops, and peripherals operate using low-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR TBTCK setting. CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. Wide operating voltage: 1.8 to 3.6 V at 8 MHz/32.768 kHz 2.7 to 3.6 V at 16 MHz/32.768 kHz 86FM48-2 2003-04-08 Pin Assignments (Top View) P-LQFP64-1010-0.50 P-QFP64-1414-0.80A P80 P81 P82 P83 P84 P85 P86 P87 P30 P31 P32 P33 P34 P35 P36 P37 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Under development 86FM48-3 (STOP/INT5) (SO2) (SI2) (SCK2) (PWM5/PDO5/TC5) (INT3/TC3) (TC1) P20 P10 P11 P12 P13 P14 P15 P16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AVDD VAREF AVSS/VASS BOOT P52 P51 ( DVO /SDA) P50 ( PPG /SCL) P07 ( SCK1 ) P06 (SO1/TXD) P05 (SI1/RXD) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P17 P77(AIN17) P76 (AIN16) P75 (AIN15) P74 (AIN14) P73 (AIN13) P72 (AIN12) P71 (AIN11) P70 (AIN10) P67 (AIN07/STOP3) P66 (AIN06/STOP2) P65 (AIN05/STOP1) P64 (AIN04/STOP0) P63 (AIN03) P62 (AIN02) P61 (AIN01) P60 (AIN00) TMP86FM48 2003-04-08 Under development Block Diagram TMP86FM48 I/O ports P87 to P80 P37 to P30 P8 Power supply VDD VSS P3 Address/Data bus Reset Input TEST pin RESET TLCS-870/C CPU System control circuit Standby control circuit (Key-on wake-up) Timing generator Data memory (RAM) Program memory (FLASH) Data memory (FLASH) I2C TEST Interrupt controller Resonator connecting pins Time base timer XIN XOUT High frequency Clock generator Low frequency 16-bit timer/counter TC1 TC2 8-bit timer/counter TC3 TC5 HSIO UART SIO2 SIO1 Watchdog timer Address/Data bus P2 P7 P6 P1 P0 P5 10-bit AD converter P22 to P20 P77 (AIN17) to P70 (AIN10) I/O ports AVDD VAREF AVSS/VASS P67 (AIN07) P17 to P10 to P60 (AIN00) I/O ports P07 to P00 P52 to P50 Analog reference pins 86FM48-4 2003-04-08 Under development Pin Functions (1/2) Pin Name P07 ( SCK1 ) P06 (TXD, SO1) P05 (RXD, SI1) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P17 P16 P15 (TC1) P14 (TC3,INT3) P13 ( PWM5 , PDO5 , TC5) P12 ( SCK2 ) P11 (SI2) P10 (SO2) P22 (XTOUT) P21 (XTIN) P20 ( INT5 , STOP ) TMP86FM48 Input/Output I/O (I/O) I/O (Output) I/O (Input) I/O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O I/O I/O (Input) I/O (Input) I/O (I/O) I/O (I/O) I/O (Input) I/O (Output) I/O (Output) I/O (Input) I/O (Input) Functions 8-bit input/output port with latch. When used as a serial interface output or UART output, respective output latch (P0DR) should be set to "1". When used as an input port, an serial interface input, UART input, timer counter input or an external interrupt input, respective output control (P0OUTCR) should be cleared to "0" after setting P0DR to "1". 8-bit input/output port with latch. When used as a timer/counter output or serial interface output, respective output latch (P1DR) should be set to "1". When used as an input port, a timer counter input, an external interrupt input or serial interface input, respective output control (P1OUTCR) should be cleared to "0" after setting P1DR to "1". Serial clock input/output 1 UART data output, Serial data output 1 UART data input, Serial data input 1 Timer counter 2 input External interrupt 2 input External interrupt 1 input External interrupt 0 input Timer counter 1 input Timer counter 3 input, External interrupt 3 input PWM5 output, PDO5 output, Timer/counter 5 input Serial clock input/output 2 Serial data input 2 Serial data output 2 3-bit input/output port with latch. When used as an input port or an external interrupt input, respective output control (P2OUTCR) should be cleared to "0" after setting output latch (P2DR) to "1". 8-bit input/output port with latch (Nch high current output). When used as an input port, respective output control (P3OUTCR) should be cleared to "0" after setting output latch (P3DR) to "1". 3-bit input/output port with latch (Nch high current output). When used as an input port or I2C-bus interface input/output, respective output control (P5OUTCR) should be cleared to "0" after setting output latch (P5DR) to "1". When used as a PPG output or divider output, respective P5DR should be set to "1". 8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P6CR1) should be cleared to "0" after setting input control (P6CR2) to "1". When used as an analog input or key on wake up input, respective P6CR1 should be cleared to "0" after clearing P6CR2 to "0". When used as a key on wake up input, STOPCR P37 to P30 I/O P52 I/O P51 ( DVO , SDA) I/O (Output,I/O) Divider Output/I2C bus serial data input/output PPG Output/I2C bus serial clock input/output STOP 3 input STOP 2 input STOP 1 input STOP 0 input AD converter analog inputs P50 ( PPG , SCL) P67 (AIN07, STOP3) P66 (AIN06, STOP2) P65 (AIN05, STOP1) P64 (AIN04, STOP0) P63 (AIN03) P62 (AIN02) P61 (AIN01) P60 (AIN00) I/O (Output,I/O) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) 86FM48-5 2003-04-08 Under development Pin Functions (2/2) Pin Name P77 (AIN17) P76 (AIN16) P75 (AIN15) P74 (AIN14) P73 (AIN13) P72 (AIN12) P71 (AIN11) P70 (AIN10) TMP86FM48 Input/Output I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) Functions 8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P7CR1) should be cleared to "0" after setting input control (P7CR2) to "1". When used as an analog input, respective P7CR1 should be cleared to "0" after clearing P7CR2 to "0". 8-bit input/output port with latch (Nch high current output). When used as an input port, respective output control (P8OUTCR) should be cleared to "0" after setting output latch (P8DR) to "1". Pin Name AD converter analog inputs P87 to P80 I/O XIN, XOUT RESET Input Output Input Input Input Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. Reset signal input Test pin for out-going test. Be fixed to low. Serial prom mode control input. When writing to FLASH memory, BOOT pin should be fixed to High level. Power supply for operation TEST BOOT VDD, VSS VAREF AVDD AVSS/VASS Power Supply Analog reference voltage for AD conversion AD circuit power supply AD circuit power supply/Analog reference GND for AD conversion 86FM48-6 2003-04-08 Under development TMP86FM48 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86FM48 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data Buffer Register) and SFR (Special Function Register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FM48 memory address map. The general-purpose registers are not assigned to the RAM address space. 0000H SFR 003FH 0040H 64 bytes FLASH memory: FLASH memory includes: Program memory (The area of 8000H to 81FFH can be used as data memory.) Vector table BOOT ROM: FLASH writing program RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers RAM 083FH 1F80H DBR 1FFFH 3800H BOOT ROM 3FFFH FLASH memory (Data memory) 8000H 81FFH 8200H 2048 bytes 128 bytes 2048 bytes 512 bytes 32176 bytes FLASH memory (Program memory) FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes 32 bytes 32 bytes Vector table for interrupts (8 vectors) Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors) Figure 1.1.1 Memory Address Maps 1.2 Program Memory (FLASH) The TMP86FM48 has a 32 K 8 bits (address 8000H to FFFFH) of program memory (FLASH). The area of 8000H to 81FFH can be used as a 512 8 bits data memory of FLASH. However, placing program memory on the internal RAM is deregulated if a certain procedure is executed (See 2.4.5 Address Trap). For details of FLASH memory, refer to section "2.16 FLASH memory". 86FM48-7 2003-04-08 Under development Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Output current (Per 1 pin) TMP86FM48 (VSS 0 V) Pins Rating 0.3 to 4.0 0.3 to VDD 0.3 to VDD P0, P1, P20, P3, P5, P6, P7, P8 Ports P0, P1, P2, P4, P6, P7, P8, Ports P3, P5 Ports P0, P1, P20, P3, P5, P6, P7, P8 Ports P0, P1, P2, P4, P6, P7, P8, Ports P3, P5 Ports 2 2 10 80 80 30 350 260 (10 s) 55 to 125 40 to 85 C mW mA 0.3 0.3 V Symbol VDD VIN VOUT1 IOUT1 IOUT2 IOUT3 IOUT1 Unit Output current (Total) Power dissipation [Topr Storage temperature Operating temperature 85C] IOUT2 IOUT3 PD Tsld Tstg Topr Soldering temperature (time) Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 86FM48-192 2003-04-08 Under development TMP86FM48 Recommended Operating Condition-1 (MCU mode) Parameter Symbol Pins fc fc (VSS 0 V, Topr 40 to 85C) Min 2.7 1.8 Condition 16 MHz 8 MHz NORMAL1, 2 mode IDLE0, 1, 2 mode NORMAL1, 2 mode IDLE0, 1, 2 mode SLOW1, 2 mode SLEEP0, 1, 2 mode STOP mode Max Unit Supply voltage VDD 3.6 fs 32.768 kHz VIH1 Input high level VIH2 VIH3 VIL1 Input low level VIL2 VIL3 Clock frequency fc fs XIN, XOUT XTIN, XTOUT Except Hysteresis input Hysteresis input Except Hysteresis input Hysteresis input 1.8 V VDD VDD VDD 0 0.70 0.75 0.90 VDD VDD VDD 1.0 30.0 0.30 0.25 0.10 MHz kHz VDD VDD VDD VDD VDD VDD VDD VDD 2.7 V 2.7 V 2.7 V 2.7 V 1.8 to 3.6 V 2.7 to 3.6 V 1.8 to 3.6 V 8.0 16.0 34.0 Note: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. (VSS 0 V, Topr 25C 5C) Max 3.6 Recommended Operating Condition-2 (Serial PROM mode) Parameter Supply voltage Symbol VDD Pins 2 MHz Condition fc 16 MHz Min 2.7 Unit V Clock frequency fc XIN, XOUT VDD 2.7 to 3.6 V 2.0 16.0 MHz Note: The operating temperature area of serial PROM mode is 25C frequency of serial PROM mode is different from MCU mode. 5C and the operating area of high 86FM48-193 2003-04-08 Under development DC Characteristics Parameter Hysteresis voltage TMP86FM48 (VSS 0 V, Topr Pins Hysteresis input TEST 40 to 85C) Condition VDD VDD 3.3 V 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V 3.6 V 3.6 V 3.4V/0.2 V 3.6 V, lOH 3.6 V, IOL 3.6 V, VOL 3.6 V 3.4 V/0.2 V 16 MHz 32.768 kHz 0.6 mA 0.9 mA 1.0 V MNP VDD RAM Area VIN fc fs Flash Area RAM Area VDD VIN fs 3.6 V MNP MNP "1" "0" "1" "1" "0" 6 T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. "1" "0" "1" "0" T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. A mA 3.2 0.4 V mA 0V 3.6 V/0 V 3.6 V 3.6 V 3.6 V 0V 100 70 70 220 1.2 M 14 10 A 450 k Symbol VHS IIN1 Min Typ. 0.4 Max 5 5 5 Unit V Input current IIN2 IIN3 RIN1 RIN2 RIN3 Sink Open Drain, Tri-state VDD RESET A VDD VDD VDD VDD VDD VDD VDD VOUT VDD TEST Pull-down BOOT Pull-down RESET Pull-Up Input resistance P21, P22 Ports XOUT XTOUT Sink Open Drain, Tri-state C-MOS, Tri-state High frequency feedback resister Low frequency feedback resister Output leakage current Output high voltage Output low voltage Output low current Supply current in NORMAL 1, 2 mode Supply current in IDLE 0, 1, 2 mode Supply current in SLOW 1 mode Supply current in SLEEP 1 mode Supply current in SLEEP 0 mode Supply current in STOP mode RFB RFBT ILO VOH VOL IOL Except XOUT, P3 and P5 VDD Ports P3, P5 Ports Flash Area Fetch area VDD MNP*ATP MNP*ATP MNP MNP MNP "1" "0" "1" IDD Fetch area 3.4 V/0.2 V MNP*ATP 32.768 kHz MNP*ATP MNP*ATP MNP*ATP VDD VIN 3.6 V 3.4 V/0.2 V Note 1: Typical values show those at Topr 25C. Note 2: Input current (IIN1, IIN2): The current through pull-up or pull-down resistor is not included. Note 3: IDD does not include IREF current. Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE 0, 1, 2. Note 5: MNP(MNPWDW) shows bit0 in EEPCR register and ATP(ATPWDW) shows bit1 in EEPCR register. Note 6: "Fetch" means reading operation of FLASH data as an instruction by CPU. 86FM48-194 2003-04-08 Under development AD Conversion Characteristics Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error TMP86FM48 3.6 V, Topr Min AVDD 1.0 VDD V 2.5 VSS VAREF T.B.D. T.B.D. 2 2 2 2 mA (VSS 0.0 V, 2.7 V Condition VDD 40 to 85C) Typ. Max AVDD Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit AVDD 0.0 V AVDD 0.0 V 2.7 V VAREF 3.6 V 2.7 V LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error 0.0 V, 2.0 V Condition VDD 2.7 V, Topr Min AVDD 0.6 40 to 85C) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit 2.0 VSS AVDD 0.0 V AVDD 0.0 V 2.0 V 2.0 V VAREF 2.0V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage non linearity error Zero point error Full scale error Total error 0.0 V, 1.8 V Condition VDD 2.0 V, Topr Min AVDD 0.1 10 to 85C) (Note 5) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit 1.8 VSS AVDD 0.0 V AVDD 0.0 V 1.8 V 1.8 V VAREF 1.8 V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to "2.15.2 Register configration". Note 3: Please use input voltage to AIN input Pin in limit of VAREF VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog Reference Voltage Range: VAREF VAREF VSS Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage. Note 6: When AD converter is not used, fix the AVDD pin and VAREFpin on the VDD level. 86FM48-195 2003-04-08 Under development AC Characteristics Parameter (VSS 0 V, VDD 2.7 to 3.6 V, Topr Condition NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High Level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input), fc 16 MHz For external clock operation (XTIN input), fs 32.768 kHz TMP86FM48 40 to 85C) Min 0.25 117.6 31.25 15.26 Symbol Typ. Max 4 Unit s 133.3 ns s (VSS Parameter 0 V, VDD 1.8 to 3.6 V, Topr Condition 40 to 85C) Min 0.5 117.6 62.5 15.26 Symbol Typ. Max 4 Unit NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input), fc 8 MHz For external clock operation (XTIN input), fs 32.768 kHz s 133.3 ns s Flash Characteristics Parameter (VSS 0 V) Condition fc 16 MHz Min Typ. Max T.B.D Unit Number of guaranteed writes (page VDD 2.7 to 3.6 V, 2 MHz writing) to Flash memory in serial PROM (Topr 25C 5C) mode Number of guaranteed writes (page writing) to Flash data memory in MCU mode Writing time to Flash data memory for one page (64 bytes) in MCU mode VDD VDD (Topr 1.8 to 3.6 V at fc 2.7 to 3.6 V at fc 40 to 85C) Times 8 MHz 16 MHz T.B.D ms T.B.D Recommended Oscillating Conditions Note 1: An electrical shield by metal shield plate on the surface of IC package is recommended in order to protect the device from the high electric field stress applied from CRT (Cathodic Ray Tube) for continuous reliable operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following http://www.murata.co.jp/search/index.html 86FM48-196 2003-04-08 |
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