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| 3 mm x 5 mm www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 16-BIT, LOW POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER FEATURES * * * * * * * * * * * * * Micropower Operation: 160 A @ 5 V Power-On Reset to Zero Single Supply: +2.7 V to +5.5 V 16-Bit Monotonic Settling Time: 10 s to 0.003% FSR I2CTM Interface With High-Speed Mode Supports Data Receive and Transmit On-Chip Rail-to-Rail Output Buffer Double-Buffered Input Register Supports Synchronous Multichannel Update Offset Error: 1 mV max at 25C Full-Scale Error: 3 mV max at 25C Small 8 Lead MSOP Package DESCRIPTION The DAC8571 is a small low-power, 16-bit voltage output DAC with an I2C compatible two-wire serial interface. Its on-chip precision output amplifier allows rail-to-rail output swing and settles within 10 microseconds. The DAC8571 architecture is 16-bit monotonic, and factory trimming typically achieves 4 mV absolute accuracy at all codes. The DAC8571 requires an external reference voltage to set its output voltage range. The low power consumption and small size of this part make it ideally suited to portable battery operated equipment. The power consumption is typically 800 W at VDD = 5 V reducing to 1 W in power-down mode. The DAC8571 incorporates a 2-wire I2C interface. Standard, fast, and high-speed modes of I2C operation are all supported up to 3.4 MHz serial clock speeds. Multichannel synchronous data update and power-down operations are supported through the I2C bus. DAC8571 is also capable of transmitting the contents of its serial shift register, a key feature for I2C system verification. The DAC8571 is available in an 8-lead MSOP package and is specified over -40C to 105C. APPLICATIONS * * * * * Process Control Data Acquisition Systems Closed-Loop Servo Control PC Peripherals Portable Instrumentation VREF V(SENSE) _ Ref + 16 Bit DAC VDD 16 + VOUT DAC Register Temporary Register SDA SCL A0 I2C Block Power Down Control Logic Resistor Network GND I2C is a trademark of Philips Corporation. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002 - 2003, Texas Instruments Incorporated DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com PIN CONFIGURATIONS VDD VREF V(SENSE) VOUT 1 2 3 4 8 7 6 5 GND SDA SCL A0 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Name VDD VREF V(SENSE) VOUT A0 SCL SDA GND Function Analog voltage supply input Positive reference voltage input Analog output sense Analog output voltage from DAC Device address select Serial clock input Serial data input/output Ground reference point for all circuitry on the part 2 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION Product DAC8571 Package 8-MSOP Package Designator DGK Specified Temperature Range -40C to +105C Package Marking D871 Ordering Number DAC8571IDGK DAC8571IDGKR Transport Media, Quantity Tube, 80 Tape & Reel, 2500 ABSOLUTE MAXIMUM RATINGS (1) DAC8571 VDD to GND Digital input voltage to GND VOUT to GND Operating temperature range Storage temperature range Junction temperature range (TJmax) JAThermal impedance JCThermal impedance Lead temperature, soldering Vapor phase (60s) Infrared (15s) (1) -0.3 V to +6 V -0.3V to VDD + 0.3V -0.3V to +VDD + 0.3V -40C to + 105C -65C to +150C + 150C 260C/W 44C/W 215C 220C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; low power mode; all specifications -40C to 105C (unless otherwise noted) DAC8571 PARAMETER STATIC PERFORMANCE (1) Resolution Relative accuracy Differential nonlinearity Offset error Full-scale error Gain error Zero code error drift Gain temperature coefficient Absolute accuracy All codes from code 485 to code 64714, 25C All codes from code 485 to code 64714, -40C...105C Monotonic by design Measured at code 485, 25C Measured at code 485, -40C...105C Measured at code 64714, 25C Measured at code 64714, -40C...105C Measured at code 64714, 25C Measured at code 64714, -40C...105C All zeroes loaded to DAC register 0.25 0.3 1.0 0.5 1.0 1.0 2.0 -20 -5 2.5 3.5 16 0.098 1 1.0 5.0 3.0 5.0 3.0 5.0 V/C ppm of FSR/C mV mV mV Bits % of FSR LSB mV CONDITIONS MIN TYP MAX UNITS (1) Linearity calculated using a reduced code range of 485 to 64714. Output unloaded. 3 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; RL = 2 k to GND; CL = 200 pF to GND; low power mode; all specifications -40C to 105C (unless otherwise noted) DAC8571 PARAMETER OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time (full scale) RL = 2 k; CL < 200 pF, fast settling RL = 2 k; CL = 500 pF, fast settling RL = 2 k; CL < 200 pF, low power Slew rate Capacitive load stability Digital-to-analog glitch impulse Digital feedthrough DC output impedance Short circuit current Power-up time PSRR REFERENCE INPUT VREFH input range Reference input impedance LOGIC INPUTS (3) Input current VIN_L, Input low voltage VIN_H0 , Input high voltage Pin capacitance POWER REQUIREMENTS VDD IDD (normal operation) VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V IDD (all power-down modes) VDD = +4.5 V to +5.5 V VDD = +2.7 V to +3.6 V POWER EFFICIENCY IOUT/IDD (2) (3) IL = 2 mA, VDD = +5 V 93% DAC active, Iref included VIH = VDD, VIL = GND, fast settling VIH = VDD, VIL = GND, low power VIH = VDD, VIL = GND, fast settling VIH = VDD, VIL = GND, low power DAC active, Iref included VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.05 1 1 A A 250 160 240 140 400 225 380 200 A A 2.7 5.5 V VDD = 2.7-5.5 V VDD = 2.7-5.5 V 0.7VDD 3 0 140 1 0.3VDD VDD V k A V V pF VDD = +5 V VDD = +3 V Coming out of power-down mode, VDD = +5 V Coming out of power-down mode, VDD = +3 V RL = 2 k; CL < 200 pF, fast settling RL = 2 k; CL < 200 pF, low power RL = RL = 2 k 0 8 12 13 1 0.5 470 1000 20 0.5 1 50 20 2.5 5 0.75 pF pF nV-s nV-s mA mA s s mV/V 15 VREF 10 V s s s V/s CONDITIONS MIN TYP MAX UNITS Assured by design and characterization, not production tested. Assured by design and characterization, not production tested. 4 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 TIMING CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 k to GND; all specifications -40C to 105C (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS Standard mode tSCL SCL clock frequency Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max tBUF Bus free time between a STOP and START condition Hold time (repeated) START condition Standard mode Fast mode Standard mode tHO; tSTA Fast mode High-speed mode tLOW LOW period of the SCL clock Standard mode Fast mode Standard mode tHIGH HIGH period of the SCL clock Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tSU; tSTA Setup time for a repeated START condition Fast mode High-speed mode Standard mode tSU; tDAT Data setup time Fast mode High-speed mode Standard mode tHD; tDAT Data hold time Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tRCL Rise time of SCL signal Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tRCL1 Rise time of SCL signal after a repeated START condition, and after an acknowledge BIT Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tFCL Fall time of SCL signal Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tRCA Rise time of SDA signal Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max Standard mode tFDA Fall time of SDA signal Fast mode High-speed mode, CB - 100pF max High-speed mode, CB - 400pF max 4.7 1.3 4.0 600 160 4.7 1.3 4.0 600 60 120 4.7 600 160 250 100 10 0 0 0 0 20 x 0.1CB 20 x 0.1CB 10 20 20 x 0.1CB 20 x 0.1CB 10 20 20 x 0.1CB 20 x 0.1CB 10 20 20 x 0.1CB 20 x 0.1CB 10 20 20 x 0.1CB 20 x 0.1CB 10 20 0.9 0.9 70 150 1000 300 40 80 1000 300 80 1600 300 300 40 80 1000 300 80 160 300 300 80 160 MIN TYP MAX 100 400 3.4 1.7 UNITS kHz kHz MHz MHz s s \s ns ns s s s ns ns ns s ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com TIMING CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; RL = 2 k to GND; all specifications -40C to 105C (unless otherwise noted) SYMBOL tSU; tSTO CB tSP PARAMETER Setup time for STOP condition Capacitive load for SDA and SCL Pulse width of spike suppressed Noise margin at the HIGH level for each connected device (including hysteresis) Noise margin at the LOW level for each connected device (including hysteresis) Fast mode High-speed mode Standard mode Fast mode High-speed mode Standard mode Fast mode High-speed mode 0.1VDO V 0.2VDO V TEST CONDITIONS Standard mode Fast mode High-speed mode MIN 4.0 600 160 400 50 10 TYP MAX UNITS s ns ns pF ns ns VNH VNL 6 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 TYPICAL CHARACTERISTICS At TA = +25C, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 Linearity Error - LSB 32 16 DLE - LSB DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 0 -16 -32 -48 -64 0 10000 20000 30000 40000 50000 60000 Digital Input Code - 0.8 -1 0 10000 20000 30000 40000 Digital Input Code 50000 60000 Figure 1. ERROR vs TEMPERATURE 3 2 Error - mV 1 0 -1 -2 -3 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C Gain Zero-Scale Full-Scale VDD = 5 V 2 Error - mV 1 Gain 0 -1 -2 -3 -40 -20 0 3 Figure 2. ERROR vs TEMPERATURE VDD = 3 V Full-Scale Zero-Scale 20 40 60 80 100 TA - Free-Air Temperature - C Figure 3. LINEARITY ERROR vs TEMPERATURE 64 Differential Linearity Error - LSB Figure 4. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1 - 40 MIN Error MAX Error 48 Linearity Error - LSB 32 16 0 - 16 - 32 - 48 - 64 - 40 MAX Error MIN Error 0 40 80 TA - Free-Air Temperature - C 110 0 40 TA - Free-Air Temperature - C 80 110 Figure 5. Figure 6. 7 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. SINK CURRENT AT NEGATIVE RAIL 0.15 VOUT - Output Voltage - V VOUT - Output Voltage - V 0.125 0.1 VDD = 5 V 0.075 0.05 0.025 0 0 1 2 3 4 5 ISINK - Sink Current - mA VREF = VDD - 10 mV DAC Loaded With 0000 H 5 SOURCE CURRENT AT POSITIVE RAIL VDD = 2.7 V 4.95 4.9 4.85 VREF = VDD - 10 mV DAC Loaded With FFFFH VDD = 5 V 0 1 2 3 4 5 4.8 ISOURCE - Source Current - mA Figure 7. SOURCE CURRENT AT POSITIVE RAIL 2.7 VOUT - Output Voltage - V IDD - Supply Current - A 250 200 150 Figure 8. SUPPLY CURRENT vs DIGITAL INPUT CODE 2.65 VDD = 5 V 2.6 VDD = 3.6 V 100 50 Reference Current Included 0 2.55 VREF = VDD - 10 mV DAC Loaded With FFFFH VDD = 2.7 V 0 1 2 3 4 5 2.5 ISOURCE - Source Current - mA 0 10000 20000 30000 40000 50000 60000 Digital Input Code Figure 9. SUPPLY CURRENT vs TEMPERATURE 250 IREF Included IDD - Supply Current - A 200 150 VDD = 3.6 V 100 50 0 -40 -20 0 20 40 60 80 100 TA - Free-Air Temperature - C Figure 10. SUPPLY CURRENT vs SUPPLY VOLTAGE 140 IDD - Supply Current - A 120 100 80 60 40 20 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD - Supply Voltage - V VREF = VDD, IDD Measured at Power-Up, Reference Current Included, No Load VDD = 5.5 V Figure 11. Figure 12. 8 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1 0.9 IDD - Supply Current - mA 0.8 f - Frequency 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 Logic Input Voltage - V 0 0 40 80 120 160 200 240 280 IDD - Supply Current - A 500 VDD = VREF = 2.7 V VDD = VREF = 5.5 V TA = 25C, A0 Input (All Other Inputs = GND) Reference Current Included HISTOGRAM OF CURRENT CONSUMPTION 2500 IREF Included 2000 VDD = 2.7 V 1500 1000 VDD = 5.5 V Figure 13. EXITING POWER-DOWN MODE 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 t - Time - 5s/div 2.5 Figure 14. OUTPUT GLITCH (Mid-Scale) VOUT - Output Voltage - V V (V, 50 mV/div) O 2.45 2.4 Vref = VDD - 50 mV Code 7FFFh to 8000h (Glitch Occurs Every N x 4096 Code Boundary) 2.3 2.35 0 5 10 15 t - Time - S 20 25 30 Figure 15. ABSOLUTE ERROR 0.005 0.004 Total Unadjusted Error - V 0.003 0.002 0.001 0 -0.001 -0.002 -0.003 -0.004 -0.005 0 10000 20000 30000 40000 50000 60000 Digital Input Code 0 Figure 16. FULL-SCALE SETTLING TIME (Large Signal) 6 VDD = 5 V VOUT - Output Voltage - V 5 4 3 2 1 VDD = VREF =5V Output Loaded With 2 k and 200 pF to GND t - Time - 12s/div, Fast-Settling Mode Figure 17. Figure 18. 9 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. HALF-SCALE SETTLING TIME (Large Signal) 3.0 VOUT - Output Voltage - V VOUT - Output Voltage - V 2.5 2.0 1.5 1.0 0.5 0.0 t - Time - 12s/div, Fast-Settling Mode VDD = VREF =5V Output Loaded With 2 k and 200 pF to GND FULL-SCALE SETTLING TIME (Large Signal) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t - Time - 12s/div, Fast-Settling Mode VDD = VREF = 2.7 V Output Loaded With 2 k and 200 pF to GND Figure 19. HALF-SCALE SETTLING TIME 1.50 98 Figure 20. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY VOUT - Output Voltage - V 96 VDD = 5V 94 1.00 0.50 VDD = VREF = 2.7 V Output Loaded With 2 k and 200 pF to GND t - Time - 12s/div, Fast-Settling Mode SNR (dB) 92 VDD = 2.7V 90 88 86 84 0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k 4.5k Output Frequency (Hz), Fast-Settling Mode VDD = VREF -1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz 0.00 Figure 21. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY OUTPUT FREQUENCY VDD = VREF = 5V FS = 52ksps, - 1dB FSR Digital Input Measurement Bandwidth = 20kHz Figure 22. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 0 - 10 - 20 - 30 THD (dB) - 40 - 50 - 60 - 70 THD VDD = VREF = 2.7V FS = 52ksps, - 1dB FSR Digital Input Measurement Bandwidth = 20kHz 0 - 10 - 20 - 30 THD (dB) - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k Output Frequency (Hz), Fast-Settling Mode THD 3rd Harmonic 2nd Harmonic - 80 - 90 - 100 0 500 1k 1.5k 2k 2.5k 3k 3.5k 4k Output Frequency (Hz), Fast - Settling Mode 2nd Harmonic 3rd Harmonic Figure 23. Figure 24. 10 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. FULL-SCALE SETTLING TIME (Small-Signal-Positive Going Step) FULL-SCALE SETTLING TIME (Small-Signal-Negative Going Step) Output Voltage Output Voltage Small-Signal Settling Time 5mV/div Small-Signal Settling Time 5mV/div Trigger Signal Trigger Signal Time (2s/div) Time (2s/div) Figure 25. Figure 26. 11 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION D/A SECTION The architecture of the DAC8571 consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture. Reference Voltage V(SENSE) Ref+ Resistor String RefGND _ + VOUT DAC Register Figure 27. DAC8571 Architecture The input coding to the DAC8571 is unsigned binary, which gives the ideal output voltage as: D V OUT + VREF 65536 (1) where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. RESISTOR STRING The resistor string section is shown in Figure 28. It is simply a divide-by-two resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is assured monotonic. VREF R To Output Amplifier R R R GND Figure 28. Resistor String. 12 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) Output Amplifier The output buffer is a gain-of-2 noninverting amplifier capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities (fast settling) of the output amplifier can be seen in the typical curves. The slew rate is 1 V/s with a full-scale settling time of 10 s with the output loaded. The feedback and gain setting resistors of the amplifier are in the order of 50 k. Their absolute value can be off significantly, but they are matched to within 0.1%. The inverting input of the output amplifier is brought out to the VSENSE pin, through the feedback resistor. This allows for better accuracy in critical applications by tying the VSENSE point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications including current sourcing. I2C Interface The DAC8571 uses the I2C interface (see I2C-Bus Specification Version 2.1, January 2000, Philips Semiconductor) to receive and transmit digital data. I2C is a 2-wire serial interface that allows multiple devices on the same bus to communicate with each other. The serial bus consists of the serial data (SDA) and serial clock (SCL) lines. Connections to the SDA and SCL lines of the bus are made through open drain IO pins of each device on the bus. Since the devices that connect to the bus have open drain outputs, the bus should include pullup structures. When the bus is not active, both SCL and SDA lines are pulled high by these pullup devices. The DAC8571 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard (100 Kbps), fast (400 kBps), and high speed (3.4 Mbps). I2C specification states that the device that controls the message is called a master, and the devices that are controlled by the master are slaves. The master device generates the SCL signal. A master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is also done by the master. The master device on an I2C bus is usually a microcontroller or a digital signal processor (DSP). The DAC8571 on the other hand, operates as a slave device on the I2C bus. A slave device acknowledges master's commands and upon master's control, either receives or transmits data. I2C specification states that a device that sends data onto the bus is defined as a transmitter, and a device receiving data from the bus is defined as a receiver. DAC8571 normally operates as a slave receiver. A master device writes to DAC8571, a slave receiver. However, if a master device inquires DAC8571 internal register data, DAC8571, operates as a slave transmitter. In this case, the master device reads from the DAC8571, a slave transmitter. According to I2C terminology, read and write are with respect to the master device. Other than specific timing signals, I2C interface works with serial bytes. At the end of each byte, a 9th clock cycle is used to generate/detect an acknowledge signal. An acknowledge is when the SDA line is pulled low during the high period of 9th clock cycle. A not-acknowledge is when SDA line is left high during the high period of the 9th clock cycle. SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 29. Valid Data 13 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master S START Condition 1 2 8 9 Clock Pulse for Acknowledgement Figure 30. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA MSB Address Acknowledgement Signal From Slave Recognize STOP or REPEATED START Condition Sr R/W SCL S or Sr START or Repeated START Condition 1 2 7 8 9 ACK 1 2 3-8 9 ACK Sr or P Clock Line Held Low While Interrupts are Serviced STOP or Repeated START Condition Figure 31. Bus Protocol 14 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) Master Writing to a Slave Receiver (Standard/Fast Modes) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master. After the start condition, the master generates the serial clock pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid data. For each valid I2C bit, SDA line should remain stable during the entire high period of the SCL line. The address byte consists of 7 address bits (1001100, assuming A0=0) and a direction bit (R/W=0). After sending the address byte, the master generates a 9th SCL pulse and monitors the state of the SDA line during the high period of this 9th clock cycle. The SDA line being pulled low by a receiver during the high period of 9th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent. Upon the receipt of this acknowledge, the master knows that the communication link with a DAC8571 has been established and more data could be sent. The master continues by sending a control byte C<7:0>, which sets DAC8571's operation mode. After sending the control byte, the master expects an acknowledge signal. Upon receipt of the acknowledge, the master sends a most significant byte M<7:0> that represents the eight most significant bits of DAC8571's 16-bit digital-to-analog conversion data. Upon receipt of the M<7:0>, DAC8571 sends an acknowledge. After receiving the acknowledge, the master sends a least significant byte L<7:0> that represents the eight least significant bits of DAC8571's 16-bit conversion data. After receiving the L<7:0>, the DAC8571 sends an acknowledge. At the falling edge of the acknowledge signal following the L<0>, DAC8571 performs a digital to analog conversion. For further DAC updates, the master can keep repeating M<7:0> and L<7:0> sequences, expecting an acknowledge after each byte. After the required number of digital-to-analog conversions is complete, the master can break the communication link with DAC8571 by pulling the SDA line from low to high while SCL line is high. This is called a stop condition. A stop condition brings the bus back to idle (SDA and SCL both high). A stop condition indicates that communication with DAC8571 has ended. All devices on the bus including DAC8571 then await a new start condition followed by a matching address byte. DAC8571 stays at its current state upon receipt of a stop condition. Table 1 demonstrates the sequence of events that should occur while a master transmitter is writing to DAC8571. 15 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) Table 1. Master Transmitter Writing to Slave Receiver (DAC8571) Standard/Fast Mode Write Sequence - Data Input Transmitter Master Master DAC8571 Master DAC8571 Master DAC8571 Master DAC8571 Master Transmitter Master Master DAC8571 Master DAC8571 Master DAC8571 Master DAC8571 Master (1) (2) (3) (4) 0 0 0 PD1 PD2 PD3 0 0 Load 1 1 0 0 1 Load 0 0 0 MSB 6 5 D7 D6 D5 D15 D14 D13 0 0 Load 1 1 0 0 1 Load 0 D12 D4 MSB 6 5 4 Start 1 0 D11 D3 A0 Brcsel D10 D2 0 0 D9 D1 R/W PD0 D8 D0 DAC8571 Acknowledges Control byte (PD0=0) Writing dataword, high byte Writing dataword, low byte Done 1 0 0 0 0 LSB R/W PD0 0 0 Comment Begin sequence 1 0 0 0 A0 Brcsel 0 0 Write addressing (LSB=0) Control byte (PD0=1) Writing dataword, high byte Writing dataword, low byte Done DAC8571 Acknowledges DAC8571 Acknowledges DAC8571 Acknowledges Stop or Repeated Start (1) (2) 4 Start DAC8571 Acknowledges DAC8571 Acknowledges DAC8571 Acknowledges DAC8571 Acknowledges Stop or Repeated Start (3) (4) 3 2 3 2 1 LSB Comment Begin sequence Write addressing (LSB=0) Standard/Fast Mode Write Sequence-Power Down Input High byte, low byte sequence can repeat. Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. High byte, low byte sequence can repeat. Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. 16 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) Master Reading From a Slave Transmitter (Standard/Fast Modes) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master. After the start condition, the master generates the serial clock pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid data. For each valid I2C bit, SDA line should remain stable during the entire high period of the SCL line. The address byte consists of seven address bits (1001100, assuming A0=0) and a direction bit (R/W=1). After sending the address byte, the master generates a 9th SCL pulse and monitors the state of the SDA line during the high period of this 9th clock cycle (master leaves the SDA line high). The SDA line being pulled low by a receiver during the high period of 9th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent. Since the R/W bit in the address byte was set, master also knows that DAC8571 is ready to transmit data. Upon the receipt of this acknowledge, the master knows that the communication link with a DAC8571 has been established and more data could be received. The master continues by sending eight clock cycles during which DAC8571 transmits a most significant byte, M<7:0>. If the master detects all bits of the M<7:0> as valid data, it sends an acknowledge signal in the 9th cycle. DAC8571 detects this acknowledge signal and prepares to send more data. Upon the receipt of eight clock cycles from the master, DAC8571 transmits the least significant byte L<7:0>. If the master detects all bits of the L<7:0> as valid data, it sends an acknowledge signal to DAC8571 during the 9th clock cycle. DAC8571 detects this acknowledge signal and prepares to send more data. Upon the receipt of 8 more clock cycles from the master, DAC8571 transmits the control byte C<7:0>. During the 9th clock cycle, the master transmits a not-acknowledge signal to DAC8571 and terminates the sequence with a stop condition, by pulling the SDA line from low to high while clock is high. M<7:0> and L<7:0> data could be either DAC data or could be the data stored in the temporary register. Bits in the C<7:0> reveal this information. Table 2 demonstrates the sequence of events that should occur while a master receiver is reading from DAC8571. Table 2. Master Receiver Reads From Slave Transmitter (DAC8571) Standard/Fast Mode Read Sequence-Data Transmit Transmitter Master Master DAC8571 DAC8571 Master DAC8571 Master DAC8571 Master Master C7 C6 C5 D7 D6 D5 D15 D14 D13 1 0 0 1 D12 D4 C4 MSB 6 5 4 Start 1 D11 D3 C3 A0 D10 D2 C2 0 D9 D1 C1 R/W D8 D0 C0 DAC8571 Acknowledges High byte Low byte Control byte Master signal end of read Done Master Acknowledges Master Acknowledges Master Not Acknowledges Stop or Repeated Start 3 2 1 LSB Comment Begin sequence Read addressing (R/W = 1) Master Writing to a Slave Receiver (High-Speed Mode) All devices must start operation in standard/fast mode and switch to high-speed mode using a well defined protocol. This is required because high-speed mode requires the on chip filter settings of each I2C device (for SDA and SCL lines) to be switched to support 3.4 Mbps operation. A stop condition always ends the high speed mode and puts all devices back to standard/fast mode. 17 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master. After the start condition, the master device puts out the high-speed master code 0000 1xxx. No device is allowed to acknowledge the master code, but the devices are required to switch their internal settings to support 3.4 Mbps operation upon the receipt of this code. After the not-acknowledge signal, the master is allowed to operate at high speed. Now at much higher speed, the master generates a repeated start condition. After the start condition, master generates the serial clock pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid data. For each valid I2C bit, SDA line should remain stable during the entire high period of the SCL line. The address byte consists of seven address bits and a direction bit (R/W=0). After sending the address byte, the master generates a 9th SCL pulse and monitors the state of the SDA line during the high period of this 9th clock cycle (master leaves the SDA line high). The SDA line being pulled low by the receiver during the high period of 9th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent. Upon the receipt of this acknowledge, the master knows that the high-speed communication link with a DAC8571 has been established and more data could be sent. The master continues by sending a control byte, C<7:0>, which sets DAC8571 operation mode. After sending the control byte, master expects an acknowledge. Upon the receipt of an acknowledge, the master sends a most significant byte, M<7:0> that represents the eight most significant bits of DAC8571's 16-bit digital-to-analog conversion data. Upon the receipt of the M<7:0>, DAC8571 sends an acknowledge. After receiving the acknowledge, the master sends a least significant byte, L<7:0>, that represents the eight least significant bits of DAC8571's 16-bit conversion data. After receiving the L<7:0>, the DAC8571 sends an acknowledge. At the falling edge of the acknowledge signal following the L<0>, DAC8571 performs a digital to analog conversion, depending on the operational mode. For further DAC updates, the master can keep repeating M<7:0> and L<7:0> sequences, expecting an acknowledge after each byte. After the required number of digital to analog conversions is complete, the master can break the communication link with DAC8571 by pulling the SDA line from low to high while SCL line is high. This is called a stop condition. A stop condition brings the bus back to idle (SDA and SCL both high). A stop condition indicates that communication with a device (DAC8571) has ended. All devices on the bus including DAC8571 then await a new start condition followed by a matching address byte. DAC8571 stays at its current state upon the receipt of a stop condition. A stop condition during the high-speed mode also indicates the end of the high-speed mode. Table 3 demonstrates the sequence of events that should occur while a master transmitter is writing to DAC8571 in I2C high-speed mode. Table 3. Master Transmitter Writes to Slave Receiver in High-Speed Mode HS Mode Write Sequence-Data Input Transmitter Master Master NONE Master Master DAC8571 Master DAC8571 Master DAC8571 Master DAC8571 Master (1) (2) 18 D7 D6 D5 D15 D14 D13 0 0 Load 1 1 0 0 0 0 0 0 MSB 6 5 4 Start 1 X X X 3 2 1 LSB Comment Begin sequence (1) HS mode master code No device may acknowledge HS master code A0 Brcsel D10 D2 0 0 D9 D1 R/W PD0 D8 D0 Write addressing (LSB = 0) Control byte (PD0=0) Writing dataword, high byte Writing dataword, low byte Done Not Acknowledge Repeated Start 1 Load 0 D12 D4 1 0 D11 D3 DAC8571 Acknowledges DAC8571 Acknowledges DAC8571 Acknowledges DAC8571 Acknowledges Stop or Repeated Start (2) High-byte, low-byte sequences can repeat Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) Master Receiver Reading From a Slave Transmitter (High-Speed Mode) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master. After the start condition, the master device puts out the high-speed master code 0000 1xxx. No device is allowed to acknowledge the master code, but the devices are required to switch their internal settings to support 3.4 Mbps operation upon the receipt of this code. After the not-acknowledge signal, the master is allowed to operate at high speed. Now at much higher speed, the master generates a repeated start condition. After the start condition, the master generates the serial clock pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid data. For each valid I2C bit, SDA line should remain stable during the entire high period of the SCL line. The address byte consists of seven address bits and a direction bit (R/W=1). After sending the address byte, the master generates a 9th SCL pulse and monitors the state of the SDA line during the high period of this 9th clock cycle (master leaves the SDA line high). The SDA line being pulled low by the receiver during the high period of 9th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent. Since the R/W bit in the address byte was set, master also knows that DAC8571 is ready to transmit data. Upon the receipt of this acknowledge, the master knows that the communication link with a DAC8571 has been established and more data could be received. The master continues by sending eight clock cycles during which DAC8571 transmits an M<7:0>. If the master detects all bits of the M<7:0> as valid data, it sends an acknowledge signal in the 9th cycle. DAC8571 detects this acknowledge signal and prepares to send more data. Upon the receipt of eight more clock cycles from the master, DAC8571 transmits L<7:0>. If the master detects all bits of the L<7:0> as valid data, it sends an acknowledge signal to DAC8571 during the 9th clock cycle. DAC8571 detects this acknowledge signal and prepares to send more data. Upon the receipt of eight more clock cycles from the master, DAC8571 transmits the control byte, C<7:0>. In the 9th clock cycle the master transmits a not-acknowledge signal to DAC8571 and terminates the sequence with a stop condition, by pulling the SDA line from low to high while clock is high. M<7:0> and L<7:0> data could be either DAC data or could be the data stored in the temporary register. Bits in the C<7:0> reveal this information. A stop condition during the high-speed mode also indicates the end of the high-speed mode. Table 4 demonstrates the sequence of events that should occur while a master receiver is reading from DAC8571 in I2C high-speed mode. Table 4. Master Receiver Reads Data From Slave Transmitter in High-Speed Mode HS Mode Read Sequence-Data Transmit Transmitter Master Master NONE Master Master DAC8571 DAC8571 Master DAC8571 Master DAC8571 Master Master C7 C6 C5 D7 D6 D5 D15 D14 D13 1 0 0 0 0 0 0 MSB 6 5 4 Start 1 X X X 3 2 1 LSB Comment Begin sequence HS Mode master code No device may acknowledge HS master code A0 D10 D2 C2 0 D9 D1 C1 R/W D8 D0 C0 Read addressing (R/W=1) High byte Low byte Control byte Master signal end of read Done Not Acknowledge Repeated Start 1 D12 D4 C4 1 D11 D3 C3 DAC8571 Acknowledges Master Acknowledges Master Acknowledges Master Not Acknowledges Stop or Repeated Start (1) (1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. 19 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) DAC8571 Update Sequence DAC8571 requires a start condition, a valid I2C address, a control byte, an MS byte and an LS byte for an update. The control byte sets the operational mode of the DAC8571. After the receipt of the control byte, DAC8571 expects an MS byte and an LS byte. After the receipt of each byte, DAC8571 acknowledges by pulling the SDA line low. At the falling edge of the acknowledge signal that follows the LS byte, DAC8571 performs an update. After the first update, further data can be sent as MS byte and LS byte sequences and DAC8571 keeps updating at the falling edge of the acknowledge signal that follows each LS byte. The bits of the last control byte determine the type of update being performed. Thus, for the first update, DAC8571 requires a start condition, a valid I2C address, a control byte, an MS byte and an LS byte. For all consecutive updates, DAC8571 needs an MS byte and an LS byte. Using the I2C high-speed mode, the clock running a 3.4 MHz, each 16-bit DAC update can be done within 18-clock cycles (MS byte, acknowledge bit, LS byte, acknowledge bit), at 188.88 KSPS. Using the fast mode, clock running at 400 kHz, maximum DAC update rate is limited to 22.22 KSPS. DAC8571 Address Byte MSB 1 0 0 1 1 A0 0 LSB R/W The address byte is the first byte received following a START condition from the master device. The first five bits (MSBs) of the slave address are factory preset to 10011. The next bit of the address byte is the device select bit A0, followed by a fixed 0 and the read/write direction bit R/W. In order for DAC8571 to respond, the 7-bit address should be 10011A00, where the state of the A0 bit matches the state of the A0 pin. A maximum of two DAC8571 devices with the same preset code can therefore be connected on the same bus at one time. The A0 Address inputs can be permanently connected to VDD or digital ground, or can be actively driven by TTL or CMOS logic levels. The device address is set by the state of these pins upon power up of the DAC8571. The last bit of the address byte (R/W) defines the direction of the data flow. When set to a 1, a read operation is selected (master device reads from DAC8571); when set to a 0, a write operation is selected (master device writes to DAC8571). Following the START condition, the DAC8571 monitors the SDA bus, checking the device address being transmitted. Upon receiving the 10011A00 code, and the R/W bit, the DAC8571 outputs an acknowledge signal on the SDA line. Broadcast addressing is also supported by DAC8571. Broadcast addressing can be used for synchronously updating or powering down multiple DAC8571 devices on the same bus. DAC8571 is designed to work with other members of DAC857x, DAC757x families to support multichannel synchronous update. When broadcast addressing is used, DAC8571 responds regardless of the state of the A0 pin. Broadcast address is only valid for write operation and cannot be used for read operation. Broadcast address is as follows. MSB 1 0 0 1 0 0 0 LSB 0 Control Byte After transmitting an acknowledge pulse following a valid address, DAC8571 expects a control byte C<7:0>. Control byte functionality is shown in Table 5. The first two MSBs C<7> and C<6> of the control byte must be zeroes for DAC8571 to update. If these two bits are not assigned to zero, DAC8571 ignores all update commands, but still generates an acknowledge signal. C<5> and C<4> are used for setting the update mode. Some of these modes are designed to support multichannel synchronous operation between multiple devices. 20 www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) * * C<5>=0, C<4>=0: Store I2C data. The contents of MS byte and LS byte data (or power-down information) are stored into the temporary register. This mode does not change the DAC output. C<5>=0, C<4>=1: Update DAC with I2C data. Most common mode. The contents of MS byte and LS byte data (or power-down information) are stored into the temporary data register and into the DAC register. This mode changes the DAC output with the contents of I2C MS byte and LS byte data. C<5>=1, C<4>=0: Update with previously stored data. The contents of MS byte and LS byte data (or power-down information) are ignored. The DAC is updated with the contents of the data previously stored in the temporary register. This mode changes the DAC output. C<5>=1, C<4>=1: Broadcast update, If C<2>=0, DAC is updated with the contents of its temporary register. If C<2>=1, DAC is updated with I2C MS byte and LS byte data. C<7> and C<6> do not have to be zeroes in order for DAC8571 to update. This mode is intended to help DAC8571 work with other DAC857x and DAC757x devices for multichannel synchronous update applications. * * C<3> should always be zero. C<2> is utilized only when C<5>=C<4>=1. Otherwise, C<2> must be assigned to zero. C<1> should always be zero. C<0> should be zero during normal DAC operation. C<0>=1 is a power-down flag. If C<0>=1, M<7>, M<6>, and M<5> indicate a powerdown operation as shown in Table 6. Table 5. Control Byte Functionality C<7> 0 0 0 0 0 C<6> 0 0 0 0 0 C<5> 0 0 0 0 1 C<4> 0 0 1 1 0 C<3> 0 0 0 0 0 C<2> Brcsel 0 0 0 0 0 0 0 0 0 0 C<1> C<0> PD0 0 1 0 1 0 M<7> MSB M<6> MSB-1 Data See Table 6 Data See Table 6 x M<5> MSB-2...LSB DAC8571 FUNCTION Write temporary register with data Write temporary register with power down command Write temporary register and load DAC with data Power down DAC Update DAC with temporary register data or power down Load all DACs, all devices with temporary register data Load all DACs, all devices with data Power down all DACs, all devices Load1 Load0 Broadcast Commands x x x x x x 1 1 1 1 1 1 x x x 0 1 1 x x x x 0 1 x Data See Table 6 Most Significant Byte Most Significant Byte M<7:0> consists of 8 most significant bits of D/A conversion data. When C<0>=1. M<7>, M<6>, M<5> indicate a powerdown operation as shown in Table 6. Least Significant Byte Least Significant Byte L<7:0> consists of the 8 least significant bits of D/A conversion data. DAC8571 updates at the falling edge of the acknowledge signal that follows the L<0> bit. Data Transmit and Read-Back I2C bus can be noisy and data integrity and can be a problem in a system of many I2C devices. To enable I2C system verification, DAC8571 provides read back capability for the user. During read back operation, the contents of the control byte, MS byte and the LS byte can be sent back to the master device using the I2C bus. This read-back function is also useful if a device on the I2C bus inquires DAC8571 data. 21 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) For read-back operation, the master device sends the I2C address and sets the R/W bit. DAC8571 acknowledges. Then, upon the receipt of clock pulses from the master, DAC8571 sends the MS byte. If the master acknowledges, DAC8571 sends the LS byte. If the master acknowledges, DAC8571 sends the control byte. This sequence is interrupted by the master sending a not acknowledge signal. Depending on the contents of the control byte transmitted by the DAC8571, the MS byte and LS byte information (transmitted by the DAC8571) is interpreted as follows: C<5> 0 0 1 1 1 C<4> 0 1 0 1 1 C<2> 0 0 0 0 1 MS and LS bytes represent temporary register data MS and LS bytes represent temporary and DAC register data MS and LS bytes represent I2C data that is discarded MS and LS bytes represent I2C data that is discarded MS and LS bytes represent temporary and DAC register data EXAMPLES (A0 TIED TO GND, VDD = 5 V) EXAMPLE 1: Write 1/4 scale to DAC8571 ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 2: Switch DAC8571 to fast settling mode ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 3: Switch DAC8571 back to low power mode ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 4: Power-down DAC8571 with Hi-Z output ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 5: Power-down DAC8571 with 1K output impedance to ground ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 6: Power-down DAC8571 with 100K output impedance to ground ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 7: Store full scale data in temporary register ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 8: Update DAC8571 with the data previously stored in the temporary register ADDRESS <7...0> START 1001 1000 ACK Previous output voltage is valid EXAMPLE 9: Broadcast a powerdown command to all DAC8571s on the I2C bus ADDRESS <7...0> 22 C<7...0> M<7...0> L<7...0> C<7...0> 0010 0000 ACK M<7...0> XXXX XXXX ACK L<7...0> XXXX XXXX ACK STOP New Vout valid C<7...0> 0000 0000 ACK M<7...0> 1111 1111 ACK L<7...0> 1111 1111 ACK STOP C<7...0> 0001 0001 ACK M<7...0> 1000 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = 0 V C<7...0> 0001 0001 ACK M<7...0> 0100 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = 0 V C<7...0> 0001 0001 ACK M<7...0> 1100 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = Hi-Z C<7...0> 0001 0001 ACK M<7...0> 0000 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = 0 V C<7...0> 0001 0001 ACK M<7...0> 0010 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = 0 V C<7...0> 0001 0000 ACK M<7...0> 0100 0000 ACK L<7...0> 0000 0000 ACK STOP Vout = 1.25 V www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) EXAMPLE 9: Broadcast a powerdown command to all DAC8571s on the I2C bus START 1001 0000 ACK 0011 0101 ACK 1100 0000 ACK 0000 0000 ACK Vout = Hi-Z STOP Previous output voltage is valid EXAMPLE 10: Broadcast update. All DAC8571s on the I2C bus update synchronously with the contents of their temporary registers ADDRESS <7...0> START 1001 0000 ACK Previous output voltage is valid EXAMPLE 11: Read back DAC8571 internal data. V denotes valid logic. ADDRESS<7...0> START 1001 1001 HS Master Code START MSB<7...0> 0000 0000 MSB<7...0> 0000 0000 Vout = 76 V MSB<7...0> 0000 0000 Vout = 3 x76 V MSB<7...0> 0000 0000 Vout = 5 x76 V ACK LSB<7...0> 0000 0110 ACK ACK LSB<7...0> 0000 0100 ACK ACK ACK Previous Vout voltage valid LSB<7...0> 0000 0010 ACK 0000 1000 NOT ACK LSB<7...0> 0000 0000 ACK Vout = 0 V MSB<7...0> 0000 0000 Vout = 2 x76 V MSB<7...0> 0000 0000 Vout = 4 x76 V MSB<7...0> 0000 0000 Vout = 6 x76 V ACK LSB<7...0> 0000 0111 ACK Vout = 7 x76 V ACK LSB<7...0> 0000 0101 ACK Vout = 5 x76 V ACK LSB<7...0> 0000 0011 ACK Vout = 3 x76 V REPEATED START Previous Vout voltage valid MSB<7...0> 0000 0000 ACK LSB<7...0> 0000 0001 ACK Vout = 76 V ACK M<7...0> VVVV VVVV MASTER ACK L<7...0> VVVV VVVV ADDRESS 1001 1000 ACK MASTER ACK C<7...0> MASTER VVVV VVVV NOT ACK STOP C<7...0> 0001 0000 ACK C<7...0> 0011 0000 ACK M<7...0> XXXX XXXX ACK L<7...0> XXXX XXXX ACK STOP New Vout valid EXAMPLE 12: Ramp generation in high speed mode (up to code 7 is shown) Power-On Reset The DAC8571 contains a power-on-reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. No input is brought high before the power is applied. Power-Down Modes The DAC8571 contains five separate power settings. These modes are programmable when C<0>=1. When C<0>=1, M<7>, M<6>, and M<5> bits represent power setting control bits, and M<4...0> and L<7...0> are assigned to zeroes. Power setting of DAC8571 is updated at the falling edge of the acknowledge signal that follows the least significant byte. To set the power consumption of the device, following I2C sequence is used. Start_condition -> Valid_address C<7:0> M<7:0> L<7:0> Stop_condition (1001 1000) -> ack (0001 0001) -> ack ( vvv0 0000) -> ack (0000 0000) -> ack 23 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) Table 6. Power Settings for the DAC8571 (C<0>=1) M<7> 0 0 0 1 1 M<6> 0 0 1 0 1 M<5> 0 1 X X X Operating Mode Low power mode, default Fast settling mode PWD. 1k to GND PWD. 100 k to GND PWD. Output Hi-Z After power-up, the device works in low power mode with its normal power consumption of 170 A at 5 V. At fast settling mode, device consumes 250 A nominally, but settles in 10 s. For the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to GND through a 1-k resistor, a 100-k resistor or it is left open-circuit (high impedance). The output stage is illustrated in Figure 32. A power on reset starts the DAC8571 in the low power mode. Low power mode and fast-settling mode settings stay unchanged during DAC8571 data updates, unless they are specifically overwritten as explained in Table 6. On the other hand, each new data sequence requiring a DAC update brings the DAC8571 out of the three power-down conditions. DAC8571 power settings can be stored in the temporary register, just like data (use C<7:0> = 0000 0001). This allows simultaneous powerdown capability for multichannel applications. Amplifier _ Resistor String DAC + VSense VOUT Powerdown Circuitry Resistor Network Figure 32. Output Stage During Power-Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s for VDD = 3 V. (See the Typical Characteristics section for additional information.) CURRENT CONSUMPTION In the low power mode, the DAC8571 typically consumes 170 A at VDD = 5 V and 150 A at VDD = 3 V including reference current consumption. Fast settling mode adds 80 A of current consumption, but ensures 10-s settling. Additional current consumption can occur at the digital inputs if VIH< www.ti.com DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 THEORY OF OPERATION (continued) DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC8571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset and gain error margins, the DAC8571 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2 k can be driven by the DAC8571 while achieving a very good load regulation. Load regulation error increases when the DAC output voltage is close to supply rails. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic. The reference voltage applied to the DAC8571 may be reduced below the supply voltage applied to VDD in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading conditions). AC PERFORMANCE DAC8571 can achieve typical ac performance of 96-dB signal-to-noise ratio (SNR) and 65-dB total harmonic distortion (THD), making the DAC8571 a solid choice for applications requiring low SNR at output frequencies at or below 4 kHz. OUTPUT VOLTAGE STABILITY The DAC8571 exhibits excellent temperature stability of 5 ppm/C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a 25 V window for a 1C ambient temperature change. Good power supply rejection ratio (PSRR) performance reduces supply noise present on VDD from appearing at the outputs to well below 10 V. Combined with good dc noise performance and true 16-bit differential linearity, the DAC8571 becomes a perfect choice for closed-loop control applications. SETTLING TIME AND OUTPUT GLITCH PERFORMANCE Settling time to within the 16-bit accurate range of the DAC8571 is achievable within 10 s for a full-scale code change at the input. Worst case settling times between consecutive code changes is typically less than 2 s, therefore, the update rate is limited by the I2C interface for digital input signals changing code-to-code. For full-scale output swings, the output stage of each DAC8571 channel typically exhibits less than 100-mV overshoot and undershoot when driving a 200-pF capacitive load. Code-to-code change glitches are extremely low (~10V) given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal segmentation of the DAC8571, code-to-code glitches occur at each crossing of an Nx4096 code boundary. These glitches can approach 100 mVs for N = 15, but settle out within ~2 s. USING REF02 AS A POWER SUPPLY FOR DAC8571 Due to the extremely low supply current required by the DAC8571, a possible configuration is to use a REF02 5-V precision voltage reference to supply the required voltage to the DAC8571's supply input as well as the reference input, as shown in Figure 33. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC8571. If the REF02 is used, the current it needs to supply to the DAC8571 is 160-A typical and 225-A max for VDD = 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5-k load on a given DAC output) is: 25 DAC8571 SLAS373A - DECEMBER 2002 - REVISED JULY 2003 www.ti.com THEORY OF OPERATION (continued) 15 V REF02 5V 2-Wire l2C Interface A0 SCL SDA VDD, Vref DAC8571 VOUT = 0 V to 5 V Figure 33. REF02 as a Power Supply 160 mA ) 5 V + 1.16 mA 5 kW (2) The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 290 V for a 1.16-mA current drawn. This corresponds to a 3.82 LSB error for a 0-V to 5-V output range. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The power applied to VDD and VREF should be well regulated and low noise. Switching power supplies and dc/dc converters often has high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise easily couples into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD is connected to a +5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1-F to 10-F, and 0.1-F bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100-F electrolytic capacitor or even a Pi filter made up of inductors and capacitors--all designed to essentially lowpass filter the 5-V supply, removing the high frequency noise. 26 MECHANICAL DATA MPDS028B - JUNE 1997 - REVISED SEPTEMBER 2001 DGK (R-PDSO-G8) 0,38 0,25 8 5 PLASTIC SMALL-OUTLINE PACKAGE 0,65 0,08 M 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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