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DAC8534
DAC 8534
(R)
SBAS254A - SEPTEMBER 2002 - REVISED JULY 2003
Quad Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER
FEATURES
q q q q q q q q q q q q POWER SUPPLY: +2.7V to +5.5V microPOWER OPERATION: 950A at 5V 16-BIT MONOTONIC OVER TEMPERATURE SETTLING TIME: 10s to 0.003% FSR ULTRA-LOW AC CROSSTALK: -100dB typ POWER-ON RESET TO ZERO-SCALE ON-CHIP OUTPUT BUFFER AMPLIFIER WITH RAIL-TO-RAIL OPERATION DOUBLE BUFFERED INPUT ARCHITECTURE SIMULTANEOUS OR SEQUENTIAL OUTPUT UPDATE AND POWER-DOWN 16 CHANNEL BROADCAST CAPABILITY SCHMITT-TRIGGERED INPUTS TSSOP-16 PACKAGE
DESCRIPTION
The DAC8534 is a quad channel, 16-bit Digital-to-Analog Converter (DAC) offering low-power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30MHz for IOVDD = 5V. The DAC8534 requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8534 provides a per channel power-down feature, accessed over the serial interface, that reduces the current consumption to 200nA per channel at 5V. The low-power consumption of this device in normal operation makes it ideally suited to portable battery-operated equipment and other low-power applications. The power consumption is 5mW at 5V, reducing to 4W in power-down mode. The DAC8534 is available in a TSSOP-16 package with a specified operating temperature range of -40C to +105C.
AVDD IOVDD VREFH
APPLICATIONS
q q q q q q PORTABLE INSTRUMENTATION CLOSED-LOOP SERVO-CONTROL PROCESS CONTROL DATA ACQUISITION SYSTEMS PROGRAMMABLE ATTENUATION PC PERIPHERALS
Data Buffer A
DAC Register A
DAC A
VOUTA VOUTB VOUTC
Data Buffer D 18
DAC Register D
DAC D
VOUTD
SYNC SCLK DIN
24-Bit Serial-toParallel Shift Register
Buffer Control 8
Register Control
Power-Down Control Logic Resistor Network
GND
A0
A1
LDAC ENABLE VREFL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002-2003, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
AVDD to GND ........................................................................ -0.3V to +6V Digital Input Voltage to GND ............................... -0.3V to +AVDD + 0.3V VOUTA to VOUTD to GND .................................... -0.3V to + AVDD + 0.3V Operating Temperature Range ...................................... -40C to +105C Storage Temperature Range ......................................... -65C to +150C Junction Temperature Range (TJ max) ........................................ +150C Power Dissipation .......................................................... (TJ max - TA)/JA JA Thermal Impedance ......................................................... 118C/W JC Thermal Impedance ........................................................... 29C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215C Infrared (15s) ........................................................................ +220C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) PW SPECIFICATION TEMPERATURE RANGE -40C to +105C PACKAGE MARKING D8534I ORDERING NUMBER DAC8534IPW DAC8534IPWR TRANSPORT MEDIA, QUANTITY Tube, 90 Tape and Reel, 2000
PRODUCT DAC8534
PACKAGE-LEAD TSSOP-16
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
AVDD = +2.7V to +5.5V, -40C to +105C, unless otherwise specified. DAC8534 PARAMETER STATIC Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Zero-Scale Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient Channel-to-Channel Matching PSRR OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time PERFORMANCE (1) CONDITIONS MIN TYP MAX UNITS
16 16-Bit Monotonic 0.25 +5 7 -0.15 3 8 0.75 0 To 0.003% FSR 0200H to FD00H RL = 2k; 0pF < CL < 200pF RL = 2k; CL = 500pF RL = RL = 2k 1LSB Change Around Major Carry 8 0.0987 1 +20 -1.0 1.0
RL = 2k, CL = 200pF
Bits % of FSR LSB mV V/C % of FSR % of FSR ppm of FSR/C mV mV/V V s
VREFH 10
Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Crosstalk AC Crosstalk DC Output Impedance Short-Circuit Current Power-Up Time
1kHz sine Wave AVDD = +5V AVDD = +3V Coming Out of Power-Down Mode AVDD = +5V Coming Out of Power-Down Mode AVDD = +3V BW = 20kHz, AVDD = 5V FOUT = 1kHz
12 1 470 1000 20 0.5 0.25 -100 1 50 20 2.5 5 94 67 69 65
-96
s V/s pF pF nV-s nV-s LSB dB mA mA s s dB dB dB dB
AC PERFORMANCE SNR (1st 19 Harmonics Removed) THD SFDR SINAD
NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.
2
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DAC8534
SBAS254A
ELECTRICAL CHARACTERISTICS (Cont.)
AVDD = +2.7V to +5.5V, -40C to +105C, unless otherwise specified. DAC8534 PARAMETER REFERENCE INPUT Reference Current Reference Input Range Reference Input Impedance LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance POWER REQUIREMENTS AVDD IOVDD AIDD (normal mode) IOIDD AIDD = +3.6V to +5.5V AIDD = +2.7V to +3.6V AIDD (all power-down modes) AIDD = +3.6V to +5.5V AIDD = +2.7V to +3.6V POWER EFFICIENCY IOUT/IDD TEMPERATURE RANGE Specified Performance CONDITIONS VREF = AVDD = +5V VREF = AVDD = +3V 0 37 1 0.8 0.6 2.4 2.1 3 2.7 2.7 DAC Active and Excluding Load Current 10 VIH = IOVDD and VIL = GND VIH = IOVDD and VIL = GND VIH = IOVDD and VIL = GND VIH = IOVDD and VIL = GND ILOAD = 2mA, AVDD = +5V -40 0.95 0.9 0.8 0.05 89 +105 20 1.6 1.5 1 1 A mA mA A A % C 5.5 5.5 MIN TYP 135 80 MAX 180 120 AVDD UNITS A A V k A V V V V pF V V
IOVDD IOVDD IOVDD IOVDD
= = = =
+5V +3V +5V +3V
NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.
PIN CONFIGURATION
Top View TSSOP
PIN DESCRIPTIONS
PIN 1 2 NAME VOUTA VOUTB VREFH AVDD VREFL GND VOUTC VOUTD SYNC DESCRIPTION Analog output voltage from DAC A. Analog output voltage from DAC B. Positive reference voltage input. Power supply input, +2.7V to +5.5V. Negative reference voltage input. Ground reference point for all circuitry on the part. Analog output voltage from DAC C. Analog output voltage from DAC D. Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8534). Serial Clock Input. Data can be transferred at rates up to 30MHz. Serial Data Input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Digital Input-Output Power Supply Address 0 -- sets device address, see Table II. Address 1 -- sets device address, see Table II. Active LOW, ENABLE LOW connects the SPI interface to the serial port. Load DACs, rising edge triggered loads all DAC registers.
VOUTA VOUTB VREFH AVDD VREFL GND VOUTC VOUTD
1 2 3 4 DAC8534 5 6 7 8
16 LDAC 15 ENABLE 14 A1 13 A0 12 IOVDD 11 DIN 10 SCLK 9 SYNC
2 4 5 6 7 8 9
10 11
SCLK DIN
12 13 14 15 16
IOVDD A0 A1 ENABLE LDAC
DAC8534
SBAS254A
3
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TIMING CHARACTERISTICS(1, 2)
AVDD = +2.7V to +5.5V; all specifications -40C to +105C unless otherwise noted. DAC8534 PARAMETER t1
(3)
DESCRIPTION SCLK Cycle Time
CONDITIONS IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V
MIN 50 33 26 15 22.5 13 0 0
TYP
MAX
UNITS ns ns ns ns ns ns ns ns
t2
SCLK HIGH Time
t3
SCLK LOW Time
t4
SYNC Falling Edge to SCLK Falling Edge Setup Time
t5
Data Setup Time
IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V
5 5 4.5 4.5 0 0
ns ns ns ns ns ns
t6
Data Hold Time
t7
24th SCLK Falling Edge to SYNC Rising Edge
t8
Minimum SYNC HIGH Time
IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V IOVDD = AVDD = 2.7V to 5.5V
50 33
ns ns
t9
24th SCLK Falling Edge to SYNC Falling Edge
130
ns
NOTES: (1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at IOVDD = AVDD = +3.6V to +5.5V and 20MHz at IOVDD = AVDD = +2.7V to +3.6V.
SERIAL WRITE OPERATION
t1 SCLK t8 t4 SYNC t6 t5 DIN DB23 DB0 1 t3 t2 t7 24
t9
DB23
4
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DAC8534
SBAS254A
TYPICAL CHARACTERISTICS
At TA = +25C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 32 16 0 -16 -32 -48 -64 1.0 CHANNEL A AVDD = 5V 64 48 32 16 0 -16 -32 -48 -64 1.0
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL B AVDD = 5V
LE (LSB)
DLE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DLE (LSB)
LE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 32 16 0 -16 -32 -48 -64 1.0 CHANNEL C AVDD = 5V
LE (LSB)
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 32 16 0 -16 -32 -48 -64 1.0
DLE (LSB)
CHANNEL D
AVDD = 5V
DLE (LSB)
LE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 32 16 0 -16 -32 -48 -64 1.0 CHANNEL A AVDD = 2.7V 64 48 32 16 0 -16 -32 -48 -64 1.0
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL B AVDD = 2.7V
LE (LSB)
DLE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DLE (LSB)
LE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DAC8534
SBAS254A
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 64 48 32 16 0 -16 -32 -48 -64 1.0 CHANNEL C AVDD = 2.7V
64 48 32 16 0 -16 -32 -48 -64 1.0
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL D AVDD = 2.7V
LE (LSB)
DLE (LSB)
DLE (LSB)
Digital Input Code
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
LE (LSB)
0.5 0.0 -0.5 -1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
ZERO-SCALE ERROR vs TEMPERATURE 10 CH D 8
Error (mV)
Error (mV)
ZERO-SCALE ERROR vs TEMPERATURE 10 AVDD = VREF = 2.7V 8 6
CH C
AVDD = VREF = 5V
6
CH A 4 2
CH C
CH B
CH D
4
2 CH B 0 -40 CH A
0 -2 -40
-10
20
50
80
110
-10
20
50
80
110
Temperature (C)
Temperature (C)
FULL-SCALE ERROR vs TEMPERATURE 20 CH C 15 CH D 10 Error (mV) 5 0 -5 CH A -10 -40 -10 20 50 80 110 -10 -40 To avoid clipping of the output signal during the test, VREF = AVDD - 10mV, AVDD = 5V, VREF = 4.99V Error (mV) 15 20
FULL-SCALE ERROR vs TEMPERATURE To avoid clipping of the output signal during the test, VREF = AVDD - 10mV, AVDD = 2.7V, VREF = 2.69V
CH C 10 5 0 CH A -5
CH D
CH B
CH B
-10
20
50
80
110
Temperature (C)
Temperature (C)
6
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DAC8534
SBAS254A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, unless otherwise noted.
SINK CURRENT CAPABILITY (ALL CHANNELS) 0.150 0.125 0.100 VREF = AVDD - 10mV DAC loaded with 0000H
SOURCE CURRENT CAPABILITY (ALL CHANNELS) 5.00 VREF = AVDD - 10mV DAC Loaded with FFFFH AVDD = 5V
4.95
VOUT (V)
0.075 AVDD = 5V 0.050
VOUT (V)
AVDD = 2.7V
4.90
4.85
0.025 0.000 0 1 2 ISINK (mA) 3 4 5
4.80 0 1 2 3 4 5 ISOURCE (mA)
SOURCE CURRENT CAPABILITY (ALL CHANNELS) 2.70 VREF = AVDD - 10mV DAC Loaded with FFFFH AVDD = 2.7V
1200
SUPPLY CURRENT vs DIGITAL INPUT CODE AVDD = VREF = 5V 1000 800
2.65
AIDD (A)
VOUT (V)
2.60
600 AVDD = VREF = 2.7V 400
2.55
200
2.50 0 1 2 3 4 5 ISOURCE (mA)
0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
SUPPLY CURRENT vs TEMPERATURE 1200 AVDD = VREF = 5V 1000 800
AIDD (A)
1000 950 900
SUPPLY CURRENT vs SUPPLY VOLTAGE
AIDD (A)
AVDD = VREF = 2.7V 600 400 200 0 -40 -10 20 50 80 110 Temperature (C) Reference Current Included All Channels Powered, No Load.
850 800 750 700 650 600 2.7 3.05 3.4 3.75 4.1 4.45 AVDD (V) 4.8 5.15 5.5
DAC8534
SBAS254A
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, unless otherwise noted.
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1750 1650 1550 TA = 25C, SYNC Input (All others inputs = GND) Reference Current Included
HISTOGRAM OF CURRENT CONSUMPTION 1500 AVDD = VREF = 5V Reference Current Included
AIDD + IOIDD (A)
1450 1350 1250 1150 1050 950 850 750 0 0.5 1.0 1.5 2.0 2.5
Frequency
AVDD = VREF = 5V
1000
500
AVDD = VREF = 2.7V
0
790 820 850 880 910 940 970 1120 1000 1030 1060
VLOGIC (V)
AIDD (A)
HISTOGRAM OF CURRENT CONSUMPTION 1500 AVDD = VREF = 2.7V Reference Current Included
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
EXITING POWER-DOWN MODE AVDD = VREF = 5V Power-Up Code = FFFFH
Frequency
500
VOUT (V)
1000
0
-0.5
730
760
790
820
850
880
910
940
970
1000
1030
AIDD (A)
1060
Time (3s/div)
OUTPUT GLITCH (Mid-Scale) 2.53 2.52 2.51
VOUT (V, 10mV/div)
OUTPUT GLITCH (Worst Case) 4.72 4.70 4.68
VOUT (V, 20mV/div)
2.50 2.49 2.48 2.47 2.46 2.45 2.44 2.43
AVDD = VREF = 5V Code 7FFFH to 8000H to 7FFFH (Glitch Occurs Every N * 4096 Code Boundary)
AVDD = VREF = 5V Code EFFFH to F000H to EFFFH (Glitch Occurs Every N * 4096 Code Boundary)
4.66 4.64 4.62 4.60 4.58 4.56 4.54
Time (1s/div)
Time (1s/div)
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1090
DAC8534
SBAS254A
1150
3.0
3.5
4.0
4.5
5.0
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, unless otherwise noted.
20 18 16
Output Error (mV)
ABSOLUTE ERROR AVDD = VREF = 5V TA = 25C Channel D Output Channel B Output
Output Error (mV)
10 8 6 4 2 0 -2 -4 -6 Channel B Output
ABSOLUTE ERROR AVDD = VREF = 2.7V TA = 25C
14 12 10 8 6 4 2
Channel D Output
Channel A Output
Channel A Output
Channel C Output 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
-8 Channel C Output -10 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
FULL-SCALE SETTLING TIME (Large Signal) 6 5 4
VOUT (V)
HALF-SCALE SETTLING TIME (Large Signal) 3.0 AVDD = VREF = 5V Output Loaded with 2k and 200pF to GND
AVDD = VREF = 5.5V Output Loaded with 2k and 200pF to GND
VOUT (V)
2.5 2.0 1.5 1.0 0.5 0
3 2 1 0 Time (12s/div)
Time (12s/div)
FULL-SCALE SETTLING TIME (Large Signal) 3.5 3.0 2.5 AVDD = VREF = 2.7V Output Loaded with 2k and 200pF to GND
HALF-SCALE SETTLING TIME 1.5
VOUT (V)
2.0 1.5 1.0 0.5 0 Time (12s/div)
VOUT (V)
1.0
0.5
AVDD = VREF = 2.7V Output Loaded with 2k and 200pF to GND
0 Time (12s/div)
DAC8534
SBAS254A
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, unless otherwise noted.
98 96
SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY
0 -10
TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY AVDD = VREF = 5V FS = 52ksps, -1dB FSR Digital Input Measurement Bandwidth = 20kHz
AVDD = 5V 94
SNR (dB)
-20 -30
92 AVDD = 2.7V 90 88 86 84 0 500 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k 4.5k Output Frequency (Hz) AVDD = VREF -1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz
THD (dB)
-40 -50 -60 -70 -80 -90 -100 0 500 1.0k 1.5k 2.0k 2.5k 3.0k Output Frequency (Hz) 3.5k 4.0k 2nd-Harmonic 3rd-Harmonic THD
0 -10 -20 -30
TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY AVDD = VREF = 2.7V FS = 52ksps, -1dB FSR Digital Input Measurement Bandwidth = 20kHz
FULL-SCALE SETTLING TIME (Small-Signal-Positive Going Step)
THD (dB)
-40 -50 -60 -70 -80 -90 -100 0 500 1.0k 1.5k 2.0k 2.5k 3.0k Output Frequency (Hz) 3.5k 4.0k THD
Output Voltage
Small-Signal Settling Time 5mV/div
Trigger Pulse
2nd-Harmonic 3rd-Harmonic
Time (2s/div)
FULL-SCALE SETTLING TIME (Small-Signal-Negative Going Step)
Output Voltage
Small-Signal Settling Time 5mV/div
Trigger Pulse
Time (2s/div)
10
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DAC8534
SBAS254A
THEORY OF OPERATION
DAC SECTION
The architecture of each channel of the DAC8534 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 1 shows a simplified block diagram of the DAC architecture.
VREFH
RDIVIDER VREF 2 R
VREFH 70k REF (+) Resistor String REF(-)
50k
50k
R
To Output Amplifier (2x Gain)
VOUT
DAC Register
VREFL
R
FIGURE 1. DAC8534 Architecture.
R
The input coding for each device is unipolar straight binary, so the ideal output voltage is given by:
VOUT X = VREFL + (VREF H - VREF L) *
DIN 65536
VREFL
FIGURE 2. Resistor String. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8534 compatible with highspeed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift regtister and the shift register gets locked. Further clocking does not change the shift register data. Once 24 bits are locked into the shift register, the 8MSBs are used as control bits and the 16LSBs are used as data. After receiving the 24th falling clock edge, DAC8534 decodes the 8 control bits and 16 data bits to perform the required function, without waiting for a SYNC rising edge. A new SPI sequence starts at the next falling edge of SYNC. A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface, no data transfer occurs. At this point, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the digital input levels are as close to each rail as possible. (Please refer to the "Typical Characteristics" section for the "Supply Current vs Logic Input Voltage" transfer characteristic curve.)
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. VOUTX refers to channel A or through D.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply a divide-by-2 resistor followed by a string of resistors. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then applied to the output amplifier by closing one of the switches connecting the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating rail-torail voltages on its output which approaches an output range of 0V to AVDD (gain and offset errors must be taken into account). Each buffer is capable of driving a load of 2k in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics.
SERIAL INTERFACE
The DAC8534 uses a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPITM, QSPITM, and MicrowireTM interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence.
SPI and QSP are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor.
IOVDD AND VOLTAGE TRANSLATORS
The IOVDD pin powers the digital input structures of the DAC8534. For single-supply operation, it could be tied to AVDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families and it should be connected to the logic supply of the system. Analog circuits and internal logic of the DAC8534 use AVDD as the supply voltage. The external logic high inputs get translated to AVDD by level shifters. These level shifters use the IOVDD voltage as a
DAC8534
SBAS254A
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reference to shift the incoming logic HIGH levels to AVDD. IOVDD is ensured to operate from 2.7V to 5.5V regardless of the AVDD voltage, which ensures compatibility with various logic families. Although specified down to 2.7V, IOVDD will operate at as low as 1.8V with degraded timing and temperature performance. For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages.
DAC8534s get updated with previously stored data (or powerdown). If DB18 = 1, then SR data (or power-down) updates all channels of all DAC8534s in the system. This broadcast update feature allows the simultaneous update of up to 16 channels. Power-down/data selection is as follows: DB16 is a power-down flag. If this flag is set, then DB15 and DB14 select one of the four power-down modes of the device as described in Table I. If DB16 = 1, DB15 and DB14 no longer represent the two MSBs of data, they represent a power-down condition described in Table I. Similar to data, power-down conditions can be stored at the temporary registers of each DAC. It is possible to update DACs simultaneously either with data, power-down, or a combination of both. Please refer to Table II for more information.
PD0 (DB16) PD1 (DB15) PD2 (DB14) 1 1 1 1 0 0 1 1 0 1 0 1 OPERATING MODE Output High Impedance Output Typically 1k to GND Output Typically 100k to GND Output High Impedance
INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8534 is 24 bits wide, as shown in Figure 3, and is made up of 8 control bits (DB16-DB23) and 16 data bits (DB0-DB15). The first two control bits (DB22 and DB23) are the address match bits. The DAC8534 offers additional hardware-enabled addressing capability allowing a single host to talk to up to four DAC8534s through a single SPI bus without any glue logic, enabling up to 16-channel operation. The state of DB23 should match the state of pin A1, similarly, the state of DB22 should match the state of pin A0. If there is no match, the control command and the data (DB21...DB0) are ignored by the DAC8534. That is, if there is no match, the DAC8534 is not addressed. Address matching can be overridden by the broadcast update, as will be explained. LD 1 (DB20) and LD 0 (DB21) control the updating of each analog output with the specified 16-bit data value or powerdown command. Bit DB19 is a "Don't Care" bit which does not affect the operation of the DAC8534 and can be 1 or 0. The DAC Channel Select Bits (DB17, DB18), control the destination of the data (or power-down command) from DAC A through DAC D. The final control bit, PD0 (DB16) selects the power-down mode of the DAC8534 channels. The DAC8534 also supports a number of different load commands. The load commands include broadcast commands to address all the DAC8534s on an SPI bus. The load commands can be summarized as follows: DB21 = 0 and DB20 = 0: Single-channel store. The temporary register (data buffer) corresponding to a DAC selected by DB18 and DB17 is updated with the contents of SR data (or power-down). DB21 = 0 and DB20 = 1: Single-channel update. The temporary register and DAC register corresponding to a DAC selected by DB18 and DB17 are updated with the contents of SR data (or power-down). DB21 = 1 and DB20 = 0: Simultaneous update. A channel selected by DB18 and DB17 gets updated with the SR data, and simultaneously, all the other channels get updated with previous stored data (or power-down). DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8534s on the SPI bus respond, regardless of address matching. If DB18 = 0, then SR data gets ignored, all channels from all
DB23 A1 DB11 D11 D10 D9 D8 D7 D6 A0 LD1 LD0 X
TABLE I. DAC8534 Power-Down Modes.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 4).
POWER-ON RESET
The DAC8534 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device.
POWER-DOWN MODES
The DAC8534 utilizes four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register and performing a "Load" action to the DACs. The DAC8534 offers a very flexible power-down interface based on channel register operation. A channel consists of a
DB12
DAC Select 1 DAC Select 0
PD0
D15
D14
D13
D12 DB0
D5
D4
D3
D2
D1
D0
FIGURE 3. DAC8534 Data Input Register Format.
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D23 A1
D22 A0
D21 Load 1
D20 Load 0
D19
D18
D17
D16 PD0
D15 MSB
D14 MSB-1
D13-D0 MSB-2...LSB DESCRIPTION
Don't Care DAC Sel 1 DAC Sel 0
(Address Select) 0/1 0/1 0 0 0 0 0 (A0 and A1 should correspond to the package address set via pins 13 and 14.) 0 0 1 0 0 0 0 0 1 1 0 X X X X X X X X 0 0 1 1 See Below 0 1 0 1 0 0 0 0 1 0 1 0 1 Data Data Data Data (see Table I) Data (see Table I) Data (see Table I) 0 0 0 This address selects 1 of 4 possible devices on a single SPI data bus based on each device's address pin(s) state. Write To Buffer A w/Data Write To Buffer B w/Data Write To Buffer C w/Data Write To Buffer D w/Data Write To Buffer (selected by DB17 and DB18) w/Power-Down Command Write To Buffer w/Data and Load DAC (selected by DB17 and DB18) Write To Buffer w/Power-Down Command and Load DAC (selected by DB17 and DB18) Write To Buffer w/Data (selected by DB17 and DB18) and Load All DACs Write To Buffer w/Power-Down Command (selected by DB17 and DB18) and Load All DACs
(00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) (00, 01, 10, or 11) Broadcast Modes
1
0
X
X X X
X X X
1 1 1
1 1 1
X X X
0 1 1
X X X
X 0 1 (see Table I)
X Data 0
Load All DACs, All Device, and All Buffers with Stored Data Write To All Devices and Load All Dacs, with SR Data Write To All Devices w/Power-Down Command in SR
TABLE II. Control Matrix.
24th Falling Edge SCLK 1 2 1 2
24th Falling Edge
SYNC Invalid Write-Sync Interrupt: SYNC HIGH Before 24th Falling Edge DIN DB23 DB22 DB0 Valid Write-Buffer/DAC Update: SYNC HIGH After 24th Falling Edge DB23 DB22 DB1 DB0
FIGURE 4. Interrupt and Valid SYNC Timing. single 16-bit DAC with power-down circuitry, a temporary storage register (TR), and a DAC register (DR). TR and DR are both 18-bit wide. Two MSBs represent power-down condition and 16LSBs represent data for TR and DR. By adding bits 17 and 18 to TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that DB15 and DB14 get transfered to TR17 and TR16 (DR17 and DR16), when DB16 = 1. The DAC8534 treats the power-down condition like data and all the operational modes are still valid for power-down. It is possible to broadcast a power-down condition to all the DAC8534s in a system, or it is possible to simultaneously power-down a channel while updating data on other channels. DB16, DB15, and DB14 = 100 represents a power-down condition with Hi-Z output impedance for a selected channel. Same is true for 111. 101 represents a power-down condition with 1k output impedance and 110 represents a power-down condition with 100k output impedance. When both bits are set to 0 or 1, the device enters a highimpedance state with a typical power consumption of 3pA at 5V. For the two low impedance output modes, however, the supply current falls to 100nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: the output is connected internally to GND through a 1k resistor, a 100k resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 5. All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 is set to 0, new data is written to the Data Buffer, and the DAC channel receives a "Load" command. The time to exit powerdown is typically 2.5s for AVDD = 5V and 5s for AVDD = 3V (see the Typical Characteristics).
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Resistor String DAC
Amplifier
VOUTX
Power-down Circuitry
Resistor Network
FIGURE 5. Output Stage During Power-Down (High-Impedance).
OPERATION EXAMPLES
Example 1: Write to Data Buffer A; Through Buffer D; Load DAC A Through DAC D Simultaneously * 1st--Write to Data Buffer A:
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 0 DAC Sel 0 0 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 2nd--Write to Data Buffer B:
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 0 DAC Sel 0 1 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 3rd--Write to Data Buffer C:
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 1 DAC Sel 0 0 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 4th--Write to Data Buffer D and simultaneously update all DACs:
A1 0 A0 0 LD1 1 LD0 0 DC X DAC Sel 1 1 DAC Sel 0 1 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the 4th write sequence. (The "Load" command moves the digital data from the data buffer to the DAC register at which time the conversion takes place and the analog output is updated. "Completion" occurs on the 24th falling SCLK edge after SYNC LOW.) Example 2: Load New Data to DAC A Through DAC D Sequentially * 1st--Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 0 DAC Sel 0 0 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 2nd--Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 0 DAC Sel 0 1 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 3rd--Write to Data Buffer C and Load DAC C: DAC C output settles to specified value upon completion:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 1 DAC Sel 0 0 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
* 4th--Write to Data Buffer D and Load DAC D: DAC D output settles to specified value upon completion:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 1 DAC Sel 0 1 PD0 0 DB15 D15 ...... ..... DB1 D1 DB0 D0
After completion of each write cycle, DAC analog output settles to the voltage specified. Example 3: Power-Down DAC A and DAC B to 1k and Power-Down DAC C and DAC D to 100k Simultaneously * Write power-down command to Data Buffer A: DAC A to 1k.
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 0 DAC Sel 0 0 PD0 1 DB15 0 DB14 1 DB13 X ........ ........
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* Write power-down command to Data Buffer B: DAC B to 1k.
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 0 DAC Sel 0 1 PD0 1 DB15 0 DB14 1 DB13 X ........ ........
* Write power-down command to Data Buffer C: DAC C to 100k.
A1 0 A0 0 LD1 0 LD0 0 DC X DAC Sel 1 1 DAC Sel 0 0 PD0 1 DB15 1 DB14 0 DB13 X ........ ........
* Write power-down command to Data Buffer D: DAC D to 100k and Simultaneously Update all DACs.
A1 0 A0 0 LD1 1 LD0 0 DC X DAC Sel 1 1 DAC Sel 0 1 PD0 1 DB15 1 DB14 0 DB13 X ........ ........
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon completion of the 4th write sequence. Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially: * Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 0 DAC Sel 0 0 PD0 1 DB15 1 DB14 1 DB13 X ........ ........
* Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 0 DAC Sel 0 1 PD0 1 DB15 1 DB14 1 DB13 X ........ ........
* Write power-down command to Data Buffer C and Load DAC C: DAC C output = High-Z:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 1 DAC Sel 0 0 PD0 1 DB15 1 DB14 1 DB13 X ........ ........
* Write power-down command to Data Buffer D and Load DAC D: DAC D output = High-Z:
A1 0 A0 0 LD1 0 LD0 1 DC X DAC Sel 1 1 DAC Sel 0 1 PD0 1 DB15 1 DB14 1 DB13 X ........ ........
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the 1st, 2nd, 3rd, and 4th write sequences, respectively.
LDAC FUNCTIONALITY
The DAC8534 offers both a software and hardware simultaneous update function. The DAC8534 double-buffered architecture has been designed so that new data can be entered for each DAC without distrubing the analog outputs. The software simultaneous update capability is controlled by the Load 1 (LD1) and Load 0 (LD0) control bits. By setting Load 1 equal to "1" all of the DAC registers will be updated on the falling edge of the 24th clock signal. When the new data has been entered into the device, all of the DAC outputs can be updated simultaneously and synchronously with the clock. The internal DAC register is edge triggered and not level triggered, therefore, when the LDAC pin signal is transitioned from LOW to HIGH, the digital word currently in the DAC input register is latched. Additionally, it allows the DAC input registers to be written to at any point, then the DAC output voltages can be asynchronously changed via the LDAC pin. The LDAC trigger should only be used after the buffers are properly updated through software. If DAC outputs are desired to be updated through software only, the LDAC pin must be tied low permanently.
MICROPROCESSOR INTERFACING
DAC8534 to 8051 INTERFACE
See Figure 6 for a serial interface between the DAC8534 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8534, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8534, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second and third write cycle is initiated to transmit the remaining data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which presents the LSB first, while the DAC8534 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and "mirror" the data as needed.
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DAC8534 to TMS320 DSP INTERFACE
80C51/80L51(1) P3.3 TXD RXD NOTE: (1) Additional pins omitted for clarity. DAC8534(1) SYNC SCLK DIN
DAC8534 AVDD 0.1F TMS320 DSP 10F Positive Supply
Figure 9 shows the connections between the DAC8534 and a TMS320 Digital Signal Processor (DSP). A Single DSP can control up to four DAC8534s without any interface logic.
FIGURE 6. DAC8534 to 80C51/80L51 Interface.
DAC8534 to Microwire INTERFACE
Figure 7 shows an interface between the DAC8534 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8534 on the rising edge of the CK signal.
FSX DX CLKX
SYNC VOUTA DIN SCLK VOUTD VREFH VREFL GND 0.1F Output A Output D Reference Input 1F to 10F
MicrowireTM CS SK SO NOTE: (1) Additional pins omitted for clarity.
DAC8534(1) SYNC SCLK DIN
FIGURE 9. DAC8534 to TMS320 DSP.
APPLICATIONS
CURRENT CONSUMPTION
The DAC8534 typically consumes 250A at AVDD = 5V and 225A at AVDD = 3V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH << IOVDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200nA per channel. A delay time of 10ms to 20ms after a powerdown command is issued to the DAC is typically sufficient for the power-down current to drop below 10A.
Microwire is a registered trademark of National Semiconductor.
FIGURE 7. DAC8534 to Microwire Interface.
DAC8534 to 68HC11 INTERFACE
Figure 8 shows a serial interface between the DAC8534 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8534, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC8534 output stage is capable of driving loads of up to 1000pF while remaining stable. Within the offset and gain error margins, the DAC8534 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2k can be driven by the DAC8534 while achieving a typical load regulation of 1%. As the load resistance drops below 2k, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 20mV of the DAC's output voltage characteristic. The reference voltage applied to the DAC8534 may be reduced below the supply voltage applied to AVDD in order to eliminate this condition if good linearity is a requirement at full-scale (under resistive loading conditions).
68HC11(1) PC7 SCK MOSI NOTE: (1) Additional pins omitted for clarity.
DAC8534(1) SYNC SCLK DIN
FIGURE 8. DAC8534 to 68HC11 Interface. The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCLK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8534, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure.
CROSSTALK AND AC PERFORMANCE
The DAC8534 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full-
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scale change on the neighboring channel is typically less than 0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under -100dB. In addition, the DAC8534 can achieve typical AC performance of 96dB SNR (Signal-to-Noise Ratio) and 65dB THD (Total Harmonic Distortion), making the DAC8534 a solid choice for applications requiring high SNR at output frequencies at or below 4kHz.
USING THE REF02 AS A POWER SUPPLY FOR THE DAC8534
Due to the extremely low supply current required by the DAC8534, a possible configuration is to use a REF02 +5V precision voltage reference to supply the required voltage to the DAC8534's supply input as well as the reference input, as shown in Figure 10. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8534. If the REF02 is used, the current it needs to supply to the DAC8534 is 1.085mA typical and 1.78mA max for AVDD = 5V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5k load on a given DAC output) is: 1.085mA + (5V/ 5k) = 2.085mA
OUTPUT VOLTAGE STABILITY
The DAC8534 exhibits excellent temperature stability of 5ppm/C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a 25V window for a 1C ambient temperature change. Good Power-Supply Rejection Ratio (PSRR) performance reduces supply noise present on AVDD from appearing at the outputs to well below 10V-s. Combined with good DC noise performance and true 16-bit differential linearity, the DAC8534 becomes a perfect choice for closed-loop control applications.
+15
+5V REF02
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 16-bit accurate range of the DAC8534 is achievable within 10s for a full-scale code change at the input. Worst-case settling times between consecutive code changes is typically less than 2s, enabling update rates up to 500ksps for digital input signals changing code-to-code. The high-speed serial interface of the DAC8534 is designed in order to support these high update rates. For full-scale output swings, the output stage of each DAC8534 channel typically exhibits less than 100mV of overshoot and undershoot when driving a 200pF capacitive load. Code-to-code change glitches are extremely low given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal segmentation of the DAC8534, code-to-code glitches occur at each crossing of an Nx4096 code boundary. These glitches can approach 100nVs for N = 15, but settle out within ~2s.
SYNC 3-Wire Serial Interface SCLK DIN
AIDD + IREF AVDD, VREF DAC8534 VOUT = 0V to 5V
FIGURE 10. REF02 as a Power Supply to the DAC8534.
BIPOLAR OPERATION USING THE DAC8534
The DAC8534 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 11. The circuit shown will give an output voltage range of VREF. Rail-to-rail operation at the amplifier output is achievable using an amplifier such as the OPA703, as shown in Figure 11.
R2 10k +5V
+5V
R1 10k OPA703 DAC8534 AVDD, VREF 10F 0.1F -5V VOUTX
5V
(Other pins omitted for clarity.)
FIGURE 11. Bipolar Operation with the DAC8534.
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The output voltage for any input code can be calculated as follows: D R1 + R 2 VOUT X = VREF * - VREF * 65536 R1 R * 2 R1
where D represents the input code in decimal (0-65535). With VREF = 5V, R1 = R2 = 10k:
10 * D VOUT X = - 5V 65536
The power applied to AVDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, AVDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1F to 10F capacitor in parallel with a 0.1F bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100F electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors--all designed to essentially low-pass filter the supply, removing the highfrequency noise. Up to four DAC8534 devices can be used on a single SPI bus without any glue logic to create a high channel count solution. Special attention is required to avoid digital signal integrity problems when using multiple DAC8534s on the same SPI bus. Signal integrity of SYNC, SCLK, and DIN lines will not be an issue as long as the rise times of these digital signals are longer than six times the propagation delay between any two DAC8534 devices. Propagation speed is approximately six inches/ns on standard PCBs. Therefore, if the digital signal risetime is 1ns, the distance between any two DAC8534 devices is recommended not to exceed 1 inch. If the DAC8534s have to be further apart on the PCB, the signal rise times should be reduced by placing series resistors at the drivers for SYNC, SCLK, and DIN lines. If the largest distance between any two DAC8534s has to be six inches, the risetime should be reduced to 6ns with an RC network formed by the series resistor at the digital driver and the total trace and input capacitance on the PCB.
This is an output voltage range of 5V with 0000H corresponding to a -5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a 2.5V output voltage range can be achieved.
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8534 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8534, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system.
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MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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