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| Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller 25 MHz C165 Specification 07.95 Preliminary C165 Revision History: Previous Releases: Page 8 9 10 12 13 14 07.95 Original Version 25 MHz 09.94 (20 MHz) Subjects (changes since last revision) External Clock Drive Specification changed. t6, t14, t15, t16, t17 updated. t22 updated. t6, t14, t15, t16, t17, t22 updated. t55 updated. t35, t36, t59, t16, t17, t22 updated. Edition 07.95 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation Balanstrae 73, D-81541 Munchen. (c) Siemens AG 1995. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Offices of Siemens Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the type in question please contact your nearest Siemens Office, Components Group. Siemens AG is an approved CECC manufacturer. C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C165 16-Bit Microcontroller, 25 MHz q q q q q q q q q q q q q q q q q q q q q q q q C165 q q q High Performance 16-bit CPU with 4-Stage Pipeline 80 ns Instruction Cycle Time at 25-MHz CPU Clock 400 ns Multiplication (16 x 16 bits), 800 ns Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip RAM 4 KBytes On-Chip ROM (RM types only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 40 ns Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) Programmable Watchdog Timer Up to 77 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin MQFP Package (EIAJ) 100-Pin TQFP Package (Thin QFP) This document describes specific items relevant for operation at 25 MHz. For functional descriptions please refer to the standard C165 data sheet. This document describes the SAB-C165-L25M, the SAB-C165-L25F, the SAB-C165-R25M and the SAB-C165-R25F. For simplicity all versions are referred to by the term C165 throughout this document. 1 07.95 C165 11Jul97@13:26h Intermediate Version Ordering Information: Type SAB-C165-R25M Ordering Code Q67121-D... Package P-MQFP-100-2 Function 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C SAB-C165-L25M Q67121-C1005 P-MQFP-100-2 SAB-C165-R25F Q67121-D... P-TQFP-100-3 SAB-C165-L25F Q67121-C1004 P-TQFP-100-3 Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group 2 11Jul97@13:26h Intermediate Version C165 Pin Configuration MQFP Package (top view) C165 Figure 1 3 Semiconductor Group C165 11Jul97@13:26h Intermediate Version Pin Configuration TQFP Package (top view) C165 Figure 2 Semiconductor Group 4 11Jul97@13:26h Intermediate Version C165 Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F....................... 0 to +70 C Storage temperature (TST)......................................................................................... - 65 to +150 C Voltage on VCC pins with respect to ground (VSS) ....................................................... -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) ...................................................-0.5 to VCC +0.5 V Input current on any pin during overload condition .................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VIN DC Characteristics VCC = 5 V 10 %; VSS = 0 V; TA = 0 to +70 C Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 fCPU = 25 MHz; Symbol min. Reset active Limit Values max. 0.2 VCC - 0.1 Unit V V V V Test Condition - - - - VIL VIH SR - 0.5 SR 0.2 VCC + 0.9 VCC + 0.5 VCC + 0.5 VCC + 0.5 VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC 5 Semiconductor Group C165 11Jul97@13:26h Intermediate Version Parameter Symbol min. Limit Values max. 0.45 Unit Test Condition Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) V IOL = 2.4 mA VOL1 CC - 0.45 - V V IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VCC 0 V < VIN < VCC - Output high voltage VOH CC 0.9 VCC 2.4 (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs) 1) VOH1 CC 0.9 VCC 2.4 - 200 500 150 -40 - 40 - -40 - -10 - 20 10 10 + 4 * fCPU 2+ 1.2 * fCPU 100 V V nA nA k A A A A A A A A A pF mA mA A Input leakage current (Port 5) Input leakage current (all other) RSTIN pullup resistor Read/Write inactive current Read/Write active current ALE inactive current ALE active current 4) 4) 4) 4) 4) IOZ1 CC - IOZ2 CC - RRST CC 50 IRWH IRWL IALEL IALEH IP6H IP6L 4) 2) 3) 2) 3) 2) 3) 2) 3) - -500 - 500 - -500 - -100 VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VCC Port 6 inactive current Port 6 active current 4) PORT0 configuration current XTAL1 input current Pin capacitance (digital inputs/outputs) Power supply current Idle mode supply current 5) IP0H IP0L IIL CIO ICC IID IPD CC - CC - - - - f = 1 MHz TA = 25 C RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply current VCC = 5.5 V 7) Semiconductor Group 6 11Jul97@13:26h Intermediate Version C165 Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and 25 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 2) 3) 4) 5) 6) 7) 150 I [mA] ICCmax A 100 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ICCtyp AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 50 10 AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 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Frequency 7 Semiconductor Group C165 11Jul97@13:26h Intermediate Version AC Characteristics External Clock Drive XTAL1 VCC = 5 V 10 %; TA = 0 to +70 C Parameter VSS = 0 V Symbol Max. CPU Clock = 25 MHz min. max. 20 - - 5 1) Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. 20 5 1) 5 - - 1) Unit max. 500 - - 5 1) Oscillator period High time Low time Rise time Fall time 1) tOSC SR 20 t1 t2 t3 t4 SR 5 1) SR 5 SR - SR - 1) ns ns ns ns ns 5 1) 5 1) The clock input signal must reach the defined levels VIL and VIH2. Figure 4 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values tA tC tF TCL * 1) 2TCL * (15 - Semiconductor Group 8 11Jul97@13:26h Intermediate Version C165 AC Characteristics Multiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD max. - - - - - 5 25 - - 25 + tC 45 + tC 45 + tA + tC 55 + 2tA + tC - 25 + tF Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. TCL - 10 + tA TCL - 17.5 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - max. - - - - - 5 TCL + 5 - - 2TCL - 15 + tC 3TCL - 15 + tC 3TCL - 15 + tA + tC 4TCL - 25 + 2tA + tC - 2TCL - 15 + tF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 CC 10 + tA CC 2.5 + tA CC 10 + tA CC 10 + tA CC -10 + tA CC - CC - CC 30 + tC CC 50 + tC SR - SR - SR - SR - SR 0 SR - 9 Semiconductor Group C165 11Jul97@13:26h Intermediate Version Parameter Symbol Max. CPU Clock = 25 MHz min. max. - - - - 10 - tA 40 + tC + 2tA - - - 0 20 15 + tC 35 + tC - - - - 20 + tF Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. 2TCL - 20 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF -5 - tA - 3TCL - 15 + tF TCL - 5 + tA -5 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - max. - - - - 10 - tA 3TCL - 20 + tC+2tA - - - 0 TCL 2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF Unit Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS t22 t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 CC 20 + tC CC 25 + tF CC 25 + tF CC 25 + tF CC -5 - tA SR - CC 45 + tF CC 15 + tA CC -5 + tA CC - CC - SR - SR - CC 30 + tC CC 50 + tC CC 25 + tC SR 0 SR - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Semiconductor Group 10 11Jul97@13:26h Intermediate Version C165 Parameter Symbol Max. CPU Clock = 25 MHz min. max. - - Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. 2TCL - 20 + tF 2TCL - 20 + tF max. - - Unit Address hold after RdCS, WrCS Data hold after WrCS t54 t56 CC 20 + tF CC 20 + tF ns ns 11 Semiconductor Group C165 11Jul97@13:26h Intermediate Version AC Characteristics Demultiplexed Bus VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR Data hold after WR max. - - - - - - 25 + tC 45 + tC 45 + tA + tC 55 + 2tA + tC - 25 + tF 10 + tF - - Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. TCL - 10 + tA TCL - 17.5 + tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 20 + tC TCL - 10 + tF max. - - - - - - 2TCL - 15 + tC 3TCL - 15 + tC 3TCL - 15 + tA + tC 4TCL - 25 + 2tA + tC - 2TCL - 15 + 2tA + tF 1) TCL - 10 + 2tA + tF 1) - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 CC 10 + tA CC 2.5 + tA CC 10 + tA CC -10 + tA CC 30 + tC CC 50 + tC SR - SR - SR - SR - SR 0 SR - SR - CC 20 + tC CC 10 + tF Semiconductor Group 12 11Jul97@13:26h Intermediate Version C165 Parameter Symbol Max. CPU Clock = 25 MHz min. max. - - 10 - tA 40 + tC + 2tA - - - 15 + tC 35 + tC - - - - 20 + tF 0 + tF - - Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. -10 + tF 0 + tF -5 - tA - TCL - 15 + tF TCL - 5 + tA -5 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 15 + tC 0 - - -10 + tF TCL - 15 + tF max. - - 10 - tA 3TCL - 20 + tC+2tA - - - 2TCL - 25 + tC 3TCL - 25 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - Unit ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t26 t28 t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57 CC -10 + tF CC 0 + tF CC -5 - tA SR - CC 5 + tF CC 15 + tA CC -5 + tA SR - SR - CC 40 + tC CC 50 + tC CC 25 + tC SR 0 SR - SR - CC -10 + tF CC 5 + tF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1) RW-delay and tA refer to the next following bus cycle. 13 Semiconductor Group C165 11Jul97@13:26h Intermediate Version AC Characteristics CLKOUT and READY VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 40 - - 5 5 10 + tA - - - - - 0 + 2tA + tC + tF 2) Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. 2TCL TCL - 5 TCL - 10 - - 0 + tA 15 5 2TCL + 15 15 5 0 max. 2TCL - - 5 5 10 + tA - - - - - Unit t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60SR CC 40 CC 15 CC 10 CC - CC - CC 0 + tA SR 15 SR 5 SR 55 SR 15 SR 5 0 ns ns ns ns ns ns ns ns ns ns ns TCL - 25 ns + 2tA + tC + tF 2) Notes 1) 2) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Semiconductor Group 14 11Jul97@13:26h Intermediate Version C165 AC Characteristics External Bus Arbitration VCC = 5 V 10 %; VSS = 0 V TA = 0 to +70 C CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 25 MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive max. - 20 20 20 25 20 25 Variable CPU Clock 1 / 2TCL = 1 to 25 MHz min. 20 - - - -5 - -5 max. - 20 20 20 25 20 25 ns ns ns ns ns ns ns Unit t61 t62 t63 t64 t65 t66 t67 SR 20 CC - CC - CC - CC -5 CC - CC -5 15 Semiconductor Group C165 11Jul97@13:26h Intermediate Version SAF-C165-L25M: Q67121-C1007 Semiconductor Group 16 |
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