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CDB43L42
Evaluation Board for CS43L42 Rev. D
Features
l Demonstrates
Description
The CDB43L42 evaluation board is an excellent means for quickly evaluating the CS43L42 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS43L42 (for control port mode only) and a power supply. Analog headphone outputs are provided via a 1/8" headphone jack and RCA phono jacks. Line outputs are provided via RCA phono jacks. The CS8415A digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB43L42 Evaluation Board
recommended layout and grounding arrangements l CS8415A receives AES/EBU, S/PDIF, and EIAJ-340 Compatible Digital Audio l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system
I/O for Clocks and Data
Control Port Microcontroller
Control Port Interface
CS8415A Digital Audio Interface
Headphone Outputs CS43L42 Line Level Outputs
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
SEP `00 DS481DB1 1
CDB43L42
TABLE OF CONTENTS
1. CDB43L42 SYSTEM OVERVIEW .................................................................. 4 2. CS43L42 DIGITAL TO ANALOG CONVERTER ............................................ 4 3. CS8415A DIGITAL AUDIO RECEIVER ......................................................... 4 4. CS8415A DATA FORMAT ............................................................................. 4 5. HEADPHONE OUTPUT .................................................................................. 4 6. LINE OUTPUT ................................................................................................ 4 7. INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 4 8. POWER SUPPLY CIRCUITRY ....................................................................... 4 9. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 5 10. CONTROL PORT SOFTWARE .................................................................... 5 11. POPGUARD(R) IMPROVEMENT ................................................................... 5 12. CDB43L42 PERFORMANCE PLOTS ......................................................... 5
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .............................................. 7 Figure 2. CS43L42 .............................................................................................. 8 Figure 3. Headphone Outputs ............................................................................. 9 Figure 4. CS8415A Digital Audio Receiver ....................................................... 10 Figure 5. Digital Audio Inputs ............................................................................ 11 Figure 6. MCLK Divider and Level Shifter ......................................................... 12 Figure 7. Control Port Interface ......................................................................... 13 Figure 8. Control Port Microcontroller ............................................................... 14 Figure 9. Control Port Level Shifter ................................................................... 15 Figure 10.I/O for Clocks and Data ...................................................................... 16 Figure 11.Reset Circuit ....................................................................................... 17 Figure 12.Line Level Outputs ............................................................................. 18 Figure 13.Power Supply ..................................................................................... 19 Figure 14.Headphone Output - Frequency Response at 1.8 V .......................... 20 Figure 15.Headphone Output - Frequency Response at 3.0 V .......................... 20 Figure 16.Headphone Output - THD+N versus Amplitude at 1.8 V .................... 20 Figure 17.Headphone Output - THD+N versus Amplitude at 3.0 V .................... 20 Figure 18.Headphone Output - FFT of 1 kHz Sine Wave at 1.8 V ..................... 20 Figure 19.Headphone Output - FFT of 1 kHz Sine Wave at 3.0 V ..................... 20 Figure 20.Line Output - Frequency Response at 1.8 V ...................................... 21
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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Figure 21.Line Output - Frequency Response at 3.0 V ...................................... 21 Figure 22.Line Output - THD+N versus Amplitude at 1.8 V ............................... 21 Figure 23.Line Output - THD+N versus Amplitude at 3.0 V ............................... 21 Figure 24.Line Output - FFT of 1 kHz Sine Wave at 1.8 V ................................. 21 Figure 25.Line Output - FFT of 1 kHz Sine Wave at 3.0 V ................................. 21 Figure 26.Silkscreen Top ................................................................................... 22 Figure 27.Top Side ............................................................................................. 23 Figure 28.Bottom Side ....................................................................................... 24
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CDB43L42
1. CDB43L42 SYSTEM OVERVIEW
The CDB43L42 evaluation board is an excellent means of quickly evaluating the CS43L42. The CS8415A digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB43L42 schematic has been partitioned into 12 schematics shown in Figures 2 through 13. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics.
5. HEADPHONE OUTPUT
A 1/8 inch, stereo headphone jack is included on the evaluation board for connecting 16 ohm or greater headphones to the CS43L42. If no headphones are connected to the 1/8 inch jack, then a 16 ohm resistor is connected to each of the CS43L42 headphone outputs, HP_A and HP_B. This is useful when evaluating the CS43L42 headphone amplifier with test equipment that has highimpedance inputs. RCA jacks are also provided on the headphone outputs for easy connection to test equipment.
6. LINE OUTPUT
The CS43L42 line level outputs are available via RCA jacks. An external mute circuit is included on the CDB43L42 to ensure an absolute minimum of extraneous clicks and pops during power-up. See Figure 12 for details.
2. CS43L42 DIGITAL TO ANALOG CONVERTER
A description of the CS43L42 is included in the CS43L42 datasheet.
3. CS8415A DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8415A Digital Audio Receiver, Figure 4. The outputs of the CS8415A include a serial bit clock, serial data, leftright clock (FSYNC), de-emphasis control and a 256 x Fs master clock. The operation of the CS8415A and a discussion of the digital audio interface are included in the CS8415A datasheet. The evaluation board has been designed such that the input can be either optical or coax, see Figure 5. However, both inputs cannot be driven simultaneously.
7. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, HDR1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 10.
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts (GND, +5 V, VL, VA, VA_HP, and VA_LINE), see Figure 13. The +5 V input supplies power to the +5 Volt digital circuitry (VA_+5, VD_+5), while the VL input supplies power to the Voltage Level Converters and the CS43L42 VL pin. VA, VA_HP, and VA_LINE supply power to the CS43L42. For ease of use, it is possible to connect VA, VA_HP, VL, and VA_LINE to the same supply. WARNING: VA, VL, and VA_LINE must be between +1.7V and +3.6V. VA_HP must be between
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4. CS8415A DATA FORMAT
The CS8415A data format is selected via software when in Control Port mode. When in Stand-Alone mode the CS8451A data format is selected via the DIP switch. See Table 2 for details.
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CDB43L42
+0.9 V and +3.6 V. Operation outside of this range can cause permanent damage to the device. See the CS43L42 datasheet for more details.
11. POPGUARD(R) IMPROVEMENT
The CDB43L42 Rev A includes a hardware improvement for the PopGuard(R) Transient Control feature of the CS43L42 Rev D. Please see the CS43L42 errata for further details. This additional hardware includes the transistors Q1, Q2, Q4, and Q5 as well as R13, R14, R24, R33, R34, and C7. Please refer to Figure 3. To bypass this hardware improvement, stuff R18 and R19 with 0 ohm resistors and change R25 and R26 to 1 k ohm resistors.
9. GROUNDING AND POWER SUPPLY DECOUPLING
The CS43L42 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 2 details the power distribution used on this board. The decoupling capacitors are located as close to the CS43L42 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise. See Figures 26-28 for the CDB43L42 PCB layout artwork.
12. CDB43L42 PERFORMANCE PLOTS
The CDB43L42 Rev A performance plots shown in Figures 14 through 25 were generated using an Audio Precision System Two Cascade with the S2AES17LP 20 kHz brickwall filter applied. All tests were performed at a sampling rate of 48 kHz and with VL, VA, VA_HP, and VA_LINE set to the indicated voltage supply. Please note that due to the architecture of the Audio Precision systems, either the S2-AES17LP 20 kHz brickwall filter must be installed or a low pass filter must be used between the CDB43L42 and the Audio Precision for proper measurements. If an external filter is used, it must provide at least 15 dB of attenuation at 120 kHz. This can be achieved with a simple 3-pole filter.
10. CONTROL PORT SOFTWARE
The CDB43L42 is shipped with Windows based software for interfacing with the CS43L42 control port via the serial connector, J1. The software can be used to communicate with the CS43L42 in Two Wire mode. Note: DIP 2-4 must be set appropriately for control port mode operation.
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CDB43L42
CONNECTOR +5 V VA, VL, VA_LINE VA_HP GND Coax Input Optical Input HDR1 Serial Port HDR2 HP_A (J3) HP_B (J2) HP_A&B (J10) AOUTA ( ) AOUTB ( )
INPUT/OUTPUT Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output Output Output Output + 5 Volt power
SIGNAL PRESENT + 1.8 Volt to + 3.3 Volt power for the CS43L42 and the Voltage Level Converters +0.9 Volt to +3.3 Volt power for the CS43L42 headphone amp Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical I/O for master, serial, left/right clocks and serial data Serial connection to PC for Two Wire mode control port signals I/O for Two Wire mode control port signals Channel A headphone output Channel B headphone output Channel A and B headphone output Channel A line output Channel B line output
Table 1. System Connections
JUMPER Program/Run HRM/BRM
PURPOSE Programming switch for the control port microcontroller Selects High Rate or Base Rate Mode
POSITION Program *Run HRM (/2) *BRM (x1) INT *EXT *0 1 *000 001 010 011 100
FUNCTION SELECTED Configures CDB43L42 to program the C Configures CDB43L42 for normal operation Selects High Rate Mode Selects Base Rate Mode Internal SCLK Mode External SCLK Mode CS8415A is enabled (HDR1 is an output) Disabled (External Clocks and Data are input via HDR1) Control Port mode Stand Alone mode, I2S Stand Alone mode, LJ24 Stand Alone mode, RJ16 (8415A not avail.) Stand Alone mode, RJ24
EXT/INT SCLK Selects SCLK Mode Reset (S1) DIP 1 Resets the CDB43L42 Enable/Disable the CS8415A
DIP 2-4
Configures the interface format and CS43L42 operational mode
Notes: *Default factory settings Table 2. CDB43L42 Jumper and Switch settings
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Control Port Interface Fig 7
Reset DIF0 DIF1
Control Port Microcontroller Fig 8
I/O for Clocks and Data Fig 10 Digital Audio Inputs Fig 5 RXN RXP CS8415A Digital Audio Receiver Connections Fig 4 MCLK LRCK SCLK SDATA
Reset Circuit Fig 11
Control Port Level Shifter Fig 9 Headphone Outputs
MCLK Divider and Level Shifter Fig 6
MCLK LRCK SCLK SDATA
Fig 3 CS43L42 Fig 2 Line Level Outputs Fig 12
CDB43L42
Figure 1. System Block Diagram and Signal Flow
7
GND
CP/SA
8
RST_A LRCK_A SDATA_A AD0/CS/DEM0_A SCLK/DEM1_A VA_HP
U1
VL
C53
24 23 22 21 20 19 18 17 16 15 14 13
C51 .1UF X7R
GND
/RST LRCK SDATA AD0/CS/DEM0 SCLK/DEM1 MCLK SCL/CCLK/DIF1 SDA/CDIN/DIF0
MCLK_B SCL/CCLK/DIF1_A SDA/CDIN/DIF0_A
1 2 3 4 5 6 7 8 9 10 11 12
/RST MUTEC LRCK AOUTA SDATA AOUTB AD0//CS/DEM0 HP_B SCLK/DEM1 VA_HP VD_IO VA_LINE MCLK VA SCL/CCLK/DIF1 GND HP_A SDA/CDIN/DIF0 GND_IO VQ_LINE FILT+ CP//SA VQ_HP REF_GND CS43L42
MUTEC AOUTA AOUTB HP_B
MUTEC AOUTA AOUTB HP_B
.1UF X7R
GND
HP_A
HP_A
VA
VA_LINE
C47 1UF X7R
GND GND
C46 1UF X7R
GND
C52 .1UF X7R
GND
C50 .1UF X7R
GND
C48 1UF X7R
GND
CDB43L42
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Figure 2. CS43L42
1
3
C19
HP_B
220UF 220UF R25 150 R26 150
L6 47UH R18 R19
3 2
2
GND
GND MUTE
1
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J3
3 NC 4 1 2
Q2 MGSF1N02ELT1 0 0
CON_RCA_RA
GND
1 2 3 4 5
J10
C43
HP_A
L8 47UH Q1 MGSF1N02ELT1 R24 R43 1M J2
3 1
R23 16
R22 16
GND
STEREO_JACK
100K
NC 4 2 CON_RCA_RA
GND
GND
GND
GND HP_A HP_B
3
U6
IC_RESET
9 8
3
R33
47K R34 39K C7
1
Q4 2SC3326
2
1
Q5 2SC3326
2
SN74HCT04D
1UF X7R
GND GND GND
R13 180
R14 180
GND
CDB43L42
Figure 3. Headphone Outputs 9
10
U4 R20
/EMPH VA_84
47K
VA_84 RXP RXN
C9 10UF
GND
C22 .1UF X7R
GND RESET_84 MCLK_84
1 2 3 4 5 6 7 8 9 10 11 12 13 14
COPY VD2+ /EMPH RXP RXN VA+ AGND FILT /RST RMCK RERR RCBL PRO CHS
ORIG VD3+ C U H//S VD+ DGND DGNG2 DGND3 AUDIO SDOUT OLRCK OSCLK NVERR
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R30
47K
ORIG
VA_84
C31
SDATA_84
R21
LRCK_84 SCLK_84
47K
VA_84
.1UF X7R
GND
R7 5.1K C2 .082UF X7R
GND
CS8415A_CZ
GND (SPDIF ERROR) GND
C14 R6 2200PF COG 5.1K
LED_CMD2821SRC_T1 D1 13
U6
12
SN74HCT04D
GND GND
11
U6
10
SN74HCT04D
GND
VD_+5
C54 .1UF X7R U12
DIR LRCK_84 LRCK SCLK_84 SCLK/DEM1
1 2 3 4 5 6 7
GND
1/OE 1A 1B 2/OE 2A 2B GND
VCC 4/OE 4A 4B 3/OE 3A 3B
14 13 12 11 10 9 8
MCLK_84 MCLK SDATA_84 SDATA
SN74CBT3125DB
GND
CDB43L42
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Figure 4. CS8415A Digital Audio Receiver
CDB43L42
OPTICAL INPUT
OPT1
6 1 2
C29 L7
.01UF X7R
RXP
3 4 5
C30 .01UF X7R
GND
47UH
VD_+5
TORX173
GND
GND
DIGITAL INPUT
J5 NC 2 CON_RCA_RA
3 4 1
C28 R29 75
.01UF X7R
RXN
GND
GND
Figure 5. Digital Audio Inputs
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11
CDB43L42
U3
1 2 4 5 10 9 13 12
VCC 1/G 1A 2/G 2A 3/G 3A 4/G 4A 1Y 2Y 3Y 4Y GND
8
14 3 6
VL SDATA_A LRCK_A SCLK/DEM1_A
SDATA LRCK SCLK_EXT MCLK GND
C39 .1UF X7R
GND
11 7
MCLK_A
74LVC125AD
GND
U5
VL MCLK
4 3 2 1 10 11 12 13
VCC 1/PRE 1CLK 1D 1/CLR 2/PRE 2CLK 2D 2/CLR 1Q 1/Q 2Q 2/Q GND
14 5 6 9 8 7
VL
C8 .1UF X7R
GND (MCLK)
HDR4 HDR1X3 1 2 3
GND
SN74LVC74AD
GND MCLK_B MCLK_A
(HRM /2) (BRM x1)
Figure 6. MCLK Divider and Level Shifter
12
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U2 C5
J1 1 6 2 7 3 8 4 9 5
L5
28 27 26 25 24 23 22 21 20 19 18 17 16 15
.33UF Z5U
DE9F_RA
GND
VD_+5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
C2+ C1+ GND V+ C2VCC VC1T1OUT T1IN T2OUT T2IN T3OUT T3IN R1IN R1OUT R2IN R2OUT T4OUT T4IN R3IN R3OUT T5OUT T5IN FORCEON R1OUTB /FORCEOFF /INVALID MAX3238CAI
C44
.047UF X7R
C27 .1UF X7R
C17 10UF
GND
BLM21A102S
VD_+5
SDA_IN0 GND SCK PD0 TXD MOSI /RESET
C6 .33UF Z5U
GND GND
C1
GND
R16 0
R15 0
.33UF Z5U
GND
GND
CDB43L42
Figure 7. Control Port Interface 13
CDB43L42
VD_+5
R10 R12 R11
10K 10K 10K
1
SW_DIP_4
0 1 2 3 4 S2 GND VD_+5 VL VD_+5
L1
8415A/EXT
OPEN
C15 47UF
GND
BLM21A102S
10K
C32 R9 .1UF X7R
GND GND IC_RESET
RN1 47K
C16 10UF
GND
R40 2K
R41 2K
AD0/CS/DEM0_A CP/SA
VD_+5
44
43
42
41
40
39
38
37
36
35
34
PB4
PB3
PB2
PB1
PB0
NC
VCC
PA0
PA1
PA2
PA3
MOSI_0 SDA_IN0 SCK_0 /RESET PD0
1 2 3 4 5 6
PB5 PB6 PB7 /RESET PD0 NC PD1 PD2 PD3 PD4 PD5 XTAL2 XTAL1 PD6 PD7 GND PC0 PC1 PC2 PC3 PC4 NC U10 AT90S8515_4AC
PA4 PA5 PA6 PA7 ICP NC ALE OC1B PC7 PC6 PC5
33 32 31 30 29 28 27 26 25 24 23
TXD MUTE
7 8
TP7 TP8
ORIG
9 10 11
12
13
14
15
16
17
18
19
20
21
22
/EMPH
TP11
TP13
GND
TP14
RESET_84
Y1
1 3 2 4
3.6864MHZ C21 39PF COG
GND
C24 39PF COG
GND
Figure 8. Control Port Microcontroller
14
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VL
C42 U6 U11
RESET SDA_IN /RESET MOSI /RESET SCK
1 2 4 5 10 9 13 12
U9
4
.1UF X7R VCC
14 3 6 8 11 7
VCC 1/G 1A 2/G 2A 3/G 3A 4/G 4A 1Y 2Y 3Y 4Y GND
8
14 3 6
/RESET VD_+5 SDA_IN0 MOSI_0 SCK_0
3
VL
GND SCL/CCLK/DIF1_A
C26 .1UF X7R R31
GND
SN74HCT04D
RESET SCK_0 MOSI_0
47K
IC_RESET
11 7
1 2 4 5 10 9 13 12
1/G 1A 2/G 2A 3/G 3A 4/G 4A
R28 2K
SDA/CDIN/DIF0_A
1Y 2Y 3Y 4Y GND
R32 47K
RST_A
GND
GND
TC74VHC125FT
GND GND
74LVC125AD
GND
VD_+5
R27 2K U6
SDA_IN
6 5 3
SN74HCT04D Q3 2SC3326
1
2
GND
CDB43L42
Figure 9. Control Port Level Shifter 15
0
R42
16
(INT SCLK) (EXT SCLK)
HDR5 HDR1X3 1 2 3
TP4
R8
10K
SCLK_EXT SCLK/DEM1 GND GND
HDR4X2 HDR2 2 1 4 3 6 5 8 7
SCL/CCLK/DIF1_A SDA/CDIN/DIF0_A AD0/CS/DEM0_A
C40
VD_+5
VCC
8415A/EXT
1
14
.1UF X7R U7
GND
1 13
U6
2
SN74HCT04D GND
7
G1 G2 A1 A2 A3 A4 B1 B2 B3 B4 VCC GND
11 10 9 8 14 7
GND
SDATA LRCK SCLK/DEM1 MCLK
3 4 5 6
HDR5X2 HDR1 1 2 3 4 5 6 7 8 9 10
(SDATA) (LRCK) (SCLK/DEM1) (MCLK)
VD_+5
C41
GND
GND
VA_84
DIR
SN74HC243D
.1UF X7R
GND
CDB43L42
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Figure 10. I/O for Clocks and Data
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R1
VD_+5
5.1K
(PROGRAM)
LED_CMD2821SRC_T1 D2 U8
/RESET VD_+5 GND
/RESET GND VCC
GND
GND
DS1233Z_10
(PROGRAM RUN)
HDR3 HDR1X3 1 2 3
(RESET)
S1
/RESET /RESET
SW_B3W_1100
GND GND GND
C20 100PF COG
GND
CDB43L42
Figure 11. Reset Circuit
17
18
JUMPER
VA
JP9 2 3
C18 Q9 2SC3326
AOUTA
J12 560 R36 C34 C35
1 2
1
MMUN2111LT1 Q7
3
7.5K
R39
1
3.3UF
R17 10K
3 4 NC
AOUTA
2
1500PF 1500PF COG COG
GND GND GND
CON_RCA_RA
GND
GND
3
JUMPER
MUTEC
1
Q6 MMUN2211LT1 7.5K
2
JP8 3
C23 Q8 2SC3326
AOUTB
J11 560 R35 C25 1500PF COG
GND GND
1
R38
1
3.3UF
R5 10K
C33 1500PF COG
GND
2
3 4 NC
AOUTB
CON_RCA_RA
2
GND GND
GND
CDB43L42
Figure 12. Line Level Outputs
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CON_BANANA CON_BANANA
(+5V)
J6
VD_+5
(VA_LINE) (+1.8-3.3v)
J13
L9 C45 47UF
GND
C3 47UF
GND
C4 .1UF X7R
GND
C49 .1UF X7R
GND
BLM21A102S
VA_LINE
CON_BANANA
(GND)
J4
GND
CON_BANANA
(VL) (+1.8-3.3v)
J7
L2 C10 47UF
GND
C38 .1UF X7R
GND
BLM21A102S
VL
CON_BANANA
(VA) (+1.8-3.3v)
J8
L3 C12 47UF
GND
C36 .1UF X7R
GND
BLM21A102S
VA
CON_BANANA
L4 C13 47UF
GND
(VA_HP) (+0.9-3.3v)
J9
C37 .1UF X7R
GND
BLM21A102S
VA_HP
CDB43L42
Figure 13. Power Supply
19
CDB43L42
+1 +0.5 -0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 d B -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 20 50 100 200 500 Hz 1k 2k 5k 10k 20k d B +1 +0.5 -0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 14. Headphone Output Frequency Response at 1.8 V
-74 -75 -76 -77 -78 -79 -80 THD+N -81 -82 -83 -84 (dB)
Figure 15. Headphone Output Frequency Response at 3.0 V
-74 -75 -76 -77 -78 -79 -80
THD+N ( dB)
-81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -91 -92
-85 -86 -87 -88 -89 -90 -91 -92 -93 -60 -55 -50 -45 -40 -35 -30 Amplitude (dB) -25 -20 -15 -10 -5 +0
-93 -60
-55
-50
-45
-40
-35
-30 Amplitude (dB)
-25
-20
-15
-10
-5
+0
Figure 16. Headphone Output THD+N versus Amplitude at 1.8 V
+0 -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 20
d B +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20
Figure 17. Headphone Output THD+N versus Amplitude at 3.0 V
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 18. Headphone Output FFT of 1 kHz Sine Wave at 1.8 V
Figure 19. Headphone Output FFT of 1 kHz Sine Wave at 3.0 V DS481DB1
20
CDB43L42
+2 +1.8 +1.6 +1.4 +1.2 +1 +0.8 +0.6 +0.4 +0.2 d B +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
+2 +1.8 +1.6 +1.4 +1.2 +1 +0.8 +0.6 +0.4 +0.2 d B +0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 20. Line Output - Frequency Response at 1.8 V
-80 -81 -82 -83 -84 -85 THD+N ( dB) d B
Figure 21. Line Output - Frequency Response at 3.0 V
-80 -81 -82 -83 -84 -85
THD+N
-86 -87 -88
-86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -60
(dB)
-89 -90 -91 -92 -93 -94 -95 -60
-55
-50
-45
-40
-35
-30 Amplitude (dB)
-25
-20
-15
-10
-5
+0
-55
-50
-45
-40
-35
-30 Amplitude (dB)
-25
-20
-15
-10
-5
+0
Figure 22. Line Output THD+N versus Amplitude at 1.8 V
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20
Figure 23. Line Output THD+N versus Amplitude at 3.0 V
+0 -10 -20 -30 -40 -50 -60 d B -70 -80 -90 -100 -110 -120 -130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 24. Line Output FFT of 1 kHz Sine Wave at 1.8 V
Figure 25. Line Output FFT of 1 kHz Sine Wave at 3.0 V
DS481DB1
21
22
CDB43L42
DS481DB1
Figure 26. Silkscreen Top
DS481DB1
CDB43L42
Figure 27. Top Side
23
24
CDB43L42
DS481DB1
Figure 28. Bottom Side
* Notes *

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