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CS403 5.0 V, 750 mA Linear Regulator with RESET
The CS403 is a linear regulator specially designed as a post regulator. The CS403 provides low noise, low drift, and high accuracy to improve the performance of a switching power supply. It is ideal for applications requiring a highly efficient and accurate linear regulator. The active RESET makes the device particularly well suited to supply microprocessor based systems. The PNP-NPN output stage assures a low dropout voltage without requiring excessive supply current. Its features include low dropout (1.0 V typically) and low supply drain (4.0 mA typical with IOUT = 500 mA). The CS403 design optimizes supply rejection by switching the internal reference from the supply input to the regulator output as soon as the nominal output voltage is reached. Features * 5.0 V 3.0% Output Voltage * Low Drift * High Efficiency * Short Circuit Protection * Active Delayed Reset * Noise Immunity on Reset * 750 mA Output Current
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TO-220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO-220 FIVE LEAD TVA SUFFIX CASE 314K
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TO-220 FIVE LEAD THA SUFFIX CASE 314A 5
PIN CONNECTIONS AND MARKING DIAGRAM
VOUT Tab = GND Pin 1. VIN 2. RESET 3. GND 4. Delay 5. VOUT
VIN Output Current Limit
Start
CS403 AWLYWW
REF - +
+ -
Error Amp
ICHARGE Delay
1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
Low Voltage INHIBIT Comparator To VOUT + - RESET Delay Comparator
SCR Latch
ORDERING INFORMATION
Device CS403GT5 VCMP GND CS403GTVA5 CS403GTHA5 Package TO-220* STRAIGHT TO-220* VERTICAL TO-220* HORIZONTAL Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail
Figure 1. Block Diagram
*Five lead.
(c) Semiconductor Components Industries, LLC, 2001
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January, 2001 - Rev. 7
Publication Order Number: CS403/D
CS403
ABSOLUTE MAXIMUM RATINGS*
Rating Forward Input Voltage Operating Junction Temperature, TJ Storage Temperature Range, TS Lead Temperature Soldering: 1. 10 second maximum. *The maximum package power dissipation must be observed. Wave Solder: (through hole styles only) (Note 1.) Value 18 -40 to 150 -55 to +150 260 peak Unit V C C C
ELECTRICAL CHARACTERISTICS (Refer to the test circuit, -40C TC 125C, -40C TJ 150C, 7.0 V VIN 10 V, unless otherwise specified.)
Characteristic Output Voltage, VOUT Operating Input Voltage Load Regulation Dropout Voltage Quiescent Current PSRR Output Short Circuit Current Reset Output Voltage Reset Output Leakage Current Delay Time for Reset Output Reset Threshold, VRTH Reset Threshold, VRTL Threshold Hysteresis Delay, VDTC Delay, VDTD Delay Hysteresis, VDH Reset Delay Capacitor Charging Current, ICH Reset Delay Capacitor Discharge Voltage, VDIS Charge Discharge - - - Test Conditions VIN = 8.5 V, IOUT = 250 mA, TJ= 25C 100 mA IOUT 750 mA 100 to 750 mA 100 mA IOUT 750 mA, VIN = 8.5 V IOUT = 750 mA IOUT = 0 mA IOUT = 750 mA IOUT - 250 mA, f = 120 Hz COUT = 10 F, VIN = 8.5 V + Vpp - IR = 1.6 mA, 1.0 VOUT 4.75 V VOUT in regulation Cd = 100 nF VOUT Increasing VOUT Decreasing - Min 4.95 4.85 -0.75 - - - - - - - - 10 - 4.75 10 3.7 3.1 200 10 - Typ 5.00 5.00 - 30 1.4 3.0 5.0 70 1.0 0.08 0 20 - - 50 4.0 3.5 500 20 0.6 Max 5.05 5.15 18.0 100 1.8 4.0 25 - - 0.40 50 30 VOUT - 0.04 - - 4.4 3.9 1000 40 1.2 Unit V V V mV V mA mA dB A V A ms V V mV V V mV A V
PACKAGE PIN DESCRIPTION
PACKAGE LEAD # 5 Lead TO-220 1 2 3 4 5 LEAD SYMBOL VIN RESET GND Delay VOUT Input voltage. CMOS compatible output lead. RESET goes low whenever VOUT falls out of regulation. Ground connection. Timing capacitor for RESET function. Regulated output voltage, 5.0 V (typ). FUNCTION
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CS403
TYPICAL PERFORMANCE CHARACTERISTICS
5.5 4.5 3.5 VOUT 2.5 1.5
22 18 Supply Current (mA) 14 10 6.0
5.02 IOUT = 250 mA 5.01 5.00 VOUT (V) 4.99 4.98 4.97 4.96
VO IQ
0 0 2.0 4.0 VIN 6.0 8.0
0 10
4.95 -40
0
40 80 120 Junction Temperature (C), TJ
150
Figure 2. Output Voltage vs. VIN, IQ
1.2 1.0 Dropout Voltage (V) 0.8 0.6 0.4 0.2 0 TA = 40C TA = 25C
Figure 3. Output Voltage vs. Junction Temperature
0
100
200 300 400 Output Current (mA), IOUT
500
Figure 4. Dropout Voltage vs. Output Current Over Temperature
RESET CIRCUIT
VOUT
VRT(ON) VRT(OFF) VRH
RESET
(3) VRL
(1) (2)
TDelay
Delay
VDH VDTC VDTD (2) VDIS
(1) - No delay Capacitor. (2) - With Delay Capacitor (3) - Max. Reset Voltage (< 1.0 V)
Figure 5. Reset Circuit Waveform
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CS403
CIRCUIT DESCRIPTION The CS403 RESET function is very precise, has hysteresis on both the RESET and Delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1.0 V. The RESET circuit output is an open collector type with ON and OFF parameters as specified. The RESET output NPN transistor is controlled by the two circuits described (see Figure 1).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when output voltage is below the specified minimum, causes the RESET output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the RESET output transistor to go into the OFF state if allowed by the reset Delay circuit.
Reset Delay Circuit
Low Voltage Inhibit circuit indicates that output voltage is above VRT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the Delay capacitor). The discharge current is latched ON when the output voltage is below VRT(OFF), or when the voltage on the Delay capacitor is above VDIS. In other words, the Delay capacitor is fully discharged any time the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled RESET pulse is generated following detection of an error condition. The circuit allows the RESET output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than VDIS.
td + Cd VDTC ICH + CDelay 2.105 (typical).
This circuit provides a programmable (external capacitor) delay on the RESET output lead. The Delay lead provides source current to the external delay capacitor only when the
where: td = Time delay. Cd = Value of external charging capacitor (see Figure 6). VDTC = Delay Threshold charge. Ich = Reset delay capacitor charging current.
VIN
C1 * 100 nF
VOUT CS403
C2** COUT = 10 F to 100 F
Delay
100 nF Cd
RESET GND
C1* is required if the regulator is far from the power source filter. C2** is required for stability.
Figure 6. Test Circuit
APPLICATION NOTES
Stability Considerations
The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR, can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for the output capacitor COUT shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for COUT for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the
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CS403
higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
Calculating Power Dissipation in a Single Output Linear Regulator
VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current, for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated:
RQJA + 150C * TA PD
(2)
The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
IIN IOUT
Smart Regulator
Control Features
IQ
Figure 7. Single Output Regulator With Key Performance Parameters Labeled
Heat Sinks
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA.
RQJA + RQJC ) RQCS ) RQSA
(3)
The maximum power dissipation for a single output regulator (Figure 7) is:
PD(max) + VIN(max) * VOUT(min) IOUT(max) ) VIN(max)IQ
(1)
where: VIN(max) is the maximum input voltage,
where: RJC = the junction-to-case thermal resistance, RCS = the case-to-heatsink thermal resistance, and RSA = the heatsink-to-ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
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CS403
PACKAGE DIMENSIONS
TO-220 FIVE LEAD T SUFFIX CASE 314D-04 ISSUE E
-T- -Q- B C E
SEATING PLANE
U K
12345
A L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E G H J K L Q U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972
G D
5 PL
J H
M
0.356 (0.014)
M
TQ
TO-220 FIVE LEAD TVA SUFFIX CASE 314K-01 ISSUE O
-T- C -Q- B E
SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5 MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5
W A L
1 2 3 4 5
U
F K
M J
M
DIM A B C D E F G J K L M Q R S U W
D 0.356 (0.014)
M
5 PL
TQ
G R
S
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CS403
TO-220 FIVE LEAD THA SUFFIX CASE 314A-03 ISSUE E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827
-T- B -P-
OPTIONAL CHAMFER
SEATING PLANE
C E
Q
U
A L
F
K
G
5X
5X
J
D 0.014 (0.356)
M
S TP
M
DIM A B C D E F G J K L Q S U
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical TO-220 4.1 50 Unit C/W C/W
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CS403
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CS403/D

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