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Features
* Comprehensive Library of Standard Logic and I/O Cells * ATC18 Core and I/O Cells Designed to Operate with VDD = 1.8V 0.15V as Main Target
Operating Conditions
* IO25 and IO33 Pad Libraries Provide Interfaces to 2.5V and 3V Environments * Memory Cells Compiled to the Precise Requirements of the Design * Compatible with Atmel's Extensive Range of Microcontroller, DSP, Standard-interface
and Application-specific Cells
Description
The Atmel ATC18 CBIC family is fabricated on a proprietary 0.18 micron, up to sixlayer-metal CMOS process intended for use with a supply voltage of 1.8V 0.15V. The following table shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions
Symbol VDD VDD2.5 VDD3.3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Industrial Conditions Core and Standard I/Os 2.5V Interface I/Os 3V Interface I/Os Min 1.65 2.25 3 0 0 -40 Typ 1.8 2.5 3.3 Max 1.95 2.75 3.6 VDD VDD +85 Unit V V V V V C
Cell-based ASIC ATC18 Summary
The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: * MIN conditions: TJ = -40C VDD (cell) = 1.95V Process = fast (industrial best case) * TYP conditions: TJ = +25C VDD (cell) = 1.8V Process = typ (industrial typical case) * MAX conditions: TJ = +100C VDD (cell) = 1.60V Process = slow (industrial worst case) Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is V OL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database.
Rev. 1389AS-11/00
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Standard Cell Library SClib
The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic and storage cells. The SClib library includes cells which belong to the following categories: * Buffers and Gates * Multiplexers * Flip-flops * Scan Flip-flops Table 2. Cell Codes
Code AD AH AS AN AOI AON AOR BH BUFB BUFF BUFT CG CLK2 DE DF INV0 INVB Description Adder Half Adder Adder/Subtractor AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Bus Holder Balanced Buffer Non-Inverting Buffer Non-Inverting 3-State Buffer Carry Generator Clock Buffer D-Enabled Flip-Flop D Flip-Flop Inverter Balanced Inverter Code INVT JK LA MI MX ND NR OAI OAN OR ORA SD SE SRLA SU XN XR Description Inverting 3-State Buffer JK Flip-Flop D Latch Inverting Multiplexer Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-Flop Multiplexed Scan Enable D Flip-Flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate
* Latches * Adders and Subtractors
Decoding the Cell Name
Table 2 shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available.
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ATC18 Summary
ATC18 Summary
Cell Matrices
Table 3, Table 4 and Table 5 provide a quick reference to the storage elements in the SClib library. Note that all storTable 3. JK Flip-Flops
Macro Name JKBRBx Set * Clear * 1xDrive * 2xDrive *
age elements feature buffered clock inputs and buffered output.
Table 4. D Flip-Flops
Macro Name DFBRBx DFCRBx DFCRQx DFCRNx DFNRBx DFNRQx DFPRBx DEPRQx DENRQx DENRBx DECRQx * * * * * * * Set * Clear * * * * Enabled D Input 1xDrive * * * * * * * * * * * 2xDrive * * * * * * * * * * * * * * * * Single Output
Table 5. Scan Flip-flops
Macro Name SDBRBx SDCRBx SDCRNx SDCRQx SDNRBx SDNRNx SDNRQx SDPRBx SECRQx SENRQx SEPRQx * * * Set * Clear * * * * 1xDrive * * * * * * * * * * * 2xDrive * * * * * * * * * * * * * * * * * * Single Output
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Input/Output Pad Cell Libraries IO18lib, IO25lib and IO33lib
The Atmel Input/Output Cell Library, IO18lib, contains a comprehensive list of input, output, bidirectional and tristate cells. The ATC18 (1.8V) cell library includes two special sets of I/O cells, IO25lib and IO33lib, for interfacing with external 2.5V and 3.3V devices.
Power and Ground Pads
Designers are strongly encouraged to provide three kinds of power pairs for the IO18lib library. These are "AC", "DC" and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance.
Voltage Levels
The IO18lib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 1.65V to 1.95V. The library is compatible with the SClib 1.8-volt standard cells library.
Table 6. VSS Power Pad Combinations
Core Vssi * * * * * * * * * * Switching I/O VssAC Quiet I/O VssDC Library Cell Name pv18i18 pv18a18 pv18d18 pv18e18 pv18b18 pv18f18 Signal Name VDD VDD VDD VDD VDD VDD
Table 7. VDD Power Pad Combinations
Core Vssi Switching I/O VssAC * * * * * * * * * * Quiet I/O VssDC Library Cell Name pv18i18 pv18a18 pv18d18 pv18e18 pv18b18 pv18f18 Signal Name VDD VDD VDD VDD VDD VDD
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ATC18 Summary
ATC18 Summary
Cell Matrices
Table 8. CMOS Pads
CMOS Cell Name PC18B01 PC18B02 PC18B03 PC18B04 PC18B05 PC18O01 PC18O02 PC18O03 PC18O04 PC18O05 PC18T01 PC18T02 PC18T03 PC18T04 PC18T05 3-state I/O * * * * * * * * * * * * * * * Output Only 3-state Output Only Drive Strength 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x Pad Sites Used 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 9. TTL Pads
TTL Cell Name PT18B01 PT18B02 PT18B03 PT18O01 PT18O02 PT18O03 PT18T01 PT18T02 PT18T03 3-state I/O * * * * * * * * * Output Only 3-state Output Only Drive Strength 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA Pad Sites Used 1 1 1 1 1 1 1 1 1
Table 10. CMOS/TTL Input Only Pad
CMOS Cell Name PC18D01 PC18D11 PC18D21 Input Levels CMOS CMOS CMOS * * Schmitt Input Level Shifter Non-inverting * * Inverting Pad Sites Used 1 1 1 1
PC18D31 CMOS * * Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device.
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IO25lib and IO33lib Low Slew Rate Cells
The IO25lib (IO33lib) cells comprise a series of 1.8V/2.5V (1.8V/3.3V) input/output pads developed for low supply voltage processes in order to interface 1.8V ASICs to 2.5V (3.3V) environments. Table 11. IO25lib/IO33lib Pads
3V Interface Pad Name pc25b0x/pc33b0x pc25d00/pc33d00 pc25o0x/pc33o0x * 3-state I/O * * 2 mA, 4 mA, 8 mA, 16 mA Output Only 3-state Output Only Input Only Drive Strength 2 mA, 4 mA, 8 mA, 16 mA Pad Sites Used 1 1 1 1
All IO25lib (IO33lib) cells are slew rate controlled. Advantage has been taken of the 1.8V to 2.5V (3.3V) level shifter (slow by construction) to reduce the slew rate without reducing speed.
pc25t0x/pc33t0x * 2 mA, 4 mA, 8 mA, 16 mA Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down devices.
Table 12. IO25lib/IO33lib Power Pads
Power Bus Connection Cell Name pv25e00/pv33e00 pv25i00/pv33i00 pv25i25/pv33i25 pv25e33/pv33e33 pv25ecrn/pv33ecrn * * * * * vssi mixvssi * vddi mixvdd Pad Sites Used 1 1 1 1 2
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ATC18 Summary
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1389AS-11/00/0M
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