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ADS930
ADS 930 E
SBAS059A - MARCH 2001
8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
q q q q q q q +3V TO +5V SUPPLY OPERATION INTERNAL REFERENCE SINGLE-ENDED INPUT RANGE: 1V to 2V LOW POWER: 66mW at +3V HIGH SNR: 46dB LOW DNL: 0.4LSB SSOP-28 PACKAGE
DESCRIPTION
The ADS930 is a high speed pipelined Analog-to-Digital Converter (ADC) specified to operate from nominal +3V or +5V power supplies with tolerances of up to 10%. This complete converter includes a high bandwidth track/hold, a 8-bit quantizer and an internal reference. The ADS930 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance ADC is specified for performance at a 30MHz sampling rate. The ADS930 is available in a SSOP-28 package.
APPLICATIONS
q q q q q BATTERY POWERED EQUIPMENT CAMCORDERS PORTABLE TEST EQUIPMENT COMPUTER SCANNERS COMMUNICATIONS
CLK ADS930 Timing Circuitry
LVDD
2V IN 1V IN (Opt.) T/H Pipeline A/D Error Correction 3-State Outputs 8-Bit Digital Data
Internal Reference
LpBy CM LnBy
1VREF
Pwrdn
OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2001, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
+VS ....................................................................................................... +6V Analog Input ............................................................................... +VS +0.3V Logic Input ................................................................................. +VS +0.3V Case Temperature ......................................................................... +100C Junction Temperature .................................................................... +150C Storage Temperature ..................................................................... +150C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 324 SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING ADS930E ADS930E ORDERING NUMBER(1) ADS930E ADS930E/1K TRANSPORT MEDIA Rails Tape and Reel
PRODUCT ADS930E
PACKAGE SSOP-28
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of "ADS930E/1K" will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
At TA = +25C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified. ADS930E PARAMETER RESOLUTION Specified Temperature Range ANALOG INPUT Differential Full Scale Input Range Single-Ended Full Scale Input Range Common-mode Voltage Analog Input Bias Current Input Impedance DIGITAL INPUTS Logic Family High Input Voltage, VIH Low Input Voltage, VIL High Input Current, IIH Low Input Current, IIL Input Capacitance CONVERSION CHARACTERISTICS Start Conversion Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error f = 500kHz f = 12MHz No Missing Codes Integral Nonlinearity Error, f = 500kHz Spurious Free Dynamic Range(1) f = 500kHz (-1dBFS input) f = 12MHz (-1dB input) Two-Tone Intermodulation Distortion(3) f = 3.4MHz and 3.5MHz (-7dBFS each tone) Signal-to-Noise Ratio (SNR) f = 500kHz (-1dBFS input) f = 12MHz (-1dBFS input) Signal-to-(Noise + Distortion) (SINAD) f = 500kHz (-1dBFS input) f = 3.58MHz (-1dBFS input) f = 12MHz (-1dBFS input) CONDITIONS TEMP MIN TYP 8 Ambient Air 0.5Vp-p 1Vp-p -40 +1.25 +1.0 1.5 1 1.25 || 5 Full TTL/HCT Compatible CMOS 2.0 VDD 0.8 10 10 5 Rising Edge of Convert Clock 10k 30M 5 V V A A pF +85 +1.75 +2.0 MAX UNITS Bits C V V V A M || pF
Full
Samples/s Clk Cyc
Largest Code Error Largest Code Error
Full Full Full Full Full Full
0.4 0.4 Guaranteed 1.0 51 50 54
1
LSB LSB LSB dBFS(2) dBFS dBc dB dB dB dB dB
2.5
46
Full Full Full Full Full
44
46 46 45 45 45
42
2
ADS930
SBAS059A
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified. ADS930E PARAMETER Differential Gain Error Differential Phase Error Output Noise Aperture Delay Time Aperture Jitter Analog Input Bandwidth Small Signal Full Power Overvoltage Recovery Time(4) DIGITAL OUTPUTS Logic Family Logic Coding High Output Voltage, VOH Low Output Voltage, VOL 3-State Enable Time 3-State Disable Time Internal Pull-Down Power-Down Enable Time Power-Down Disable Time Internal Pull-Down ACCURACY Gain Error Input Offset Power Supply Rejection (Gain) Power Supply Rejection (Offset) Internal Positive Reference Voltage Internal Negative Reference Voltage POWER SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation Power Dissipation (Power Down) Thermal Resistance, JA SSOP-28 CONDITIONS NTSC, PAL NTSC, PAL Input Grounded TEMP MIN TYP 2.3 1 0.2 2 7 350 100 2 TTL/HCT Compatible CMOS Straight Offset Binary +2.4 LVDD 0.4 20 40 2 10 50 133 18 50 Full Full Full Full Full Full Full Full Full Full Full Full +2.7 5.9 10 56 56 +1.75 +1.25 +3.0 22 66 168 10 15 89 10 60 MAX UNITS % degrees LSBs rms ns ps rms MHz MHz ns
-20dBFS Input 0dBFS Input CL = 15pF
OE = L OE = H PwrDn = L PwrDn = H fS = 2.5MHz Referred to Ideal Midscale VS = +10%
V V ns ns k ns ns k %FS mV dB dB V V V mA mW mW mW mW C/W
Operating Operating, +3V Operating, +3V Operating, +5V Operating, +3V Operating, +5V
+5.25 84
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No "Rollover" of bits.
ADS930
SBAS059A
3
PIN CONFIGURATION
Top View SSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESIGNATOR +VS LVDD NC NC Bit 8 (LSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(MSB) GND GND CLK OE Pwrdn +VS GND GND LpBy NC 1VREF IN LnBy CM +IN +VS DESCRIPTION Analog Supply Output Logic Driver Supply Voltage No Connection No Connection Data Bit 8 (D7) Data Bit 7 (D6) Data Bit 6 (D5) Data Bit 5 (D4) Data Bit 4 (D3) Data Bit 3 (D2) Data Bit 2 (D1) Data Bit 1 (D0) Analog Ground Analog Ground Convert Clock Input Output Enable, Active Low Power Down Pin Analog Supply Analog Ground Analog Ground Positive Ladder Bypass No Connection 1V Reference Output Complementary Input Negative Ladder Bypass Common-Mode Voltage Output Analog Input Analog Supply
+VS LVDD NC NC LSB Bit 8 Bit 7 Bit 6 Bit 5 Bit 4
1 2 3 4 5 6 7 ADS930 8 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
+VS +IN CM LnBy IN 1VREF NC LpBy GND GND +VS Pwrdn OE CLK
Bit 3 10 Bit 2 11 MSB Bit 1 12 GND 13 GND 14
TIMING DIAGRAM
N+1 Analog In N tD Clock tCONV
N+2 N+3
N+4 N+5 tL tH N+6
N+7
5 Clock Cycles t2 Data Out N-5 N-4 N-3 N-2 N-1 N t1 N+1 N+2
Data Invalid
SYMBOL tCONV tL tH tD t1 t2
DESCRIPTION Convert Clock Period Clock Pulse Low Clock Pulse High Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max
MIN 33 15.5 15.5 3.9
TYP
MAX 100s
UNITS ns ns ns ns ns ns
16.5 16.5 2 12
4
ADS930
SBAS059A
TYPICAL CHARACTERISTICS
At TA = +25C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SPECTRAL PERFORMANCE 0 fIN = 500kHz -20
Amplitude (dB) Amplitude (dB)
SPECTRAL PERFORMANCE 0 fIN = 3.58MHz -20
-40
-40
-60
-60
-80
-80
-100 0 5 10 Frequency (MHz) 15
-100 0 5 10 Frequency (MHz) 15
SPECTRAL PERFORMANCE 0 fIN = 12MHz -20 -20 0
TWO-TONE INTERMODULATION f1 = 3.5MHz at -7dBFS f2 = 3.4MHz at -7dBFS 2f1 -f2 = 54.7dBFS 2f2 -f1 = 54.2dBFS
-40
Magnitude (dBFS)
0 5 10 Frequency (MHz) 15
Amplitude (dB)
-40
-60
-60
-80
-80
-100
-100 0 2 4 6 8 10 Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 500kHz 1.0 1.0
DLE (LSB)
DIFFERENTIAL LINEARITY ERROR 2.0 fIN = 12MHz
DLE (LSB)
0.0
0.0
-1.0
-1.0
-2.0 0 64 128 Output Code 192 256
-2.0 0 64 128 Output Code 192 256
ADS930
SBAS059A
5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
INTEGRAL LINEARITY ERROR 4.0 fIN = 500kHz 2.0
ILE (LSB)
SWEPT POWER SFDR 100 dBFS 80
SFDR (dBFS, dBc)
60
0
40
-2.0
20 dBc
-4.0 0 64 128 Output Code 192 256
0 -50 -40 -30 -20 -10 0 Input Amplitude (dBFS)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY 52 0 -20
UNDERSAMPLING (With Differential Input) fIN = 20MHz fS = 16MHz
SFDR
SFDR, SNR (dB)
Amplitude (dB)
SNR
50
-40 -60 -80 -100
48
46 0.1 1 10 Frequency (MHz) 100
-120 0 1.6 3.2 4.8 6.4 8.0 Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.7
SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE 54 fIN = 500kHz
0.6
52
0.5 SFDR (dBFS) DLE (LSB)
50 fIN = 12MHz 48
0.4
0.3 fIN = 500kHz fIN = 10MHz 0.2 -50 -25 0 25 50 75 100 Temperature (C)
46 -50 -25 0 25 50 75 100 Temperature (C)
6
ADS930
SBAS059A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SIGNAL-TO-NOISE RATIO vs TEMPERATURE 48 69
POWER DISSIPATION vs TEMPERATURE
Power Dissipation (mW)
47
SNR (dB)
fIN = 12MHz
68
46 fIN = 500kHz 45
67
66
44 -50
65 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (C) Temperature (C)
GAIN ERROR vs TEMPERATURE 6.5 7
OFFSET ERROR vs TEMPERATURE
6.0
Offset Error (mV)
Gain (%FSR)
6
5.5
5
5.0
4
4.5 -50 -25 0 25 50 75 100 Temperature (C)
3 -50 -25 0 25 50 75 100 Temperature (C)
OUTPUT NOISE HISTOGRAM (DC Input) 12 10
Counts (x 105)
8 6 4 2 0 N-2
N-1
N Output Code
N+1
N+2
ADS930
SBAS059A
7
THEORY OF OPERATION
The ADS930 is a high speed sampling ADC that utilizes a pipeline architecture. The fully differential topology and digital error correction guarantee 8-bit resolution. The track/ hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, 1 and 2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors. In the next clock phase, 2, the bottom plates of the input capacitors are connected together and the feedback capacitors are switched to the op amp output. At this time the charge redistributes between CI and CH, completing one track/hold cycle. The differential output is a held DC representation of the analog input at the sample time. In the normal mode of operation, the complementary input is tied to the common-mode voltage. In this case, the track/hold circuit converts a single-ended input signal into a fully differential signal for the quantizer. Consequently, the input signal gets amplified by a gain or two, which improves the signal-to-noise performance. Other parameters such as smallsignal and full-power bandwidth, and wideband noise are also defined in this stage.
Op Amp Bias 1
VCM 1 CH 2
CI IN IN (Opt.) 1 1 2 CI CH 1 Input Clock (50%) Op Amp Bias Internal Non-overlapping Clock 1 2 1 VCM 1 1
OUT OUT
2
FIGURE 1. Input Track/Hold Configuration with Timing Signals.
IN IN
(Opt.)
Input T/H 2-Bit Flash STAGE 1 2-Bit DAC
Digital Delay
x2
+
-
Digital Delay
2-Bit Flash STAGE 2
2-Bit DAC B1 (MSB)
x2
+
Digital Error Correction
-
B2 B3 B4 B5 B6 B7 B8 (LSB)
Digital Delay
2-Bit Flash STAGE 6
2-Bit DAC
x2
+
-
STAGE 7
2-Bit Flash
Digital Delay
FIGURE 2. Pipeline ADC Architecture. 8
ADS930
SBAS059A
The pipelined quantizer architecture has 7 stages with each stage containing a two-bit quantizer and a two bit Digitalto-Analog Converter (DAC), as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the subclock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the subsequent quantizer stages. This aligned data is fed into a digital error correction circuit which can adjust the output data based on the information found on the redundant bits. This technique provides the ADS930 with excellent differential linearity and guarantees no missing codes at the 8-bit level. The ADS930 includes an internal reference circuit that provides the bias voltages for the internal stages (for details see "Internal Reference"). A midpoint voltage is established by the built-in resistor ladder which is made available at pin 26 "CM". This voltage can be used to bias the inputs up to the recommended common-mode voltage or to level shift the input driving circuitry. The ADS930 can be used in both a single-ended or differential input configuration. When operated in single-ended mode, the reference midpoint (pin 26) should be tied to the inverting input, pin 24. To accommodate a bipolar signal swing, the ADS930 operates with a common-mode voltage (VCM) which is derived from the internal references. Due to the symmetric resistor ladder inside the ADS930, VCM is situated between the top and bottom reference voltage. The following equation can be used for calculating the common-mode voltage level: VCM = (REFT +REFB)/2 (1)
signal. The capacitor C1 and resistor R1 form a high-pass filter with the -3dB frequency set at f-3dB = 1/(2 R1 C1) (2)
The values for C1 and R1 are not critical in most applications and can be set freely. The values shown in Figure 3 correspond to a corner frequency of 1.6kHz. Figure 4 depicts a circuit that can be used in single-supply applications. The mid-reference biases the op amp up to the appropriate common-mode voltage, for example VCM = +1.5V. With the use of capacitor CG, the DC gain for the non-inverting op amp input is set to +1V/V. As a result, the transfer function is modified to VOUT = VIN {(1 + RF/RG) + VCM} (3)
Again, the input coupling capacitor C1 and resistor R1 form a high-pass filter. At the same time, the input impedance is defined by R1. Resistor RS isolates the op amp's output from the capacitive load to avoid gain peaking or even oscillation. It can also be used to establish a defined bandwidth to reduce the wideband noise. Its value is usually between 10 and 100.
+3V +5V VIN C1 10 0.1F IN IN -5V R1 1k VCM 402 ADS930 CM
OPA650 OPA658
APPLICATIONS
DRIVING THE ANALOG INPUTS Figure 3 shows an example of an ac-coupled, single-ended interface circuit using high-speed op amps which operate on dual supplies (OPA650, OPA658). The mid-point reference voltage, (VCM), biases the bipolar, ground-referenced input
402 0.1F
FIGURE 3. AC-Coupled Driver.
C1 0.1F VIN
+5V RS 50 OPA680 R1 1k 22pF VCM RF 402 RG 402 CG 0.1F IN IN
+3V
ADS930 CM
0.1F
RP 402
FIGURE 4. Interface Circuit Example Using the Voltage Feedback Amplifier OPA680.
ADS930
SBAS059A
9
DC-COUPLED INTERFACE CIRCUIT Figure 5 illustrates an example of a DC-coupled interface circuit using one high-speed op amp to level-shift the groundreferenced input signal. This serves to condition it for the input requirements of the ADS930. With a +3V supply the input signal swings 1Vp-p centered around a typical common-mode voltage of +1.5V. This voltage can be derived from the internal bottom reference (REFB) and then fed back through a resistor divider (R1, R2) to level-shift the driving op amp (A1). A capacitor across R2 will shunt most of the wideband noise to ground. Depending on the configured gain, the values of resistors R1 and R2 must be adjusted since the offsetting voltage (VOS) is amplified by the noninverting gain, 1 + (RF / RIN). This example assumes the sum of R1 and R2 to be 5k, drawing only 250A from the bottom reference. Considerations for the selection of a proper op amp should include its output swing, input common-mode range, and bias current. This circuit can easily be modified for a +5V operation of the ADC, requiring a higher common-mode level (+2.5V). INTERNAL REFERENCE The ADS930 features an internal reference that provides fixed reference voltages for the internal stages. As shown in
Figure 6, each end of the resistor ladder (REFT and REFB) are driven by a buffer amplifier. The ladder has a nominal resistance of 4k (15%). The two outputs of the buffers are brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily to connect external bypass capacitors, typically 0.1F. They will shunt the high frequency switching noise that is fed back into the reference circuit and improve the performance. The buffers can drive limited external loads, for example level-shifting of the converter's interface circuit. However, the current draw should be limited to approximately 1mA. Derived from the top reference of +1.75V is an additional voltage of +1.0V. Note that this voltage, available on pin 23, is not buffered and care should be taken when external loads are applied. In normal operation, this pin is left unconnected and no bypassing components are required. CLOCK INPUT The clock input of the ADS930 is designed to accommodate either +5V or +3V CMOS logic levels. To drive the clock input with a minimum amount of duty cycle variation and support the maximum sampling rate (30MSPS), high speed or advanced CMOS logic should be used (HC/HCT, AC/ACT). When digitizing at high sampling rates, a 50% duty cycle, along with fast rise and fall times (2ns or less),
+5V RF RIN VIN OPA680 22pF VOS 0.1F 0.1F R2 R1 I = 250A 0.1F RS IN IN CM VCM = 1.5V ADS930 REFB +1.25V +3V
FIGURE 5. Single-supply, DC-coupled Interface Circuit.
ADS930 +1.75V
REFT
21 0.1F 2k 2.1k 23 2.8k 2k
LpBy
CM 0.1F
26
+1VREF
+1.25V
REFB
25 0.1F
LnBy
FIGURE 6. Internal Reference Structure and Recommended Reference Bypassing.
10
ADS930
SBAS059A
are recommended to meet the rated performance specifications. However, the ADS930 performance is tolerant to duty cycle variations of as much as 10%, which should not affect the performance. For applications operating with input frequencies up to Nyquist (fCLK/2) or undersampling applications, special considerations must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limitation in achieving good SNR performance. The following equation shows the relationship between aperture jitter, input frequency and the signal-to-noise ratio: SNR = 20log10 [1/(2 fIN tA)]
STRAIGHT OFFSET BINARY (SOB) PIN 12 FLOATING or LO 11111111 11111111 11111110 11100000 11000000 10100000 10000001 10000000 01111111 01100000 01000000 00100000 00000001 00000000
LVDD, the digital output levels will vary respectively. It is recommended to limit the fan-out to one in order to keep the capacitive loading on the data lines below the specified 15pF. If necessary, external buffers or latches may be used to provide the added benefit of isolating the ADC from any digital activities on the bus coupling back high frequency noise which degrades the performance. POWER-DOWN MODE The ADS930's low power consumption can be reduced even further by initiating a power-down mode. For this, the Power Down Pin (Pin 17) must be tied to a logic "High" reducing the current drawn from the supply by approximately 70%. In normal operation, the power-down mode is disabled by an internal pull-down resistor (50k). During power-down, the digital outputs are set in 3-state. With the clock applied, the converter does not accurately process the sampled signal. After removing the power-down condition, the output data from the following 5 clock cycles is invalid (data latency). DECOUPLING AND GROUNDING CONSIDERATIONS The ADS930 has several supply pins, one of which is dedicated to supply only the output driver (LVDD). The remaining supply pins are not divided into analog and digital supply pins since they are internally connected on the chip. For this reason, it is recommended that the converter be treated as an analog component and to power it from the analog supply only. Digital supply lines often carry high levels of noise which can couple back into the converter and limit performance. Because of the pipeline architecture, the converter also generates high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed. Figure 8 shows the recommended decoupling scheme for the analog supplies. In most cases 0.1F ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close as possible to the supply pins.
(4)
SINGLE-ENDED INPUT (IN = 1.5V DC) +FS (IN = +2V) +FS -1LSB +FS -2LSB +3/4 Full Scale +1/2 Full Scale +1/4 Full Scale +1LSB Bipolar Zero (IN +1.5V) -1LSB -1/4 Full Scale -1/2 Full Scale -3/4 Full Scale -FS +1LSB -FS (IN = +1V)
TABLE I. Coding Table for the ADS930.
DIGITAL OUTPUTS There is a 5.0 clock cycle data latency from the start convert signal to the valid output data. The standard output coding is Straight Offset Binary where a full scale input signal corresponds to all "1's" at the output. The digital outputs of the ADS930 can be set to a high impedance state by driving the OE (pin 16) with a logic "HI". Normal operation is achieved with pin 16 "LO" or Floating due to internal pulldown resistors. This function is provided for testability purposes but is not recommended to be used dynamically. The digital outputs of the ADS930 are standard CMOS stages and designed to be compatible to both high speed TTL and CMOS logic families. The logic thresholds are for low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows the ADS930 to directly interface to 3V-logic. The digital output driver of the ADS930 uses a dedicated digital supply pin (pin 2, LVDD) see Figure 7. By adjusting the voltage on
+VS +LVDD
ADS930 VS 1 GND 13 14 VS 18 GND 19 20 VS 28
0.1F
0.1F
0.1F
ADS930
Digital Output Stage
FIGURE 8. Recommended Bypassing for Analog Supply Pins.
FIGURE 7. Independent Supply Connection for Output Stage.
ADS930
SBAS059A
11
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Copyright (c) 2001, Texas Instruments Incorporated

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