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ADS8342
SBAS277 - MAY 2003
16 Bit, 250kSPS, 4 Channel, Parallel Output ANALOG TO DIGITAL CONVERTER
FEATURES D True Bipolar Input D Input Signal Range: 2.5V D 4-Channel Input Multiplexer D Up to 250kSPS Sampling Rate D Selectable 8-Bit or 16-Bit Parallel Interface D 16-Bit Ensured No Missing Codes D Offset: 1mV max D Low Power: 200mW D TQFP-48 Package D Operating Temperature Range: -40C to +85C APPLICATIONS D Data Acquisition D Test and Measurement D Industrial Process Control D Medical Instruments D Laboratory Equipment DESCRIPTION
The ADS8342 is a 4-channel, 16-bit analog-to-digital converter (ADC). It contains a 16-bit succesive approximation register (SAR), a capacitor-based ADC with an inherent sample-and-hold circuit, an interface for microprocessor use, and parallel 3-state output drivers. The ADS8342 is specified at a 250kHz sampling rate while dissipating only 200mW of power using a 5V power supply. The ADS8342 is available in a TQFP-48 package and is ensured over the -40C to +85C temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
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ADS8342
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) NO MISSING CODES (Bits) PACKAGE- LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE ORDERING NUMBER TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2000 Tape and Reel, 250 Tape and Reel, 2000
ADS8342IPFBT ADS8342 6 15 TQFP-48 TQFP 48 PFB -40C to +85C 40C t 85C ADS8342IPFBR ADS8342IBPFBT ADS8342 4 16 TQFP-48 TQFP 48 PFB -40C t +85C 40C to 85C ADS8342IBPFBR (1) For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) ADS8342I Supply voltage, +AVDD to AGND and +DVDD to DGND Supply voltage, -AVDD to AGND and -DVDD to DGND Supply voltage, BVDD to BGND Analog input voltage to AGND Reference voltage, REFIN to AGND Common voltage to AGND Digital input voltage to BGND Ground voltage differences, AGND to REFGND or BGND or DGND Voltage differences, BVDD or +DVDD to AGND Voltage differences, +DVDD to +AVDD and -DVDD to -AVDD Voltage differences, BVDD to DVDD Input current to any pin except supply Power dissipation Operating virtual junction temperature range, TJ Operating free-air temperature range, TA Storage temperature range, TSTG -0.3 to 6 -6 to 0.3 -0.3 to 6 -AVDD - 0.3 to +AVDD + 0.3 -0.3 to +AVDD + 0.3 -0.3 to +0.3 BGND - 0.3 to BVDD + 0.3 -0.3 to 0.3 -0.3 to 6 -0.3 to 0.3 -(+DVDD) to 0.3 -20 to 20 see Package Dissipation Ratings table -40 to +150 -40 to +85 -65 to +150 C C C UNIT V V V V V V V V V V V mA
Lead temperature 1.6mm (1/16 inch) from case for 10 seconds +300 C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
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PACKAGE DISSIPATION RATINGS
BOARD Low K PACKAGE PFB RJC (C/W) 19.6 RJA (C/W) 97.5 DERATING FACTOR ABOVE TA +25C (mW/C) 10.256 TA +25C POWER RATING (mW) 1282 TA +70C POWER RATING (mW) 820 TA = +85C POWER RATING (mW) 666
High K PFB 19.6 63.7 15.698 1962 1255 1020 (1) The JEDEC Low K(1s) board design used to derive this data was a 3 inch x 3 inch, 2-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC High K(2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board.
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, +AVDD to AGND Supply voltage, -AVDD to AGND Low-voltage levels Supply voltage, BVDD to BGND voltage Supply voltage, +DVDD to DGND Supply voltage, -DVDD to DGND Reference input voltage Analog input voltage Common voltage Ground differences, AGND to REFGND or BGND or DGND Voltage differences, +DVDD to +AVDD and -DVDD to -AVDD 5V logic levels 4.75 -5.25 2.7 4.5 4.75 -5.25 2.0 -REFIN -0.3 -0.01 -0.01 0 0 0 5 -5 2.5 NOM 5 -5 MAX 5.25 -4.75 3.6 +DVDD 5.25 -4.75 2.55 +REFIN +0.3 0.01 0.01 UNIT V V V V V V V V V V V
EQUIVALENT INPUT CIRCUIT
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at -40C to +85C, AVDD = DVDD = 5V, BVDD = +5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. ADS8342I ADS8342IB PARAMETER TEST CONDITIONS UNIT MIN TYP(1) MAX MIN TYP(1) MAX Analog Input Full-scale range (FSR) Input MUX on-resistance Input capacitance Input leakage current Full power bandwidth Voltage Accuracy Resolution No missing code (NMC) Integral linearity error (INL) Differential nonlinearity (DNL) Bipolar zero (offset) error (VOS) Bipolar zero (offset) error drift (TCVOS) Bipolar zero (offset) error match Positive gain error (PGERR) Positive gain error drift (TCPGERR) Positive gain error match Negative gain error (NGERR) Negative gain error drift (TCNGERR) Negative gain error match Sampling Dynamics Conversion time (tCONV) Acquisition time (tACQ) Throughput rate Multiplexer settling time Aperture delay Aperture jitter AC Accuracy Total haromonic distortion (THD) Spurious-free dynamic range (SFDR) Signal-to-noise ratio (SNR) Signal-to-noise + distortion (SINAD) Channel-to-channel isolation(2) Effective number of bits (ENOB) Indicates the same specifications as the ADS8342I. (1) All typical values are at TA = +25C. (2) Ensured by design. (3) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (4) Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
:
AIN to Common Common = AGND Common = AGND Common = AGND FS sinewave, -3dB
-VREF 500 20 0.3 16 16 15 -6 -2 3 1 1 0.150 -0.25 1.5 0.003 -0.25 1.5 0.003 3.4 0.6
+VREF
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:
V pF A MHz Bits Bits
:
16 +6 +2 +2 1 +0.25 0.01 +0.25 0.01 34 250 150 8 50
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-4 -1 -1
2 0.6
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+4 +1.5 +1
: :
LSB LSB mV ppm/C mV % FSR ppm/C % FSR % FSR ppm/C % FSR s s kHz ns ns ps dB dB dB dB dB Bits
AIN = Common = 0V AIN = Common = 0V AIN = Common = 0V AIN = VREF, Common = 0V AIN = VREF, Common = 0V AIN = VREF, Common = 0V AIN = -VREF, Common = 0V AIN = -VREF, Common = 0V AIN = -VREF, Common = 0V 500kHz fCLK 5MHz fCLK = 5MHz
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: :
VIN = 2.5Vp-p at 10kHz VIN = 2.5Vp-p at 10kHz VIN = 2.5Vp-p at 10kHz VIN = 2.5Vp-p at 10kHz VIN = 2.5Vp-p at 50kHz 95
-89 92 86 84.6
:
: : : :
14
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at -40C to +85C, AVDD = DVDD = 5V, BVDD = +5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. ADS8342I ADS8342IB PARAMETER TEST CONDITIONS UNIT MIN TYP(1) MAX MIN TYP(1) MAX Voltage Reference Input Reference voltage Reference input resistance Reference input capacitance Reference input current 5V Digital Inputs(3) Logic family High-level input voltage (VIH) Low-level input voltage (VIL) Input leakage current (IIN) Input capacitance (CI) 5V Digital Outputs(3) Logic family High-level output voltage (VOH) Low-level output voltage (VOL) High-impeadance-state output current (IOZ) Output capacitance (CO) Load capacitance (CL) Data format 3V Digital Inputs(4) Logic family High-level input voltage (VIH) Low-level input voltage (VIL) Input leakage current (IIN) Input capacitance (CI) 3V Digital Outputs(4) Logic family High-level output voltage (VOH) Low-level output voltage (VOL) High-impeadance-state output current (IOZ) Output capacitance (CO) Load capacitance (CL) Data format
:
2.0
2.5 100 5 25 CMOS
2.55
:
: : : :
:
V M pF nA
0.7 x BVDD
BVDD + 0.3 0.3 x BVDD
V V nA pF
-0.3 VI = BVDD or GND 50 5 CMOS IOH = -100A IOL = +100A CS = BVDD, VO = BVDD or GND 4.4
V 0.5 50 5 20 V nA pF pF
Binary Two's Complement LVCMOS BVDD = 3.6V BVDD = 2.7V VI = BVDD or GND 2 -0.3 50 5 LVCMOS BVDD = 2.7V, IOH = -100A BVDD = 2.7V, IOL = +100A CS = BVDD, VO = BVDD or GND
BVDD - 0.3 BVDD + 0.3
V V nA pF
0.8
V 0.2 50 5 20 V nA pF pF
Binary Two's Complement
Indicates the same specifications as the ADS8342I. (1) All typical values are at TA = +25C. (2) Ensured by design. (3) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (4) Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at -40C to +85C, AVDD = DVDD = 5V, BVDD = +5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. ADS8342I ADS8342IB PARAMETER TEST CONDITIONS UNIT MIN TYP(1) MAX MIN TYP(1) MAX Power-Supply Requirements Negative analog power supply (-AVDD) Positive analog power supply (+AVDD) Negative digital power supply (-DVDD) Positive digital power supply (+DVDD) Low-voltage levels I/O buffer power supply (BVDD) Negative analog operating supply current (-AIDD) Positive analog operating supply current (+AIDD) Negative digital operating supply current (-DIDD) Positive digital operating supply current (+DIDD) I/O buffer operating supply current o erating su ly (BIDD) Power Dissipation
:
-5.25 4.75 -5.25 4.75 2.7 4.5 11.5 14 8.3 7.1 BVDD = 3V BVDD = 5V BVDD = 3V 0.65 1 208 5V logic levels
-4.75 5.25 -4.75 5.25 3.6 +DVDD 13.8 16.8 9.9 8.5 0.81 1.25 250
: : : : : : :
: : : : : : :
V V V V V V mA mA mA mA mA mA mW
:
:
:
:
: : : :
: : : :
Indicates the same specifications as the ADS8342I. (1) All typical values are at TA = +25C. (2) Ensured by design. (3) Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (4) Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
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APPLICATION BLOCK DIAGRAM
Figure 1. ADS8342 Typical Connection Diagram
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TQFP PACKAGE (TOP VIEW)
PIN ASSIGNMENTS--NUMERICAL LISTING
PIN NO.
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PIN NAME NC(1) NC(1) CLKDIV0 CLKDIV1 A0 A1 BYTE CONV RD CS CLK +DVDD DGND -DVDD BUSY DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7
PIN NO. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
PIN NAME BGND DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 (MSB) NC(1) NC(1) AGND -AVDD AGND +AVDD NC(1) REFIN REFGND NC(1) COMMON AIN0 AIN1 AIN2 AIN3
BVDD (1) NC = no connection. These pins should be left unconnected. 8
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Terminal Functions
TERMINAL NAME NO. Analog Input Signals AIN0 AIN1 AIN2 AIN3 COMMON REFIN REFGND 45 46 47 48 44 41 42 AI AI AI AI AI AI AI Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input common signal Reference voltage input pin for external reference voltage. Decouple to reference ground with a 0.1F ceramic capacitor. Reference ground. Connected to the ground of the external reference voltage. TYPE(1) DESCRIPTION
Digital Interface Signals A(x) DB(x) CS RD CLK CLKDIV(x) CONV 5, 6 16-23, 26-33 10 9 11 3, 4 8 DI DO DI DI DI DI DI Address decode input, select analog input. Output 3-state data bus. DB15 (MSB) to DB0 (LSB). Data lines are 3-state during conversion. RD should be asserted only when the part is not converting. Active low chip select signal Active low read signal System clock Select clock divider ratio. Internally divides external clock (pin 11) by 1, 2, 4, or 8. Convert start. When CONV switches from high to low, the device switches from sample mode to hold mode, independent of the external clock status. The address for the next conversion will be latched on low-to-high transition. BUSY goes high during a conversion and returns low at the end when data is available for reading. Active high bus width is 8 bits. When BYTE is low, the bus width is 16 bits.
BUSY BYTE Power Supply +AVDD -AVDD BVDD +DVDD -DVDD AGND BGND DGND
15 7
DO DI
39 37 24 12 14 36, 38 25 13
P P P P P P P P
Positive analog power supply, +5VDC. Decouple to analog ground with a 0.1F ceramic capacitor and a 4.7F tantalum capacitor. Referenced to the same power supply as +DVDD (pin 12). Negative analog power supply -5VDC. Decouple to analog ground with a 0.1F ceramic capacitor and a 4.7F tantalum capacitor. Referenced to the same power supply as -DVDD (pin 14). Digital I/O power supply in the range 2.7V to DVDD. Decouple to digital I/O ground with a 0.1F ceramic capacitor and a 4.7F tantalum capacitor. Positive digital power supply +5VDC. Decouple to digital ground with a 0.1F ceramic capacitor and a 4.7F tantalum capacitor. Referenced to the same power supply as +AVDD (pin 39). Negative digital power supply -5VDC. Decouple to digital ground with a 0.1F ceramic capacitor and a 4.7F tantalum capacitor. Referenced to the same power supply as -AVDD (pin 37). Analog ground. Connected directly to digital ground (pin 13) and digital I/O ground (pin 25). Digital I/O ground. Connected directly to analog ground (pins 36 and 38) and digital ground (pin 13). Digital ground. Connected directly to analog ground (pins 36 and 38) and digital I/O ground (pin 25).
(1) AI is analog input, AO is analog output, DI is digital input, DO is digital output, and P is power-supply connection.
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Figure 2. Timing Diagram
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TIMING REQUIREMENTS(1)(2)
Over recommended operating free-air temperature range at -40C to +85C, and BVDD = +5V, unless otherwise noted. ADS8342I PARAMETER Conversion time Acquisition time CLK period CLK high time (for 5MHz clock frequency) CLK low time (for 5MHz clock frequency) CONV low to CLK high CONV low time CS low to CONV low CONV low to BUSY high CONV and CS high to 2nd CLK high(3) 18 CLK high to BUSY low 18 CLK low to CS low CS low to RD low CS high time RD low time RD low to data valid RD high to CS high Data hold from RD high RD high to CONV low RD high time BYTE change to RD low(4) A0 and A1 to CONV low A0 and A1 hold to CONV high
:
ADS8342IB MIN
: :
SYMBOL tCONV tACQ tC1 tW1 tW2 tD1 tW3 tD2 tD3 tD4 tD5 tD6 tD7 tW4 tW5 tD8 tD9 tD10 tD11 tW6 tD12 tD13 tD14
MIN 17 3 0.2 25 40 40 40 0
MAX
MAX
UNIT tC1 tC1
2
: : : : : :
:
s ns ns ns ns ns
70 80 60 0 0 40 40 25 0 5 1.5 40 20 40 10
: : : : : : : : : : :
:
ns ns
:
ns ns ns
:
ns ns
:
ns ns ns tC1 ns ns ns ns
Indicates the same specifications as the ADS8342I. (1) All input signals are specified with rise and fall times of 5ns, tR = tF = 5ns (10% to 90% of BVDD), and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram in Figure 2. (3) CS can stay low during conversion. If it is not held low, then CS high to 2nd CS high must be > 80ns (tD4) (4) BYTE is asynchronous. When BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8 appear on DB7-DB0. RD may remain low between changes in BYTE.
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TYPICAL CHARACTERISTICS
At TA = +25C, +AVDD = +DVDD = +5V, BVDD = 5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kHz, unless otherwise noted.
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
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Figure 8
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C, +AVDD = +DVDD = +5V, BVDD = 5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kHz, unless otherwise noted.
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
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TYPICAL CHARACTERISTICS (continued)
At TA = +25C, +AVDD = +DVDD = +5V, BVDD = 5V, VREF = +2.5V, fCLK = 5MHz, and fSAMPLE = 250kHz, unless otherwise noted.
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
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Figure 20
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THEORY OF OPERATION
The ADS8342 is a classic successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive charge redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.5m CMOS process. The architecture and process allow the ADS8342 to acquire and convert an analog signal at up to 250,000 conversions per second, while consuming less than 200mW. The ADS8342 requires an external reference, an external clock, and a dual power source (5V). When a digital interface voltage (BVDD) different from +5V is desired, a triple power source is required (5V and BVDD). The external reference can be between 2V and 2.55V. The value of the reference voltage directly sets the range of the analog input. The external clock can vary between 500kHz (25kHz throughput) and 5MHz (250kHz throughput). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8342. The analog inputs to the ADC consists of two input pins: AINx and COMMON. The positive input to the ADC, AINx, is one of four analog channels (AIN0 to AIN3) and is selected by the front-end multiplexer. When a conversion is initiated, the differential input on these pins is sampled on to the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function.
Figure 21. Simplified Diagram of the Analog Input Table 1. Input Channel Selection
A1 0 0 1 1 A0 0 1 0 1 AIN0 +IN -- -- -- AIN1 -- +IN -- -- AIN2 -- -- +IN -- AIN3 -- -- -- +IN COMMON -IN -IN -IN -IN
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs (Figure 21) is captured on the internal capacitor array.
SAMPLE-AND-HOLD CIRCUIT
The sample-and-hold circuit on the ADS8342 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 16-bit accuracy. The input bandwidth of the sample-and-hold circuit is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 250kHz. Typical aperture delay time, or the time it takes for the ADS8342 to switch from sample mode to hold mode following the start of conversion, is 8ns. The average delta of repeated aperture delay values (also known as aperture jitter) is typically 50ps. These specifications reflect the ability of the ADS8342 to capture AC input signals accurately.
MULTIPLEXER
The ADS8342 has an input multiplexer (MUX) that is used to select the desired positive analog input, and connect the sample-and-hold circuit and ADC to it. MUX address pins A0 and A1 are decoded to select the MUX channel; Table 1 shows information on selecting the input channel. Both the AINx and COMMON input signal voltages are sampled and held simultaneously to provide the best possible noise rejection. Figure 21 shows a block diagram of the input multiplexer on the ADS8342. The differential input of the converter is derived from one of the four inputs in reference to the COMMON pin. Table 1 shows the relationship between the A1 and A0 control bits and the selection of the analog multiplexer. The control bits are provided via input pins; see the Digital Interface section of this data sheet for more details.
ANALOG INPUT
The analog input of ADS8342 is bipolar and pseudo-differential, as shown in Figure 22. The AIN0 to AIN3 and COMMON input pins allow for a differential input signal. The amplitude of the input is the difference between the AINx and COMMON inputs, or AINx - COMMON. Unlike some converters of this type, the COMMON input is not resampled later in the conversion cycle. When the converter goes into hold mode, the voltage difference between AINx and COMMON is captured on the internal capacitor array.
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Figure 22. Pseudo-Differential Input Mode of the ADS8342
The range of the COMMON input is limited to -0.1V to +0.1V. Due to this, the differential input can be used to reject signals that are common to both inputs in the specified range. Thus, the COMMON input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The general method for driving the analog input of the ADS8342 is shown in Figure 23 and Figure 24. The COMMON input is held at the common-mode voltage. The AINx input swings from COMMON - VREF to COMMON + VREF, and the peak-to-peak amplitude is 2 x VREF. Often, a small capacitor (100pF) between the positive and negative inputs helps to match their impedance. To obtain good performance from the ADS8342, the input circuit from Figure 24 is recommended.
Figure 23. Method for Driving the ADS8342
The input current required by the analog inputs depends on a number of factors, such as sample rate, input voltage, and source impedance. Essentially, the current into the ADS8342 analog inputs charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (20pF) to a 16-bit settling level within 3 clock cycles (600ns). When the converter goes into hold mode, the input impedance is greater than 1G. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the COMMON input should not drop below AGND - 0.1V, or exceed AGND + 0.1V. The AINx input must always remain within the range of COMMON - VREF to COMMON + VREF. To minimize noise, low bandwidth input signals or low-pass filters must be used. In each case, care must be taken to ensure that the output impedance of the sources driving the AINx and COMMON inputs are matched.
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Figure 24. Single-Ended Method of Interfacing the ADS8342
REFERENCE AND REFGND INPUTS
The reference input of the ADS8342, REFIN, is buffered with an internal reference amplifier. The reference amplifier buffers the reference input from the switching currents needed to charge and discharge the internal capacitor DAC (CDAC), and therefore, the need to provide an external reference capable of supplying these switching currents is eliminated. The reference ground input, REFGND, is connected directly to the CDAC. During the conversion, currents to charge and discharge the CDAC flow through the REFGND pin. For that reason, it is important that REFGND has a low-impedance connection to ground.
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The external reference voltage sets the analog input voltage range. The ADS8342 can operate with a reference between 2.0V and 2.55V. There are several important implications to this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the least significant bit (LSB) size and is equal to the reference voltage divided by 32,768. This means that any offset or gain error inherent in the ADC appears to increase (in terms of LSB size) as the reference voltage is reduced. For a reference voltage of 2V, the value of the LSB is 61.035V. For a reference voltage of 2.5V, the LSB is 76.294V. The noise inherent in the converter also appears to increase with a lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 1.5LSBs peak-to-peak of potential error to the output code. When the external reference is 2.0V, the potential error contribution from the internal noise is larger (2LSBs). The errors due to the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. To obtain optimum performance from the ADS8342, a 0.22F ceramic capacitor must be connected as close as possible to the REFIN pin, to reduce noise coupling into this high impedance input. Because the reference voltage is internally buffered, a high output impedance reference source can be used without the need for an additional operational amplifier to drive the REFIN pin.
Figure 25. Histogram of 8192 Conversions of a DC Input at Code Transition
NOISE
The transition noise of the ADS8342 is extremely low, as shown in Figure 25 and Figure 26. These histograms were generated by applying a low-noise dc input and initiating 8192 conversions. The digital output of the ADC varies in output code due to the internal noise of the ADS8342. This is true for all 16-bit, SAR-type ADCs. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The 1, 2, and 3 distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise is calculated by dividing the number of codes measured by 6, and yields the 3 distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8342, with less than three output codes for the 3 distribution, will yield < 0.5LSBs of transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50V.
Figure 26. Histogram of 8192 Conversions of a DC Input at Code Center
Note that the effective number of bits (ENOB) figure is calculated based on the ADC signal-to-noise (SNR) ratio with a 10kHz, -0.2dB input signal. SNR is related to ENOB as follows:
SNR = 6.02 x ENOB + 1.76 AVERAGING
The noise of the ADC can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/ n, where n is the number of averages. For example, averaging four conversion results will reduce the transition noise from 0.5LSB to 0.25LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio will improve by 3dB.
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ADS8342
www.ti.com SBAS277 - MAY 2003
DIGITAL INTERFACE
SIGNAL LEVELS
The ADS8342 digital interface accommodates different logic levels. The digital interface circuit is designed to operate using 2.7V to 5.5V logic levels. When the ADS8342 interface power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8342 can be connected directly to another 5V CMOS integrated circuit. If the ADS8342 interface power-supply voltage is in the range of 2.7V to 3.6V, the ADS8342 can be connected directly to another 3.3V LVCMOS integrated circuit. Note that digital inputs must not exceed BVDD by more than +0.3V.
5MHz is available. For example, if a digital signal processor (DSP) uses a 20MHz clock, it is possible to set up the internal clock divider of the ADS8342 to divide the input clock frequency by four, to provide an internal clock speed of 5MHz. Table 2 shows the maximum applicable external clock frequency as a function of the CLKDIV0 and CLKDIV1 signals.
Table 2. Clock Divider Selection
CLOCK RATIO (1:n) 1 2 4 8 MAX INPUT FREQUENCY (MHz) 5 10 20 20 INTERNAL FREQUENCY (MHz) 5 5 5 2.5
CLKDIV1 0 0 1
CLKDIV0 0 1 0 1
TIMING AND CONTROL
The ADS8342 uses a parallel control interface consisting of the following digital input pins: CS, RD, CONV, CLK, BYTE, A0, A1, CLKDIV0, and CLKDIV1. The following pins are digital outputs: BUSY, and DB1 to DB15. See Figure 2 (page 10) for a typical timing diagram. The CS input enables the digital interface of the ADS8342. CS and CONV start a conversion and CS and RD allow the output data to be read. BYTE controls the data output bus width. A0 and A1 select the input MUX channel and CLKDIV0 and CLKDIV1 select the internal clock divider ratio. The ADS8342 needs an external clock, CLK ( pin 11), that controls the conversion rate of the ADC. A typical conversion cycle takes 20 clock cycles: 17 for conversion and 3 for signal acquisition. A 250kHz sample rate can be achieved with a 5MHz external clock and a clock divider ratio of 1. This corresponds to a 4s maximum throughput period. The following list describes some of the pins used: CLK--An external clock must be provided to the ADS8342 via the digital input pin CLK. The frequency of the externally provided clock can be divided down inside the ADS8342 to provide a slower internal clock frequency for the ADS8342. The maximum internal clock frequency is 5MHz. The minimum internal clock period is 200ns (see Figure 2, tC1). The clock duty cycle (HIGH/LOW) for an external clock of 5MHz can range up to 40/60 to 60/40. CLKDIVx--The CLKDIVx digital input pins are decoded to select the clock frequency divider ratio that divides the external clock frequency for use internal to the ADS8342. This feature is useful for systems where a clock rate higher than
1
Note that all timing diagrams and specifications are referenced to a clock divider ratio of 1:1 and an external clock frequency of 5MHz. For higher clock input frequencies, there will be a minor increase in power consumption and a possible increase in noise. BUSY--The digital output signal, BUSY, provides an external indication that a conversion is taking place. BUSY goes high a maximum of 70ns after a conversion is initiated (see Figure 2, tD3) and remains high until the end of the conversion. When BUSY goes low at the end of the conversion, the data from the conversion in progress is latched into the ADC output registers and is ready to be read. The BUSY signal remains low until another conversion is started by bringing CS and CONV low. A0 AND A1--The digital inputs, A0 and A1, are MUX address lines used to select the positive analog input MUX channel to use for conversion. When a conversion is started with CS and CONV, the Ax inputs are latched into registers on the rising edge of CS or CONV. The latched MUX inputs control the state of the MUX for the next conversion following the current conversion. At the end of the conversion, the analog input returns to the sampling mode and samples the MUX channel that was latched during the previous conversion start. BYTE--The BYTE signal can be used in conjunction with the RD signal to control the output data bus width. If BYTE is held low, the ADS8342 operates in 16-bit output mode and the output data is read on pins DB15 to DB0. When an 8-bit bus interface is required, the 16-bit output word can be read using eight data lines by toggling the RD and BYTE signals. The lower eight data output bits are read on output pins D7 to D0 when BYTE is low. The higher eight data output bits are read on the same output pins, D7 to D0, when BYTE is high (see Figure 2).
18
ADS8342
www.ti.com SBAS277 - MAY 2003
START OF A CONVERSION (CS AND CONV)
CS and CONV are NORed together internally and must both be low to start a conversion. Bringing both the CS and CONV signals low for 40ns will start a conversion. Immediately after a conversion is started, the analog inputs, the selected MUX channel input, and the COMMON input are held by the sample-and-hold circuit (8ns). The conversion starts on the next rising edge of the clock signal following the conversion start signal, if the conversion is started at least 40ns before the rising edge of the next clock (see Figure 2, tD1). The CONV signal--and CS if it is not always held low--needs to go high 80ns before the rising edge of the second clock cycle of the conversion in order to reduce noise caused by bus activity on the control interface, which can disturb critical comparator decisions made during the conversion. Once CONV goes high, it has to stay high during the entire conversion period (see Figure 2). After a conversion has been started, the rising edge of either CS or CONV, whichever is first, latches the MUX address on pins A0 and A1 in a register. This address is used to select the channel that will be converted upon the next conversion start. After a conversion is finished (17 clock cycles), the sample-and-hold circuit switches from hold mode to sample mode in order to sample the MUX channel address that was latched during the previous conversion start. The start of the next conversion can be initiated after the input capacitor of the ADS8342 is fully charged. This signal acquisition time depends on the driving amplifier, but should be at least 600ns.
For best performance, none of the input control lines should change state after 80ns prior to the rising edge of the second clock in the conversion, as previously described. READING DATA (RD, CS)--CS and RD are NORed together internally and both must be low to enable the data outputs. During the conversion, the data outputs are tri-state and cannot be read. After a conversion has completed, both CS and RD must be low for at least 40ns (see Figure 2, tW5) to enable the outputs. The output data can be latched into external registers using the rising edge of RD and another conversion can be started 1.5 clocks following the rising edge of RD. Before bringing RD back low for a subsequent read command, it must remain high for at least 40ns (see Figure 2, tW6) When BUSY rises after a conversion is initiated, the data outputs will become tri-state regardless of the state of RD. Noise will be generated when the enabled outputs transition to tri-state, which can affect the results of the conversion. To obtain best performance, it is recommended to read the output data immediately after the BUSY signal goes low at the end of conversion and to bring RD high prior to starting the next conversion.
DATA FORMAT
The output data from the ADS8342 is in binary two's complement (BTC) format (see Figure 27). This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise.
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ADS8342
www.ti.com SBAS277 - MAY 2003
Figure 27. Ideal Conversion Characteristics (VCM = 0V and VREF = 2.5V)
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8342 circuitry. This is particularly true if the ADC is approaching the maximum throughput rate. During the ADC conversion, the basic SAR architecture is sensitive to glitches or sudden changes in the power supply, reference, ground connections, and digital inputs. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. The digital output error can change if the external event changes in time with respect to the CLK input. With this in mind, power to the ADS8342 must be quiet and well bypassed. The 0.1F ceramic bypass capacitors should be placed as close to the device as possible.In
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addition, a 1F to 4.7F capacitor is recommended. If needed, an even larger capacitor and a 5 or 10 series resistor can be used to low-pass filter a noisy supply. The ADS8342 draws very little current from an external reference because the reference voltage is internally buffered. The VREF pin should be bypassed with a 0.22F capacitor. An additional larger capacitor can also be used, if desired. If the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. The REFGND and GND pins should be connected to a quiet ground. In many cases, this will be the analog ground. Avoid connections that are too near to the grounding point of a microcontroller or DSP. The ideal layout should include an analog ground plane dedicated to the converter and associated analog circuitry.
ADS8342
www.ti.com SBAS277 - MAY 2003
APPLICATION INFORMATION
Figure 1 shows a typical connection diagram. Different connection diagrams to DSPs or microcontrollers are shown in Figure 28 thru Figure 31.
Figure 28.
Figure 30.
Figure 29.
Figure 31.
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ADS8342
www.ti.com SBAS277 - MAY 2003
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,50 36 25
0,27 0,17
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,05 MIN 1,05 0,95 Seating Plane 0,75 0,45 12
Gage Plane 0,25 0-7
1,20 MAX
0,08 4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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